Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef _IOAT_HW_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define _IOAT_HW_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) /* PCI Configuration Space Values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define IOAT_MMIO_BAR		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) /* CB device ID's */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define PCI_DEVICE_ID_INTEL_IOAT_IVB0	0x0e20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define PCI_DEVICE_ID_INTEL_IOAT_IVB1	0x0e21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define PCI_DEVICE_ID_INTEL_IOAT_IVB2	0x0e22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define PCI_DEVICE_ID_INTEL_IOAT_IVB3	0x0e23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define PCI_DEVICE_ID_INTEL_IOAT_IVB4	0x0e24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define PCI_DEVICE_ID_INTEL_IOAT_IVB5	0x0e25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define PCI_DEVICE_ID_INTEL_IOAT_IVB6	0x0e26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define PCI_DEVICE_ID_INTEL_IOAT_IVB7	0x0e27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define PCI_DEVICE_ID_INTEL_IOAT_IVB8	0x0e2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define PCI_DEVICE_ID_INTEL_IOAT_IVB9	0x0e2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define PCI_DEVICE_ID_INTEL_IOAT_HSW0	0x2f20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define PCI_DEVICE_ID_INTEL_IOAT_HSW1	0x2f21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define PCI_DEVICE_ID_INTEL_IOAT_HSW2	0x2f22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define PCI_DEVICE_ID_INTEL_IOAT_HSW3	0x2f23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define PCI_DEVICE_ID_INTEL_IOAT_HSW4	0x2f24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define PCI_DEVICE_ID_INTEL_IOAT_HSW5	0x2f25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define PCI_DEVICE_ID_INTEL_IOAT_HSW6	0x2f26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define PCI_DEVICE_ID_INTEL_IOAT_HSW7	0x2f27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define PCI_DEVICE_ID_INTEL_IOAT_HSW8	0x2f2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define PCI_DEVICE_ID_INTEL_IOAT_HSW9	0x2f2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define PCI_DEVICE_ID_INTEL_IOAT_BWD0	0x0C50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define PCI_DEVICE_ID_INTEL_IOAT_BWD1	0x0C51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define PCI_DEVICE_ID_INTEL_IOAT_BWD2	0x0C52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PCI_DEVICE_ID_INTEL_IOAT_BWD3	0x0C53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE0	0x6f50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE1	0x6f51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE2	0x6f52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define PCI_DEVICE_ID_INTEL_IOAT_BDXDE3	0x6f53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define PCI_DEVICE_ID_INTEL_IOAT_BDX0	0x6f20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define PCI_DEVICE_ID_INTEL_IOAT_BDX1	0x6f21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define PCI_DEVICE_ID_INTEL_IOAT_BDX2	0x6f22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define PCI_DEVICE_ID_INTEL_IOAT_BDX3	0x6f23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define PCI_DEVICE_ID_INTEL_IOAT_BDX4	0x6f24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define PCI_DEVICE_ID_INTEL_IOAT_BDX5	0x6f25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define PCI_DEVICE_ID_INTEL_IOAT_BDX6	0x6f26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define PCI_DEVICE_ID_INTEL_IOAT_BDX7	0x6f27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define PCI_DEVICE_ID_INTEL_IOAT_BDX8	0x6f2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define PCI_DEVICE_ID_INTEL_IOAT_BDX9	0x6f2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define PCI_DEVICE_ID_INTEL_IOAT_SKX	0x2021
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define PCI_DEVICE_ID_INTEL_IOAT_ICX	0x0b00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IOAT_VER_1_2            0x12    /* Version 1.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IOAT_VER_2_0            0x20    /* Version 2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define IOAT_VER_3_0            0x30    /* Version 3.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define IOAT_VER_3_2            0x32    /* Version 3.2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IOAT_VER_3_3            0x33    /* Version 3.3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IOAT_VER_3_4		0x34	/* Version 3.4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) int system_has_dca_enabled(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define IOAT_DESC_SZ	64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) struct ioat_dma_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	uint32_t	size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 		uint32_t ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 			unsigned int int_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 			unsigned int src_snoop_dis:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 			unsigned int dest_snoop_dis:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 			unsigned int compl_write:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 			unsigned int fence:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 			unsigned int null:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 			unsigned int src_brk:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 			unsigned int dest_brk:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 			unsigned int bundle:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 			unsigned int dest_dca:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 			unsigned int hint:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 			unsigned int rsvd2:13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 			#define IOAT_OP_COPY 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 			unsigned int op:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 		} ctl_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	uint64_t	src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	uint64_t	dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	uint64_t	next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	uint64_t	rsv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	uint64_t	rsv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	/* store some driver data in an unused portion of the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 		uint64_t	user1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 		uint64_t	tx_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	uint64_t	user2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct ioat_xor_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	uint32_t	size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 		uint32_t ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 			unsigned int int_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 			unsigned int src_snoop_dis:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 			unsigned int dest_snoop_dis:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 			unsigned int compl_write:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 			unsigned int fence:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 			unsigned int src_cnt:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 			unsigned int bundle:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 			unsigned int dest_dca:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 			unsigned int hint:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 			unsigned int rsvd:13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 			#define IOAT_OP_XOR 0x87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 			#define IOAT_OP_XOR_VAL 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 			unsigned int op:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 		} ctl_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	uint64_t	src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	uint64_t	dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	uint64_t	next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	uint64_t	src_addr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	uint64_t	src_addr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	uint64_t	src_addr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	uint64_t	src_addr5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct ioat_xor_ext_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	uint64_t	src_addr6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	uint64_t	src_addr7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	uint64_t	src_addr8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	uint64_t	next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	uint64_t	rsvd[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct ioat_pq_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 		uint32_t	size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 		uint32_t	dwbes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 			unsigned int rsvd:25;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 			unsigned int p_val_err:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 			unsigned int q_val_err:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 			unsigned int rsvd1:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 			unsigned int wbes:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 		} dwbes_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 		uint32_t ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 			unsigned int int_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 			unsigned int src_snoop_dis:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 			unsigned int dest_snoop_dis:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 			unsigned int compl_write:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 			unsigned int fence:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			unsigned int src_cnt:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 			unsigned int bundle:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 			unsigned int dest_dca:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 			unsigned int hint:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 			unsigned int p_disable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 			unsigned int q_disable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 			unsigned int rsvd2:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 			unsigned int wb_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			unsigned int prl_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 			unsigned int rsvd3:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) 			#define IOAT_OP_PQ 0x89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 			#define IOAT_OP_PQ_VAL 0x8a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) 			#define IOAT_OP_PQ_16S 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 			#define IOAT_OP_PQ_VAL_16S 0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 			unsigned int op:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 		} ctl_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	uint64_t	src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 	uint64_t	p_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	uint64_t	next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	uint64_t	src_addr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		uint64_t	src_addr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 		uint64_t	sed_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	uint8_t		coef[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	uint64_t	q_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) struct ioat_pq_ext_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	uint64_t	src_addr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 	uint64_t	src_addr5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	uint64_t	src_addr6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	uint64_t	next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	uint64_t	src_addr7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	uint64_t	src_addr8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	uint64_t	rsvd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct ioat_pq_update_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 	uint32_t	size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 		uint32_t ctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 		struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 			unsigned int int_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 			unsigned int src_snoop_dis:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 			unsigned int dest_snoop_dis:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 			unsigned int compl_write:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 			unsigned int fence:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 			unsigned int src_cnt:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 			unsigned int bundle:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 			unsigned int dest_dca:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 			unsigned int hint:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 			unsigned int p_disable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 			unsigned int q_disable:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 			unsigned int rsvd:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 			unsigned int coef:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 			#define IOAT_OP_PQ_UP 0x8b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 			unsigned int op:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		} ctl_f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	uint64_t	src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	uint64_t	p_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	uint64_t	next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	uint64_t	src_addr2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	uint64_t	p_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 	uint64_t	q_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	uint64_t	q_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct ioat_raw_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	uint64_t	field[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) struct ioat_pq16a_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 	uint8_t coef[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	uint64_t src_addr3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) 	uint64_t src_addr4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	uint64_t src_addr5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	uint64_t src_addr6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	uint64_t src_addr7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	uint64_t src_addr8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	uint64_t src_addr9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct ioat_pq16b_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	uint64_t src_addr10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	uint64_t src_addr11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	uint64_t src_addr12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	uint64_t src_addr13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	uint64_t src_addr14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	uint64_t src_addr15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	uint64_t src_addr16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	uint64_t rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) union ioat_sed_pq_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	struct ioat_pq16a_descriptor a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct ioat_pq16b_descriptor b;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define SED_SIZE	64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct ioat_sed_raw_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	uint64_t	a[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	uint64_t	b[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	uint64_t	c[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #endif