Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright(c) 2004 - 2009 Intel Corporation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #ifndef IOATDMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #define IOATDMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/cache.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/pci_ids.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/circ_buf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include "registers.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include "hw.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define IOAT_DMA_VERSION  "5.00"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define IOAT_DMA_DCA_ANY_CPU		~0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define to_ioatdma_device(dev) container_of(dev, struct ioatdma_device, dma_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define to_dev(ioat_chan) (&(ioat_chan)->ioat_dma->pdev->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define to_pdev(ioat_chan) ((ioat_chan)->ioat_dma->pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define chan_num(ch) ((int)((ch)->reg_base - (ch)->ioat_dma->reg_base) / 0x80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* ioat hardware assumes at least two sources for raid operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define src_cnt_to_sw(x) ((x) + 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define src_cnt_to_hw(x) ((x) - 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define ndest_to_sw(x) ((x) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define ndest_to_hw(x) ((x) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define src16_cnt_to_sw(x) ((x) + 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define src16_cnt_to_hw(x) ((x) - 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * workaround for IOAT ver.3.0 null descriptor issue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * (channel returns error when size is 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define NULL_DESC_BUFFER_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) enum ioat_irq_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 	IOAT_NOIRQ = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	IOAT_MSIX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	IOAT_MSI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	IOAT_INTX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50)  * struct ioatdma_device - internal representation of a IOAT device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51)  * @pdev: PCI-Express device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52)  * @reg_base: MMIO register space base address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53)  * @completion_pool: DMA buffers for completion ops
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54)  * @sed_hw_pool: DMA super descriptor pools
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55)  * @dma_dev: embedded struct dma_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56)  * @version: version of ioatdma device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57)  * @msix_entries: irq handlers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58)  * @idx: per channel data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59)  * @dca: direct cache access context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60)  * @irq_mode: interrupt mode (INTX, MSI, MSIX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61)  * @cap: read DMA capabilities register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) struct ioatdma_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 	void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	struct dma_pool *completion_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define MAX_SED_POOLS	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	struct dma_pool *sed_hw_pool[MAX_SED_POOLS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	struct dma_device dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	u8 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IOAT_MAX_CHANS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	struct msix_entry msix_entries[IOAT_MAX_CHANS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	struct ioatdma_chan *idx[IOAT_MAX_CHANS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	struct dca_provider *dca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	enum ioat_irq_mode irq_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	u32 cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	/* shadow version for CB3.3 chan reset errata workaround */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	u64 msixtba0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	u64 msixdata0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 	u32 msixpba;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IOAT_MAX_ORDER 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define IOAT_MAX_DESCS (1 << IOAT_MAX_ORDER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define IOAT_CHUNK_SIZE (SZ_512K)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define IOAT_DESCS_PER_CHUNK (IOAT_CHUNK_SIZE / IOAT_DESC_SZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) struct ioat_descs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	void *virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	dma_addr_t hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) struct ioatdma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	struct dma_chan dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	void __iomem *reg_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	dma_addr_t last_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	spinlock_t cleanup_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	unsigned long state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	#define IOAT_CHAN_DOWN 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	#define IOAT_COMPLETION_ACK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	#define IOAT_RESET_PENDING 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	#define IOAT_KOBJ_INIT_FAIL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	#define IOAT_RUN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	#define IOAT_CHAN_ACTIVE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	struct timer_list timer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	#define RESET_DELAY msecs_to_jiffies(100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct ioatdma_device *ioat_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	dma_addr_t completion_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	u64 *completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) 	struct tasklet_struct cleanup_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	struct kobject kobj;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* ioat v2 / v3 channel attributes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)  * @xfercap_log; log2 of channel max transfer length (for fast division)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)  * @head: allocated index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)  * @issued: hardware notification point
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)  * @tail: cleanup index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)  * @dmacount: identical to 'head' except for occasionally resetting to zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)  * @alloc_order: log2 of the number of allocated descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)  * @produce: number of descriptors to produce at submit time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)  * @ring: software ring buffer implementation of hardware ring
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)  * @prep_lock: serializes descriptor preparation (producers)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	size_t xfercap_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u16 head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	u16 issued;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	u16 tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u16 dmacount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	u16 alloc_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	u16 produce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	struct ioat_ring_ent **ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	spinlock_t prep_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	struct ioat_descs descs[IOAT_MAX_DESCS / IOAT_DESCS_PER_CHUNK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	int desc_chunks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	int intr_coalesce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	int prev_intr_coalesce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct ioat_sysfs_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	struct attribute attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	ssize_t (*show)(struct dma_chan *, char *);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	ssize_t (*store)(struct dma_chan *, const char *, size_t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)  * struct ioat_sed_ent - wrapper around super extended hardware descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)  * @hw: hardware SED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)  * @dma: dma address for the SED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)  * @parent: point to the dma descriptor that's the parent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)  * @hw_pool: descriptor pool index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct ioat_sed_ent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	struct ioat_sed_raw_descriptor *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 	dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	struct ioat_ring_ent *parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	unsigned int hw_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)  * struct ioat_ring_ent - wrapper around hardware descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)  * @hw: hardware DMA descriptor (for memcpy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)  * @xor: hardware xor descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)  * @xor_ex: hardware xor extension descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)  * @pq: hardware pq descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)  * @pq_ex: hardware pq extension descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)  * @pqu: hardware pq update descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)  * @raw: hardware raw (un-typed) descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  * @txd: the generic software descriptor for all engines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * @len: total transaction length for unmap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  * @result: asynchronous result of validate operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)  * @id: identifier for debug
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)  * @sed: pointer to super extended descriptor sw desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct ioat_ring_ent {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 	union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 		struct ioat_dma_descriptor *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 		struct ioat_xor_descriptor *xor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) 		struct ioat_xor_ext_descriptor *xor_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 		struct ioat_pq_descriptor *pq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 		struct ioat_pq_ext_descriptor *pq_ex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 		struct ioat_pq_update_descriptor *pqu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 		struct ioat_raw_descriptor *raw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	struct dma_async_tx_descriptor txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	enum sum_check_flags *result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	#ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	#endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	struct ioat_sed_ent *sed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) extern const struct sysfs_ops ioat_sysfs_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) extern struct ioat_sysfs_entry ioat_version_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) extern struct ioat_sysfs_entry ioat_cap_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) extern int ioat_pending_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) extern int ioat_ring_alloc_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) extern struct kobj_type ioat_ktype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) extern struct kmem_cache *ioat_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) extern int ioat_ring_max_alloc_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) extern struct kmem_cache *ioat_sed_cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static inline struct ioatdma_chan *to_ioat_chan(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	return container_of(c, struct ioatdma_chan, dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) /* wrapper around hardware descriptor format + additional software fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define set_desc_id(desc, i) ((desc)->id = (i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define desc_id(desc) ((desc)->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define set_desc_id(desc, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define desc_id(desc) (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) __dump_desc_dbg(struct ioatdma_chan *ioat_chan, struct ioat_dma_descriptor *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 		struct dma_async_tx_descriptor *tx, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct device *dev = to_dev(ioat_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	dev_dbg(dev, "desc[%d]: (%#llx->%#llx) cookie: %d flags: %#x"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 		" ctl: %#10.8x (op: %#x int_en: %d compl: %d)\n", id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 		(unsigned long long) tx->phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 		(unsigned long long) hw->next, tx->cookie, tx->flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 		hw->ctl, hw->ctl_f.op, hw->ctl_f.int_en, hw->ctl_f.compl_write);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define dump_desc_dbg(c, d) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	({ if (d) __dump_desc_dbg(c, d->hw, &d->txd, desc_id(d)); 0; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static inline struct ioatdma_chan *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ioat_chan_by_index(struct ioatdma_device *ioat_dma, int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	return ioat_dma->idx[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline u64 ioat_chansts(struct ioatdma_chan *ioat_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	return readq(ioat_chan->reg_base + IOAT_CHANSTS_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) static inline u64 ioat_chansts_to_addr(u64 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	return status & IOAT_CHANSTS_COMPLETED_DESCRIPTOR_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static inline u32 ioat_chanerr(struct ioatdma_chan *ioat_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	return readl(ioat_chan->reg_base + IOAT_CHANERR_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static inline void ioat_suspend(struct ioatdma_chan *ioat_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	u8 ver = ioat_chan->ioat_dma->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	writeb(IOAT_CHANCMD_SUSPEND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	       ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) static inline void ioat_reset(struct ioatdma_chan *ioat_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 	u8 ver = ioat_chan->ioat_dma->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	writeb(IOAT_CHANCMD_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	       ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) static inline bool ioat_reset_pending(struct ioatdma_chan *ioat_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	u8 ver = ioat_chan->ioat_dma->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	u8 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	cmd = readb(ioat_chan->reg_base + IOAT_CHANCMD_OFFSET(ver));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	return (cmd & IOAT_CHANCMD_RESET) == IOAT_CHANCMD_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) static inline bool is_ioat_active(unsigned long status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static inline bool is_ioat_idle(unsigned long status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) static inline bool is_ioat_halted(unsigned long status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_HALTED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) static inline bool is_ioat_suspended(unsigned long status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	return ((status & IOAT_CHANSTS_STATUS) == IOAT_CHANSTS_SUSPENDED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* channel was fatally programmed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) static inline bool is_ioat_bug(unsigned long err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	return !!err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) static inline u32 ioat_ring_size(struct ioatdma_chan *ioat_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	return 1 << ioat_chan->alloc_order;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* count of descriptors in flight with the engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static inline u16 ioat_ring_active(struct ioatdma_chan *ioat_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	return CIRC_CNT(ioat_chan->head, ioat_chan->tail,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 			ioat_ring_size(ioat_chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* count of descriptors pending submission to hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static inline u16 ioat_ring_pending(struct ioatdma_chan *ioat_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 	return CIRC_CNT(ioat_chan->head, ioat_chan->issued,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 			ioat_ring_size(ioat_chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) static inline u32 ioat_ring_space(struct ioatdma_chan *ioat_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	return ioat_ring_size(ioat_chan) - ioat_ring_active(ioat_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static inline u16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) ioat_xferlen_to_descs(struct ioatdma_chan *ioat_chan, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) 	u16 num_descs = len >> ioat_chan->xfercap_log;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) 	num_descs += !!(len & ((1 << ioat_chan->xfercap_log) - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 	return num_descs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static inline struct ioat_ring_ent *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ioat_get_ring_ent(struct ioatdma_chan *ioat_chan, u16 idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) 	return ioat_chan->ring[idx & (ioat_ring_size(ioat_chan) - 1)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) ioat_set_chainaddr(struct ioatdma_chan *ioat_chan, u64 addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	writel(addr & 0x00000000FFFFFFFF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 	       ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_LOW);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	writel(addr >> 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 	       ioat_chan->reg_base + IOAT2_CHAINADDR_OFFSET_HIGH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* IOAT Prep functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) ioat_dma_prep_memcpy_lock(struct dma_chan *c, dma_addr_t dma_dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 			   dma_addr_t dma_src, size_t len, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) ioat_prep_interrupt_lock(struct dma_chan *c, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) ioat_prep_xor(struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 	       unsigned int src_cnt, size_t len, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) ioat_prep_xor_val(struct dma_chan *chan, dma_addr_t *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 		    unsigned int src_cnt, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) 		    enum sum_check_flags *result, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) ioat_prep_pq(struct dma_chan *chan, dma_addr_t *dst, dma_addr_t *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	      unsigned int src_cnt, const unsigned char *scf, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	      unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ioat_prep_pq_val(struct dma_chan *chan, dma_addr_t *pq, dma_addr_t *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 		  unsigned int src_cnt, const unsigned char *scf, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 		  enum sum_check_flags *pqres, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) ioat_prep_pqxor(struct dma_chan *chan, dma_addr_t dst, dma_addr_t *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 		 unsigned int src_cnt, size_t len, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) ioat_prep_pqxor_val(struct dma_chan *chan, dma_addr_t *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 		     unsigned int src_cnt, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 		     enum sum_check_flags *result, unsigned long flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /* IOAT Operation functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) irqreturn_t ioat_dma_do_interrupt(int irq, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) irqreturn_t ioat_dma_do_interrupt_msix(int irq, void *data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) struct ioat_ring_ent **
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) ioat_alloc_ring(struct dma_chan *c, int order, gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) void ioat_start_null_desc(struct ioatdma_chan *ioat_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) void ioat_free_ring_ent(struct ioat_ring_ent *desc, struct dma_chan *chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) int ioat_reset_hw(struct ioatdma_chan *ioat_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) enum dma_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) ioat_tx_status(struct dma_chan *c, dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 		struct dma_tx_state *txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) void ioat_cleanup_event(struct tasklet_struct *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) void ioat_timer_event(struct timer_list *t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int ioat_check_space_lock(struct ioatdma_chan *ioat_chan, int num_descs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) void ioat_issue_pending(struct dma_chan *chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /* IOAT Init functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) bool is_bwd_ioat(struct pci_dev *pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) struct dca_provider *ioat_dca_init(struct pci_dev *pdev, void __iomem *iobase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) void ioat_kobject_add(struct ioatdma_device *ioat_dma, struct kobj_type *type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) void ioat_kobject_del(struct ioatdma_device *ioat_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) int ioat_dma_setup_interrupts(struct ioatdma_device *ioat_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) void ioat_stop(struct ioatdma_chan *ioat_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #endif /* IOATDMA_H */