^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // drivers/dma/imx-sdma.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // This file contains a driver for the Freescale Smart DMA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Based on code from Freescale:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) // Copyright 2004-2009 Freescale Semiconductor, Inc. All Rights Reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/sched.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/semaphore.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/firmware.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <linux/platform_data/dma-imx-sdma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <linux/platform_data/dma-imx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #include "dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #include "virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* SDMA registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SDMA_H_C0PTR 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SDMA_H_INTR 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SDMA_H_STATSTOP 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SDMA_H_START 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SDMA_H_EVTOVR 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SDMA_H_DSPOVR 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SDMA_H_HOSTOVR 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SDMA_H_EVTPEND 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SDMA_H_DSPENBL 0x020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SDMA_H_RESET 0x024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SDMA_H_EVTERR 0x028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SDMA_H_INTRMSK 0x02c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SDMA_H_PSW 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SDMA_H_EVTERRDBG 0x034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SDMA_H_CONFIG 0x038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SDMA_ONCE_ENB 0x040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SDMA_ONCE_DATA 0x044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SDMA_ONCE_INSTR 0x048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SDMA_ONCE_STAT 0x04c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SDMA_ONCE_CMD 0x050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SDMA_EVT_MIRROR 0x054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SDMA_ILLINSTADDR 0x058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SDMA_CHN0ADDR 0x05c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SDMA_ONCE_RTB 0x060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SDMA_XTRIG_CONF1 0x070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SDMA_XTRIG_CONF2 0x074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SDMA_CHNENBL0_IMX35 0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SDMA_CHNENBL0_IMX31 0x080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SDMA_CHNPRI_0 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * Buffer descriptor status values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define BD_DONE 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define BD_WRAP 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define BD_CONT 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define BD_INTR 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define BD_RROR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define BD_LAST 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define BD_EXTD 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * Data Node descriptor status values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DND_END_OF_FRAME 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DND_END_OF_XFER 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DND_DONE 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DND_UNUSED 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * IPCV2 descriptor status values.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BD_IPCV2_END_OF_FRAME 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IPCV2_MAX_NODES 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * Error bit set in the CCB status field by the SDMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * in setbd routine, in case of a transfer error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DATA_ERROR 0x10000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * Buffer descriptor commands.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define C0_ADDR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define C0_LOAD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define C0_DUMP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define C0_SETCTX 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define C0_GETCTX 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define C0_SETDM 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define C0_SETPM 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define C0_GETDM 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define C0_GETPM 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * Change endianness indicator in the BD command field
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CHANGE_ENDIANNESS 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * p_2_p watermark_level description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * Bits Name Description
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * 0-7 Lower WML Lower watermark level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * 8 PS 1: Pad Swallowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * 0: No Pad Swallowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * 9 PA 1: Pad Adding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * 0: No Pad Adding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * 10 SPDIF If this bit is set both source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * and destination are on SPBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * 11 Source Bit(SP) 1: Source on SPBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * 0: Source on AIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * 12 Destination Bit(DP) 1: Destination on SPBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * 0: Destination on AIPS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * 13-15 --------- MUST BE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * 16-23 Higher WML HWML
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * 24-27 N Total number of samples after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * which Pad adding/Swallowing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * must be done. It must be odd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * 28 Lower WML Event(LWE) SDMA events reg to check for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * LWML event mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * 0: LWE in EVENTS register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * 1: LWE in EVENTS2 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * 29 Higher WML Event(HWE) SDMA events reg to check for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * HWML event mask
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * 0: HWE in EVENTS register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * 1: HWE in EVENTS2 register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * 30 --------- MUST BE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * 31 CONT 1: Amount of samples to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * transferred is unknown and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * script will keep on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * transferring samples as long as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * both events are detected and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * script must be manually stopped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * by the application
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * 0: The amount of samples to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * transferred is equal to the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * count field of mode word
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define SDMA_WATERMARK_LEVEL_LWML 0xFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define SDMA_WATERMARK_LEVEL_PS BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define SDMA_WATERMARK_LEVEL_PA BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define SDMA_WATERMARK_LEVEL_SPDIF BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SDMA_WATERMARK_LEVEL_SP BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SDMA_WATERMARK_LEVEL_DP BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SDMA_WATERMARK_LEVEL_HWML (0xFF << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SDMA_WATERMARK_LEVEL_LWE BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SDMA_WATERMARK_LEVEL_HWE BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SDMA_WATERMARK_LEVEL_CONT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SDMA_DMA_DIRECTIONS (BIT(DMA_DEV_TO_MEM) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) BIT(DMA_MEM_TO_DEV) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) BIT(DMA_DEV_TO_DEV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * Mode/Count of data node descriptors - IPCv2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct sdma_mode_count {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SDMA_BD_MAX_CNT 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 count : 16; /* size of the buffer pointed by this BD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 status : 8; /* E,R,I,C,W,D status bits stored here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 command : 8; /* command mostly used for channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * Buffer descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct sdma_buffer_descriptor {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct sdma_mode_count mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 buffer_addr; /* address of the buffer described */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 ext_buffer_addr; /* extended buffer address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * struct sdma_channel_control - Channel control Block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @current_bd_ptr: current buffer descriptor processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @base_bd_ptr: first element of buffer descriptor array
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * @unused: padding. The SDMA engine expects an array of 128 byte
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * control blocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct sdma_channel_control {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 current_bd_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 base_bd_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 unused[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * struct sdma_state_registers - SDMA context for a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @pc: program counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @unused1: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @t: test bit: status of arithmetic & test instruction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @rpc: return program counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @unused0: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @sf: source fault while loading data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @spc: loop start program counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @unused2: unused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @df: destination fault while storing data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @epc: loop end program counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @lm: loop mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct sdma_state_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) u32 pc :14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u32 unused1: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 t : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 rpc :14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 unused0: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u32 sf : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u32 spc :14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 unused2: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 df : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u32 epc :14;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 lm : 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * struct sdma_context_data - sdma context specific to a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * @channel_state: channel state bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * @gReg: general registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * @mda: burst dma destination address register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * @msa: burst dma source address register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * @ms: burst dma status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) * @md: burst dma data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @pda: peripheral dma destination address register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * @psa: peripheral dma source address register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @ps: peripheral dma status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @pd: peripheral dma data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @ca: CRC polynomial register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * @cs: CRC accumulator register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @dda: dedicated core destination address register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * @dsa: dedicated core source address register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * @ds: dedicated core status register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * @dd: dedicated core data register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * @scratch0: 1st word of dedicated ram for context switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * @scratch1: 2nd word of dedicated ram for context switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * @scratch2: 3rd word of dedicated ram for context switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * @scratch3: 4th word of dedicated ram for context switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @scratch4: 5th word of dedicated ram for context switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * @scratch5: 6th word of dedicated ram for context switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * @scratch6: 7th word of dedicated ram for context switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * @scratch7: 8th word of dedicated ram for context switch
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct sdma_context_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct sdma_state_registers channel_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 gReg[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 mda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 msa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 md;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 pda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 psa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) u32 ps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) u32 ca;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u32 cs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u32 dda;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u32 dsa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u32 ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) u32 scratch0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) u32 scratch1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) u32 scratch2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u32 scratch3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u32 scratch4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) u32 scratch5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) u32 scratch6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u32 scratch7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) } __attribute__ ((packed));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct sdma_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * struct sdma_desc - descriptor structor for one transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * @vd: descriptor for virt dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * @num_bd: number of descriptors currently handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @bd_phys: physical address of bd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * @buf_tail: ID of the buffer that was processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * @buf_ptail: ID of the previous buffer that was processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * @period_len: period length, used in cyclic.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @chn_real_count: the real count updated from bd->mode.count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * @chn_count: the transfer count set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * @sdmac: sdma_channel pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * @bd: pointer of allocate bd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct sdma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct virt_dma_desc vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int num_bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) dma_addr_t bd_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) unsigned int buf_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) unsigned int buf_ptail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) unsigned int period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned int chn_real_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int chn_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) struct sdma_channel *sdmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) struct sdma_buffer_descriptor *bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * struct sdma_channel - housekeeping for a SDMA channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * @vc: virt_dma base structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * @desc: sdma description including vd and other special member
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * @sdma: pointer to the SDMA engine for this channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) * @channel: the channel number, matches dmaengine chan_id + 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * @direction: transfer type. Needed for setting SDMA script
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * @slave_config: Slave configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * @peripheral_type: Peripheral type. Needed for setting SDMA script
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * @event_id0: aka dma request line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * @event_id1: for channels that use 2 events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * @word_size: peripheral access size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * @pc_from_device: script address for those device_2_memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * @pc_to_device: script address for those memory_2_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * @device_to_device: script address for those device_2_device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @pc_to_pc: script address for those memory_2_memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @flags: loop mode or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) * @per_address: peripheral source or destination address in common case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) * destination address in p_2_p case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) * @per_address2: peripheral source address in p_2_p case
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) * @event_mask: event mask used in p_2_p script
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) * @watermark_level: value for gReg[7], some script will extend it from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * basic watermark such as p_2_p
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * @shp_addr: value for gReg[6]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @per_addr: value for gReg[2]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * @status: status of dma channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * @context_loaded: ensure context is only loaded once
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * @data: specific sdma interface structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) * @bd_pool: dma_pool for bd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) * @terminate_worker: used to call back into terminate work function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct sdma_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) struct virt_dma_chan vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) struct sdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct sdma_engine *sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) unsigned int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) enum dma_transfer_direction direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct dma_slave_config slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) enum sdma_peripheral_type peripheral_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) unsigned int event_id0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned int event_id1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) enum dma_slave_buswidth word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) unsigned int pc_from_device, pc_to_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) unsigned int device_to_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned int pc_to_pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dma_addr_t per_address, per_address2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) unsigned long event_mask[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) unsigned long watermark_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u32 shp_addr, per_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct imx_dma_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct work_struct terminate_worker;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define IMX_DMA_SG_LOOP BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define MAX_DMA_CHANNELS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define MXC_SDMA_DEFAULT_PRIORITY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define MXC_SDMA_MIN_PRIORITY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define MXC_SDMA_MAX_PRIORITY 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SDMA_FIRMWARE_MAGIC 0x414d4453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * struct sdma_firmware_header - Layout of the firmware image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * @magic: "SDMA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * @version_major: increased whenever layout of struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) * sdma_script_start_addrs changes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * @version_minor: firmware minor version (for binary compatible changes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * @script_addrs_start: offset of struct sdma_script_start_addrs in this image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) * @num_script_addrs: Number of script addresses in this image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) * @ram_code_start: offset of SDMA ram image in this firmware image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) * @ram_code_size: size of SDMA ram image
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * @script_addrs: Stores the start address of the SDMA scripts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * (in SDMA memory space)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct sdma_firmware_header {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 magic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 version_major;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) u32 version_minor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) u32 script_addrs_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) u32 num_script_addrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) u32 ram_code_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) u32 ram_code_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct sdma_driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) int chnenbl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) int num_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct sdma_script_start_addrs *script_addrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) bool check_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct sdma_engine {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct sdma_channel channel[MAX_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct sdma_channel_control *channel_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) struct sdma_context_data *context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dma_addr_t context_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct dma_device dma_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct clk *clk_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) spinlock_t channel_0_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) u32 script_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct sdma_script_start_addrs *script_addrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) const struct sdma_driver_data *drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) u32 spba_start_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) u32 spba_end_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) dma_addr_t bd0_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct sdma_buffer_descriptor *bd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /* clock ratio for AHB:SDMA core. 1:1 is 1, 2:1 is 0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) bool clk_ratio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) static int sdma_config_write(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) struct dma_slave_config *dmaengine_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) enum dma_transfer_direction direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) static struct sdma_driver_data sdma_imx31 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) .chnenbl0 = SDMA_CHNENBL0_IMX31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) .num_events = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static struct sdma_script_start_addrs sdma_script_imx25 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) .ap_2_ap_addr = 729,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) .uart_2_mcu_addr = 904,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) .per_2_app_addr = 1255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) .mcu_2_app_addr = 834,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) .uartsh_2_mcu_addr = 1120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) .per_2_shp_addr = 1329,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .mcu_2_shp_addr = 1048,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) .ata_2_mcu_addr = 1560,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) .mcu_2_ata_addr = 1479,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) .app_2_per_addr = 1189,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) .app_2_mcu_addr = 770,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) .shp_2_per_addr = 1407,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) .shp_2_mcu_addr = 979,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) static struct sdma_driver_data sdma_imx25 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .chnenbl0 = SDMA_CHNENBL0_IMX35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .num_events = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .script_addrs = &sdma_script_imx25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static struct sdma_driver_data sdma_imx35 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .chnenbl0 = SDMA_CHNENBL0_IMX35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .num_events = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) static struct sdma_script_start_addrs sdma_script_imx51 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .ap_2_ap_addr = 642,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .uart_2_mcu_addr = 817,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .mcu_2_app_addr = 747,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .mcu_2_shp_addr = 961,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .ata_2_mcu_addr = 1473,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .mcu_2_ata_addr = 1392,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .app_2_per_addr = 1033,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .app_2_mcu_addr = 683,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .shp_2_per_addr = 1251,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .shp_2_mcu_addr = 892,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static struct sdma_driver_data sdma_imx51 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .chnenbl0 = SDMA_CHNENBL0_IMX35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) .num_events = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) .script_addrs = &sdma_script_imx51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static struct sdma_script_start_addrs sdma_script_imx53 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) .ap_2_ap_addr = 642,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) .app_2_mcu_addr = 683,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) .mcu_2_app_addr = 747,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) .uart_2_mcu_addr = 817,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) .shp_2_mcu_addr = 891,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) .mcu_2_shp_addr = 960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) .uartsh_2_mcu_addr = 1032,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) .spdif_2_mcu_addr = 1100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) .mcu_2_spdif_addr = 1134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) .firi_2_mcu_addr = 1193,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) .mcu_2_firi_addr = 1290,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static struct sdma_driver_data sdma_imx53 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) .chnenbl0 = SDMA_CHNENBL0_IMX35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) .num_events = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) .script_addrs = &sdma_script_imx53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static struct sdma_script_start_addrs sdma_script_imx6q = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) .ap_2_ap_addr = 642,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) .uart_2_mcu_addr = 817,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) .mcu_2_app_addr = 747,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) .per_2_per_addr = 6331,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) .uartsh_2_mcu_addr = 1032,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) .mcu_2_shp_addr = 960,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) .app_2_mcu_addr = 683,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) .shp_2_mcu_addr = 891,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) .spdif_2_mcu_addr = 1100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .mcu_2_spdif_addr = 1134,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) static struct sdma_driver_data sdma_imx6q = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) .chnenbl0 = SDMA_CHNENBL0_IMX35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) .num_events = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) .script_addrs = &sdma_script_imx6q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) static struct sdma_script_start_addrs sdma_script_imx7d = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) .ap_2_ap_addr = 644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) .uart_2_mcu_addr = 819,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) .mcu_2_app_addr = 749,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) .uartsh_2_mcu_addr = 1034,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) .mcu_2_shp_addr = 962,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) .app_2_mcu_addr = 685,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) .shp_2_mcu_addr = 893,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) .spdif_2_mcu_addr = 1102,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) .mcu_2_spdif_addr = 1136,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) static struct sdma_driver_data sdma_imx7d = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) .chnenbl0 = SDMA_CHNENBL0_IMX35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) .num_events = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) .script_addrs = &sdma_script_imx7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) static struct sdma_driver_data sdma_imx8mq = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) .chnenbl0 = SDMA_CHNENBL0_IMX35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) .num_events = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) .script_addrs = &sdma_script_imx7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) .check_ratio = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static const struct platform_device_id sdma_devtypes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) .name = "imx25-sdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) .driver_data = (unsigned long)&sdma_imx25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) .name = "imx31-sdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) .driver_data = (unsigned long)&sdma_imx31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .name = "imx35-sdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .driver_data = (unsigned long)&sdma_imx35,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .name = "imx51-sdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) .driver_data = (unsigned long)&sdma_imx51,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) .name = "imx53-sdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) .driver_data = (unsigned long)&sdma_imx53,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .name = "imx6q-sdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .driver_data = (unsigned long)&sdma_imx6q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .name = "imx7d-sdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) .driver_data = (unsigned long)&sdma_imx7d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) .name = "imx8mq-sdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .driver_data = (unsigned long)&sdma_imx8mq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) MODULE_DEVICE_TABLE(platform, sdma_devtypes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) static const struct of_device_id sdma_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) { .compatible = "fsl,imx6q-sdma", .data = &sdma_imx6q, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) { .compatible = "fsl,imx53-sdma", .data = &sdma_imx53, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) { .compatible = "fsl,imx51-sdma", .data = &sdma_imx51, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) { .compatible = "fsl,imx35-sdma", .data = &sdma_imx35, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) { .compatible = "fsl,imx31-sdma", .data = &sdma_imx31, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) { .compatible = "fsl,imx25-sdma", .data = &sdma_imx25, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) { .compatible = "fsl,imx7d-sdma", .data = &sdma_imx7d, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) { .compatible = "fsl,imx8mq-sdma", .data = &sdma_imx8mq, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) MODULE_DEVICE_TABLE(of, sdma_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define SDMA_H_CONFIG_DSPDMA BIT(12) /* indicates if the DSPDMA is used */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define SDMA_H_CONFIG_RTD_PINS BIT(11) /* indicates if Real-Time Debug pins are enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define SDMA_H_CONFIG_ACR BIT(4) /* indicates if AHB freq /core freq = 2 or 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define SDMA_H_CONFIG_CSM (3) /* indicates which context switch mode is selected*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static inline u32 chnenbl_ofs(struct sdma_engine *sdma, unsigned int event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u32 chnenbl0 = sdma->drvdata->chnenbl0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) return chnenbl0 + event * 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) static int sdma_config_ownership(struct sdma_channel *sdmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) bool event_override, bool mcu_override, bool dsp_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct sdma_engine *sdma = sdmac->sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) int channel = sdmac->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) unsigned long evt, mcu, dsp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (event_override && mcu_override && dsp_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) evt = readl_relaxed(sdma->regs + SDMA_H_EVTOVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) mcu = readl_relaxed(sdma->regs + SDMA_H_HOSTOVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) dsp = readl_relaxed(sdma->regs + SDMA_H_DSPOVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) if (dsp_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) __clear_bit(channel, &dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) __set_bit(channel, &dsp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) if (event_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) __clear_bit(channel, &evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) __set_bit(channel, &evt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (mcu_override)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) __clear_bit(channel, &mcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) __set_bit(channel, &mcu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) writel_relaxed(evt, sdma->regs + SDMA_H_EVTOVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) writel_relaxed(mcu, sdma->regs + SDMA_H_HOSTOVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) writel_relaxed(dsp, sdma->regs + SDMA_H_DSPOVR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static void sdma_enable_channel(struct sdma_engine *sdma, int channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) writel(BIT(channel), sdma->regs + SDMA_H_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) * sdma_run_channel0 - run a channel and wait till it's done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) static int sdma_run_channel0(struct sdma_engine *sdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) sdma_enable_channel(sdma, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = readl_relaxed_poll_timeout_atomic(sdma->regs + SDMA_H_STATSTOP,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) reg, !(reg & 1), 1, 500);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) dev_err(sdma->dev, "Timeout waiting for CH0 ready\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /* Set bits of CONFIG register with dynamic context switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) reg = readl(sdma->regs + SDMA_H_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if ((reg & SDMA_H_CONFIG_CSM) == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) reg |= SDMA_H_CONFIG_CSM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) writel_relaxed(reg, sdma->regs + SDMA_H_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static int sdma_load_script(struct sdma_engine *sdma, void *buf, int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) u32 address)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) struct sdma_buffer_descriptor *bd0 = sdma->bd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) void *buf_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) dma_addr_t buf_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) buf_virt = dma_alloc_coherent(sdma->dev, size, &buf_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (!buf_virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) spin_lock_irqsave(&sdma->channel_0_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) bd0->mode.command = C0_SETPM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) bd0->mode.count = size / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) bd0->buffer_addr = buf_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) bd0->ext_buffer_addr = address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) memcpy(buf_virt, buf, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) ret = sdma_run_channel0(sdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) dma_free_coherent(sdma->dev, size, buf_virt, buf_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) struct sdma_engine *sdma = sdmac->sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) int channel = sdmac->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) u32 chnenbl = chnenbl_ofs(sdma, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) val = readl_relaxed(sdma->regs + chnenbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) __set_bit(channel, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) writel_relaxed(val, sdma->regs + chnenbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct sdma_engine *sdma = sdmac->sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) int channel = sdmac->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) u32 chnenbl = chnenbl_ofs(sdma, event);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) val = readl_relaxed(sdma->regs + chnenbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) __clear_bit(channel, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) writel_relaxed(val, sdma->regs + chnenbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static struct sdma_desc *to_sdma_desc(struct dma_async_tx_descriptor *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return container_of(t, struct sdma_desc, vd.tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void sdma_start_desc(struct sdma_channel *sdmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct virt_dma_desc *vd = vchan_next_desc(&sdmac->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct sdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct sdma_engine *sdma = sdmac->sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int channel = sdmac->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (!vd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) sdmac->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) sdmac->desc = desc = to_sdma_desc(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) list_del(&vd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) sdma->channel_control[channel].base_bd_ptr = desc->bd_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) sdma->channel_control[channel].current_bd_ptr = desc->bd_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) sdma_enable_channel(sdma, sdmac->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) static void sdma_update_channel_loop(struct sdma_channel *sdmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct sdma_buffer_descriptor *bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) int error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) enum dma_status old_status = sdmac->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) * loop mode. Iterate over descriptors, re-setup them and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) * call callback function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) while (sdmac->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct sdma_desc *desc = sdmac->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) bd = &desc->bd[desc->buf_tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) if (bd->mode.status & BD_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (bd->mode.status & BD_RROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) bd->mode.status &= ~BD_RROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) sdmac->status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) * We use bd->mode.count to calculate the residue, since contains
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) * the number of bytes present in the current buffer descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) desc->chn_real_count = bd->mode.count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) bd->mode.status |= BD_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) bd->mode.count = desc->period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) desc->buf_ptail = desc->buf_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) desc->buf_tail = (desc->buf_tail + 1) % desc->num_bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) * The callback is called from the interrupt context in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) * to reduce latency and to avoid the risk of altering the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) * SDMA transaction status by the time the client tasklet is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) * executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) spin_unlock(&sdmac->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dmaengine_desc_get_callback_invoke(&desc->vd.tx, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) spin_lock(&sdmac->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) sdmac->status = old_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static void mxc_sdma_handle_channel_normal(struct sdma_channel *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct sdma_channel *sdmac = (struct sdma_channel *) data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct sdma_buffer_descriptor *bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) int i, error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) sdmac->desc->chn_real_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) * non loop mode. Iterate over all descriptors, collect
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) * errors and call callback function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) for (i = 0; i < sdmac->desc->num_bd; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) bd = &sdmac->desc->bd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (bd->mode.status & (BD_DONE | BD_RROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) error = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) sdmac->desc->chn_real_count += bd->mode.count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) sdmac->status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) sdmac->status = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static irqreturn_t sdma_int_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) struct sdma_engine *sdma = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) unsigned long stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) stat = readl_relaxed(sdma->regs + SDMA_H_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) writel_relaxed(stat, sdma->regs + SDMA_H_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* channel 0 is special and not handled here, see run_channel0() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) stat &= ~1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) while (stat) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) int channel = fls(stat) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) struct sdma_channel *sdmac = &sdma->channel[channel];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct sdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) spin_lock(&sdmac->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) desc = sdmac->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) if (desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (sdmac->flags & IMX_DMA_SG_LOOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) sdma_update_channel_loop(sdmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) mxc_sdma_handle_channel_normal(sdmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) vchan_cookie_complete(&desc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) sdma_start_desc(sdmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) spin_unlock(&sdmac->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) __clear_bit(channel, &stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) * sets the pc of SDMA script according to the peripheral type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) static void sdma_get_pc(struct sdma_channel *sdmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) enum sdma_peripheral_type peripheral_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) struct sdma_engine *sdma = sdmac->sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) int per_2_emi = 0, emi_2_per = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * These are needed once we start to support transfers between
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * two peripherals or memory-to-memory transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int per_2_per = 0, emi_2_emi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) sdmac->pc_from_device = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) sdmac->pc_to_device = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) sdmac->device_to_device = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) sdmac->pc_to_pc = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) switch (peripheral_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) case IMX_DMATYPE_MEMORY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) emi_2_emi = sdma->script_addrs->ap_2_ap_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) case IMX_DMATYPE_DSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) emi_2_per = sdma->script_addrs->bp_2_ap_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) per_2_emi = sdma->script_addrs->ap_2_bp_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) case IMX_DMATYPE_FIRI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) per_2_emi = sdma->script_addrs->firi_2_mcu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) emi_2_per = sdma->script_addrs->mcu_2_firi_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) case IMX_DMATYPE_UART:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) per_2_emi = sdma->script_addrs->uart_2_mcu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) emi_2_per = sdma->script_addrs->mcu_2_app_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) case IMX_DMATYPE_UART_SP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) per_2_emi = sdma->script_addrs->uartsh_2_mcu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) case IMX_DMATYPE_ATA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) per_2_emi = sdma->script_addrs->ata_2_mcu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) emi_2_per = sdma->script_addrs->mcu_2_ata_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) case IMX_DMATYPE_CSPI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) case IMX_DMATYPE_EXT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) case IMX_DMATYPE_SSI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) case IMX_DMATYPE_SAI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) per_2_emi = sdma->script_addrs->app_2_mcu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) emi_2_per = sdma->script_addrs->mcu_2_app_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) case IMX_DMATYPE_SSI_DUAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) per_2_emi = sdma->script_addrs->ssish_2_mcu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) emi_2_per = sdma->script_addrs->mcu_2_ssish_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) case IMX_DMATYPE_SSI_SP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) case IMX_DMATYPE_MMC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) case IMX_DMATYPE_SDHC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) case IMX_DMATYPE_CSPI_SP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) case IMX_DMATYPE_ESAI:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) case IMX_DMATYPE_MSHC_SP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) case IMX_DMATYPE_ASRC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) per_2_emi = sdma->script_addrs->asrc_2_mcu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) emi_2_per = sdma->script_addrs->asrc_2_mcu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) per_2_per = sdma->script_addrs->per_2_per_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) case IMX_DMATYPE_ASRC_SP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) per_2_emi = sdma->script_addrs->shp_2_mcu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) emi_2_per = sdma->script_addrs->mcu_2_shp_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) per_2_per = sdma->script_addrs->per_2_per_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) case IMX_DMATYPE_MSHC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) per_2_emi = sdma->script_addrs->mshc_2_mcu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) emi_2_per = sdma->script_addrs->mcu_2_mshc_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) case IMX_DMATYPE_CCM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) per_2_emi = sdma->script_addrs->dptc_dvfs_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) case IMX_DMATYPE_SPDIF:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) per_2_emi = sdma->script_addrs->spdif_2_mcu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) emi_2_per = sdma->script_addrs->mcu_2_spdif_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) case IMX_DMATYPE_IPU_MEMORY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) sdmac->pc_from_device = per_2_emi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) sdmac->pc_to_device = emi_2_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) sdmac->device_to_device = per_2_per;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) sdmac->pc_to_pc = emi_2_emi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) static int sdma_load_context(struct sdma_channel *sdmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) struct sdma_engine *sdma = sdmac->sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) int channel = sdmac->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) int load_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) struct sdma_context_data *context = sdma->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) struct sdma_buffer_descriptor *bd0 = sdma->bd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (sdmac->direction == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) load_address = sdmac->pc_from_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) else if (sdmac->direction == DMA_DEV_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) load_address = sdmac->device_to_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) else if (sdmac->direction == DMA_MEM_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) load_address = sdmac->pc_to_pc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) load_address = sdmac->pc_to_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (load_address < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return load_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) dev_dbg(sdma->dev, "load_address = %d\n", load_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dev_dbg(sdma->dev, "wml = 0x%08x\n", (u32)sdmac->watermark_level);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) dev_dbg(sdma->dev, "shp_addr = 0x%08x\n", sdmac->shp_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) dev_dbg(sdma->dev, "per_addr = 0x%08x\n", sdmac->per_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) dev_dbg(sdma->dev, "event_mask0 = 0x%08x\n", (u32)sdmac->event_mask[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dev_dbg(sdma->dev, "event_mask1 = 0x%08x\n", (u32)sdmac->event_mask[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) spin_lock_irqsave(&sdma->channel_0_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) memset(context, 0, sizeof(*context));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) context->channel_state.pc = load_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) /* Send by context the event mask,base address for peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * and watermark level
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) context->gReg[0] = sdmac->event_mask[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) context->gReg[1] = sdmac->event_mask[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) context->gReg[2] = sdmac->per_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) context->gReg[6] = sdmac->shp_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) context->gReg[7] = sdmac->watermark_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) bd0->mode.command = C0_SETDM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) bd0->mode.status = BD_DONE | BD_WRAP | BD_EXTD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) bd0->mode.count = sizeof(*context) / 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) bd0->buffer_addr = sdma->context_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) bd0->ext_buffer_addr = 2048 + (sizeof(*context) / 4) * channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) ret = sdma_run_channel0(sdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) spin_unlock_irqrestore(&sdma->channel_0_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static struct sdma_channel *to_sdma_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) return container_of(chan, struct sdma_channel, vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) static int sdma_disable_channel(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct sdma_channel *sdmac = to_sdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct sdma_engine *sdma = sdmac->sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) int channel = sdmac->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) writel_relaxed(BIT(channel), sdma->regs + SDMA_H_STATSTOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) sdmac->status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static void sdma_channel_terminate_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct sdma_channel *sdmac = container_of(work, struct sdma_channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) terminate_worker);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) * According to NXP R&D team a delay of one BD SDMA cost time
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) * (maximum is 1ms) should be added after disable of the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) * bit, to ensure SDMA core has really been stopped after SDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) * clients call .device_terminate_all.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) usleep_range(1000, 2000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) spin_lock_irqsave(&sdmac->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) vchan_get_all_descriptors(&sdmac->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) spin_unlock_irqrestore(&sdmac->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) vchan_dma_desc_free_list(&sdmac->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) static int sdma_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct sdma_channel *sdmac = to_sdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) spin_lock_irqsave(&sdmac->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) sdma_disable_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (sdmac->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) vchan_terminate_vdesc(&sdmac->desc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) sdmac->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) schedule_work(&sdmac->terminate_worker);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) spin_unlock_irqrestore(&sdmac->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static void sdma_channel_synchronize(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) struct sdma_channel *sdmac = to_sdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) vchan_synchronize(&sdmac->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) flush_work(&sdmac->terminate_worker);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) struct sdma_engine *sdma = sdmac->sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) int lwml = sdmac->watermark_level & SDMA_WATERMARK_LEVEL_LWML;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) int hwml = (sdmac->watermark_level & SDMA_WATERMARK_LEVEL_HWML) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) set_bit(sdmac->event_id0 % 32, &sdmac->event_mask[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) set_bit(sdmac->event_id1 % 32, &sdmac->event_mask[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (sdmac->event_id0 > 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_LWE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (sdmac->event_id1 > 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_HWE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * If LWML(src_maxburst) > HWML(dst_maxburst), we need
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * swap LWML and HWML of INFO(A.3.2.5.1), also need swap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * r0(event_mask[1]) and r1(event_mask[0]).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) if (lwml > hwml) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) sdmac->watermark_level &= ~(SDMA_WATERMARK_LEVEL_LWML |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) SDMA_WATERMARK_LEVEL_HWML);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) sdmac->watermark_level |= hwml;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) sdmac->watermark_level |= lwml << 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) swap(sdmac->event_mask[0], sdmac->event_mask[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) if (sdmac->per_address2 >= sdma->spba_start_addr &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) sdmac->per_address2 <= sdma->spba_end_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) if (sdmac->per_address >= sdma->spba_start_addr &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) sdmac->per_address <= sdma->spba_end_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_DP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) static int sdma_config_channel(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) struct sdma_channel *sdmac = to_sdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) sdma_disable_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) sdmac->event_mask[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) sdmac->event_mask[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) sdmac->shp_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) sdmac->per_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) switch (sdmac->peripheral_type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) case IMX_DMATYPE_DSP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) sdma_config_ownership(sdmac, false, true, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) case IMX_DMATYPE_MEMORY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) sdma_config_ownership(sdmac, false, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) sdma_config_ownership(sdmac, true, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) sdma_get_pc(sdmac, sdmac->peripheral_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) (sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /* Handle multiple event channels differently */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (sdmac->event_id1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) if (sdmac->peripheral_type == IMX_DMATYPE_ASRC_SP ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) sdmac->peripheral_type == IMX_DMATYPE_ASRC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) sdma_set_watermarklevel_for_p2p(sdmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) __set_bit(sdmac->event_id0, sdmac->event_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) /* Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) sdmac->shp_addr = sdmac->per_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) sdmac->per_addr = sdmac->per_address2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) sdmac->watermark_level = 0; /* FIXME: M3_BASE_ADDRESS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static int sdma_set_channel_priority(struct sdma_channel *sdmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) unsigned int priority)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) struct sdma_engine *sdma = sdmac->sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) int channel = sdmac->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (priority < MXC_SDMA_MIN_PRIORITY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) || priority > MXC_SDMA_MAX_PRIORITY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) writel_relaxed(priority, sdma->regs + SDMA_CHNPRI_0 + 4 * channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) static int sdma_request_channel0(struct sdma_engine *sdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) int ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) sdma->bd0 = dma_alloc_coherent(sdma->dev, PAGE_SIZE, &sdma->bd0_phys,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) if (!sdma->bd0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) sdma->channel_control[0].base_bd_ptr = sdma->bd0_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) sdma->channel_control[0].current_bd_ptr = sdma->bd0_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) sdma_set_channel_priority(&sdma->channel[0], MXC_SDMA_DEFAULT_PRIORITY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) static int sdma_alloc_bd(struct sdma_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) desc->bd = dma_alloc_coherent(desc->sdmac->sdma->dev, bd_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) &desc->bd_phys, GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) if (!desc->bd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) static void sdma_free_bd(struct sdma_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) u32 bd_size = desc->num_bd * sizeof(struct sdma_buffer_descriptor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) dma_free_coherent(desc->sdmac->sdma->dev, bd_size, desc->bd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) desc->bd_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static void sdma_desc_free(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) struct sdma_desc *desc = container_of(vd, struct sdma_desc, vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) sdma_free_bd(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) static int sdma_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) struct sdma_channel *sdmac = to_sdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) struct imx_dma_data *data = chan->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) struct imx_dma_data mem_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) int prio, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * MEMCPY may never setup chan->private by filter function such as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * dmatest, thus create 'struct imx_dma_data mem_data' for this case.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * Please note in any other slave case, you have to setup chan->private
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * with 'struct imx_dma_data' in your own filter function if you want to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * request dma channel by dma_request_channel() rather than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) * dma_request_slave_channel(). Othwise, 'MEMCPY in case?' will appear
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) * to warn you to correct your filter function.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) if (!data) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dev_dbg(sdmac->sdma->dev, "MEMCPY in case?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) mem_data.priority = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) mem_data.peripheral_type = IMX_DMATYPE_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) mem_data.dma_request = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) mem_data.dma_request2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) data = &mem_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) switch (data->priority) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) case DMA_PRIO_HIGH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) prio = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) case DMA_PRIO_MEDIUM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) prio = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) case DMA_PRIO_LOW:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) prio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) sdmac->peripheral_type = data->peripheral_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) sdmac->event_id0 = data->dma_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) sdmac->event_id1 = data->dma_request2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) ret = clk_enable(sdmac->sdma->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) ret = clk_enable(sdmac->sdma->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) goto disable_clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) ret = sdma_set_channel_priority(sdmac, prio);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) goto disable_clk_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) disable_clk_ahb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) clk_disable(sdmac->sdma->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) disable_clk_ipg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) clk_disable(sdmac->sdma->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static void sdma_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) struct sdma_channel *sdmac = to_sdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct sdma_engine *sdma = sdmac->sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) sdma_terminate_all(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) sdma_channel_synchronize(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) sdma_event_disable(sdmac, sdmac->event_id0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) if (sdmac->event_id1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) sdma_event_disable(sdmac, sdmac->event_id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) sdmac->event_id0 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) sdmac->event_id1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) sdma_set_channel_priority(sdmac, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) clk_disable(sdma->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) clk_disable(sdma->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) static struct sdma_desc *sdma_transfer_init(struct sdma_channel *sdmac,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) enum dma_transfer_direction direction, u32 bds)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) struct sdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) desc = kzalloc((sizeof(*desc)), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) sdmac->status = DMA_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) sdmac->direction = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) sdmac->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) desc->chn_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) desc->chn_real_count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) desc->buf_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) desc->buf_ptail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) desc->sdmac = sdmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) desc->num_bd = bds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (sdma_alloc_bd(desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) goto err_desc_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) /* No slave_config called in MEMCPY case, so do here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (direction == DMA_MEM_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) sdma_config_ownership(sdmac, false, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) if (sdma_load_context(sdmac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) goto err_desc_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) err_desc_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) static struct dma_async_tx_descriptor *sdma_prep_memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) struct dma_chan *chan, dma_addr_t dma_dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dma_addr_t dma_src, size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) struct sdma_channel *sdmac = to_sdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct sdma_engine *sdma = sdmac->sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) int channel = sdmac->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) size_t count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) int i = 0, param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) struct sdma_buffer_descriptor *bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) struct sdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) if (!chan || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) dev_dbg(sdma->dev, "memcpy: %pad->%pad, len=%zu, channel=%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) &dma_src, &dma_dst, len, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) desc = sdma_transfer_init(sdmac, DMA_MEM_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) len / SDMA_BD_MAX_CNT + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) count = min_t(size_t, len, SDMA_BD_MAX_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) bd = &desc->bd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) bd->buffer_addr = dma_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) bd->ext_buffer_addr = dma_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) bd->mode.count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) desc->chn_count += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) bd->mode.command = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) dma_src += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) dma_dst += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) len -= count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) param = BD_DONE | BD_EXTD | BD_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) /* last bd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) if (!len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) param |= BD_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) param |= BD_LAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) param &= ~BD_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) dev_dbg(sdma->dev, "entry %d: count: %zd dma: 0x%x %s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) i, count, bd->buffer_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) param & BD_WRAP ? "wrap" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) param & BD_INTR ? " intr" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) bd->mode.status = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) } while (len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) static struct dma_async_tx_descriptor *sdma_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct dma_chan *chan, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) unsigned int sg_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) unsigned long flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) struct sdma_channel *sdmac = to_sdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) struct sdma_engine *sdma = sdmac->sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) int i, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) int channel = sdmac->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) struct sdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) sdma_config_write(chan, &sdmac->slave_config, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) desc = sdma_transfer_init(sdmac, direction, sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) dev_dbg(sdma->dev, "setting up %d entries for channel %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) sg_len, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) for_each_sg(sgl, sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) struct sdma_buffer_descriptor *bd = &desc->bd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) int param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) bd->buffer_addr = sg->dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) count = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (count > SDMA_BD_MAX_CNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) dev_err(sdma->dev, "SDMA channel %d: maximum bytes for sg entry exceeded: %d > %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) channel, count, SDMA_BD_MAX_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) goto err_bd_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) bd->mode.count = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) desc->chn_count += count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) goto err_bd_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) switch (sdmac->word_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) bd->mode.command = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (count & 3 || sg->dma_address & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) goto err_bd_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) bd->mode.command = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (count & 1 || sg->dma_address & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) goto err_bd_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) bd->mode.command = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) goto err_bd_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) param = BD_DONE | BD_EXTD | BD_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) if (i + 1 == sg_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) param |= BD_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) param |= BD_LAST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) param &= ~BD_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) dev_dbg(sdma->dev, "entry %d: count: %d dma: %#llx %s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) i, count, (u64)sg->dma_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) param & BD_WRAP ? "wrap" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) param & BD_INTR ? " intr" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) bd->mode.status = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) err_bd_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) sdma_free_bd(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) sdmac->status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) static struct dma_async_tx_descriptor *sdma_prep_dma_cyclic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) size_t period_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct sdma_channel *sdmac = to_sdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) struct sdma_engine *sdma = sdmac->sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) int num_periods = buf_len / period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) int channel = sdmac->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) int i = 0, buf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct sdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) dev_dbg(sdma->dev, "%s channel: %d\n", __func__, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) sdma_config_write(chan, &sdmac->slave_config, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) desc = sdma_transfer_init(sdmac, direction, num_periods);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) desc->period_len = period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) sdmac->flags |= IMX_DMA_SG_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (period_len > SDMA_BD_MAX_CNT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) dev_err(sdma->dev, "SDMA channel %d: maximum period size exceeded: %zu > %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) channel, period_len, SDMA_BD_MAX_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) goto err_bd_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) while (buf < buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) struct sdma_buffer_descriptor *bd = &desc->bd[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) int param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) bd->buffer_addr = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) bd->mode.count = period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) if (sdmac->word_size > DMA_SLAVE_BUSWIDTH_4_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) goto err_bd_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) if (sdmac->word_size == DMA_SLAVE_BUSWIDTH_4_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) bd->mode.command = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) bd->mode.command = sdmac->word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) param = BD_DONE | BD_EXTD | BD_CONT | BD_INTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) if (i + 1 == num_periods)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) param |= BD_WRAP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) dev_dbg(sdma->dev, "entry %d: count: %zu dma: %#llx %s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) i, period_len, (u64)dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) param & BD_WRAP ? "wrap" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) param & BD_INTR ? " intr" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) bd->mode.status = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) dma_addr += period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) buf += period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) return vchan_tx_prep(&sdmac->vc, &desc->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) err_bd_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) sdma_free_bd(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) sdmac->status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) static int sdma_config_write(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) struct dma_slave_config *dmaengine_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) enum dma_transfer_direction direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) struct sdma_channel *sdmac = to_sdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (direction == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) sdmac->per_address = dmaengine_cfg->src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) sdmac->watermark_level = dmaengine_cfg->src_maxburst *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) dmaengine_cfg->src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) sdmac->word_size = dmaengine_cfg->src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) } else if (direction == DMA_DEV_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) sdmac->per_address2 = dmaengine_cfg->src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) sdmac->per_address = dmaengine_cfg->dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) sdmac->watermark_level = dmaengine_cfg->src_maxburst &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) SDMA_WATERMARK_LEVEL_LWML;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) sdmac->watermark_level |= (dmaengine_cfg->dst_maxburst << 16) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) SDMA_WATERMARK_LEVEL_HWML;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) sdmac->word_size = dmaengine_cfg->dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) sdmac->per_address = dmaengine_cfg->dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) dmaengine_cfg->dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) sdmac->word_size = dmaengine_cfg->dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) sdmac->direction = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) return sdma_config_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static int sdma_config(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) struct dma_slave_config *dmaengine_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) struct sdma_channel *sdmac = to_sdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) /* Set ENBLn earlier to make sure dma request triggered after that */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) sdma_event_enable(sdmac, sdmac->event_id0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) if (sdmac->event_id1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) if (sdmac->event_id1 >= sdmac->sdma->drvdata->num_events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) sdma_event_enable(sdmac, sdmac->event_id1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) static enum dma_status sdma_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) struct sdma_channel *sdmac = to_sdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) struct sdma_desc *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) u32 residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) struct virt_dma_desc *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) enum dma_status ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) ret = dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) if (ret == DMA_COMPLETE || !txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) spin_lock_irqsave(&sdmac->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) vd = vchan_find_desc(&sdmac->vc, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) if (vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) desc = to_sdma_desc(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) else if (sdmac->desc && sdmac->desc->vd.tx.cookie == cookie)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) desc = sdmac->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (sdmac->flags & IMX_DMA_SG_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) residue = (desc->num_bd - desc->buf_ptail) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) desc->period_len - desc->chn_real_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) residue = desc->chn_count - desc->chn_real_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) residue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) spin_unlock_irqrestore(&sdmac->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) residue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) return sdmac->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) static void sdma_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) struct sdma_channel *sdmac = to_sdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) spin_lock_irqsave(&sdmac->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) if (vchan_issue_pending(&sdmac->vc) && !sdmac->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) sdma_start_desc(sdmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) spin_unlock_irqrestore(&sdmac->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) #define SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) static void sdma_add_scripts(struct sdma_engine *sdma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) const struct sdma_script_start_addrs *addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) s32 *addr_arr = (u32 *)addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) s32 *saddr_arr = (u32 *)sdma->script_addrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) /* use the default firmware in ROM if missing external firmware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (!sdma->script_number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) if (sdma->script_number > sizeof(struct sdma_script_start_addrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) / sizeof(s32)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) dev_err(sdma->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) "SDMA script number %d not match with firmware.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) sdma->script_number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) for (i = 0; i < sdma->script_number; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (addr_arr[i] > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) saddr_arr[i] = addr_arr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) static void sdma_load_firmware(const struct firmware *fw, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) struct sdma_engine *sdma = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) const struct sdma_firmware_header *header;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) const struct sdma_script_start_addrs *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) unsigned short *ram_code;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (!fw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) dev_info(sdma->dev, "external firmware not found, using ROM firmware\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) /* In this case we just use the ROM firmware. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) if (fw->size < sizeof(*header))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) goto err_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) header = (struct sdma_firmware_header *)fw->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) if (header->magic != SDMA_FIRMWARE_MAGIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) goto err_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) if (header->ram_code_start + header->ram_code_size > fw->size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) goto err_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) switch (header->version_major) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) case 3:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) sdma->script_number = SDMA_SCRIPT_ADDRS_ARRAY_SIZE_V4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) dev_err(sdma->dev, "unknown firmware version\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) goto err_firmware;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) addr = (void *)header + header->script_addrs_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) ram_code = (void *)header + header->ram_code_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) clk_enable(sdma->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) clk_enable(sdma->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) /* download the RAM image for SDMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) sdma_load_script(sdma, ram_code,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) header->ram_code_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) addr->ram_code_start_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) clk_disable(sdma->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) clk_disable(sdma->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) sdma_add_scripts(sdma, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) dev_info(sdma->dev, "loaded firmware %d.%d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) header->version_major,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) header->version_minor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) err_firmware:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) release_firmware(fw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) #define EVENT_REMAP_CELLS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) static int sdma_event_remap(struct sdma_engine *sdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) struct device_node *np = sdma->dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) struct device_node *gpr_np = of_parse_phandle(np, "gpr", 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) struct property *event_remap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) struct regmap *gpr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) char propname[] = "fsl,sdma-event-remap";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) u32 reg, val, shift, num_map, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) if (IS_ERR(np) || IS_ERR(gpr_np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) event_remap = of_find_property(np, propname, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) num_map = event_remap ? (event_remap->length / sizeof(u32)) : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (!num_map) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) dev_dbg(sdma->dev, "no event needs to be remapped\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) } else if (num_map % EVENT_REMAP_CELLS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) dev_err(sdma->dev, "the property %s must modulo %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) propname, EVENT_REMAP_CELLS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) gpr = syscon_node_to_regmap(gpr_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) if (IS_ERR(gpr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) dev_err(sdma->dev, "failed to get gpr regmap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) ret = PTR_ERR(gpr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) for (i = 0; i < num_map; i += EVENT_REMAP_CELLS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) ret = of_property_read_u32_index(np, propname, i, ®);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) dev_err(sdma->dev, "failed to read property %s index %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) propname, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) ret = of_property_read_u32_index(np, propname, i + 1, &shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) dev_err(sdma->dev, "failed to read property %s index %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) propname, i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) ret = of_property_read_u32_index(np, propname, i + 2, &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) dev_err(sdma->dev, "failed to read property %s index %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) propname, i + 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) regmap_update_bits(gpr, reg, BIT(shift), val << shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) if (!IS_ERR(gpr_np))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) of_node_put(gpr_np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) static int sdma_get_firmware(struct sdma_engine *sdma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) const char *fw_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) ret = request_firmware_nowait(THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) FW_ACTION_HOTPLUG, fw_name, sdma->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) GFP_KERNEL, sdma, sdma_load_firmware);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) static int sdma_init(struct sdma_engine *sdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) dma_addr_t ccb_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) ret = clk_enable(sdma->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) ret = clk_enable(sdma->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) goto disable_clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (sdma->drvdata->check_ratio &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) (clk_get_rate(sdma->clk_ahb) == clk_get_rate(sdma->clk_ipg)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) sdma->clk_ratio = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) /* Be sure SDMA has not started yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) writel_relaxed(0, sdma->regs + SDMA_H_C0PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) sdma->channel_control = dma_alloc_coherent(sdma->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) sizeof(struct sdma_context_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) &ccb_phys, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (!sdma->channel_control) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) goto err_dma_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) sdma->context = (void *)sdma->channel_control +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) sdma->context_phys = ccb_phys +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) MAX_DMA_CHANNELS * sizeof (struct sdma_channel_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) /* disable all channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) for (i = 0; i < sdma->drvdata->num_events; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) writel_relaxed(0, sdma->regs + chnenbl_ofs(sdma, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) /* All channels have priority 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) for (i = 0; i < MAX_DMA_CHANNELS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) writel_relaxed(0, sdma->regs + SDMA_CHNPRI_0 + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) ret = sdma_request_channel0(sdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) goto err_dma_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) sdma_config_ownership(&sdma->channel[0], false, true, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) /* Set Command Channel (Channel Zero) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) writel_relaxed(0x4050, sdma->regs + SDMA_CHN0ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) /* Set bits of CONFIG register but with static context switching */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) if (sdma->clk_ratio)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) writel_relaxed(SDMA_H_CONFIG_ACR, sdma->regs + SDMA_H_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) writel_relaxed(0, sdma->regs + SDMA_H_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) writel_relaxed(ccb_phys, sdma->regs + SDMA_H_C0PTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) /* Initializes channel's priorities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) sdma_set_channel_priority(&sdma->channel[0], 7);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) clk_disable(sdma->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) clk_disable(sdma->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) err_dma_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) clk_disable(sdma->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) disable_clk_ipg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) clk_disable(sdma->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) dev_err(sdma->dev, "initialisation failed with %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) static bool sdma_filter_fn(struct dma_chan *chan, void *fn_param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) struct sdma_channel *sdmac = to_sdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) struct imx_dma_data *data = fn_param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) if (!imx_dma_is_general_purpose(chan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) sdmac->data = *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) chan->private = &sdmac->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) static struct dma_chan *sdma_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) struct sdma_engine *sdma = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) dma_cap_mask_t mask = sdma->dma_device.cap_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) struct imx_dma_data data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) if (dma_spec->args_count != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) data.dma_request = dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) data.peripheral_type = dma_spec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) data.priority = dma_spec->args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) * init dma_request2 to zero, which is not used by the dts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) * For P2P, dma_request2 is init from dma_request_channel(),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) * chan->private will point to the imx_dma_data, and in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) * device_alloc_chan_resources(), imx_dma_data.dma_request2 will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) * be set to sdmac->event_id1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) data.dma_request2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) return __dma_request_channel(&mask, sdma_filter_fn, &data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) ofdma->of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) static int sdma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) const struct of_device_id *of_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) of_match_device(sdma_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) struct device_node *spba_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) const char *fw_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) struct resource *iores;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) struct resource spba_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) struct sdma_platform_data *pdata = dev_get_platdata(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) struct sdma_engine *sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) s32 *saddr_arr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) const struct sdma_driver_data *drvdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) drvdata = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) else if (pdev->id_entry)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) drvdata = (void *)pdev->id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) if (!drvdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) dev_err(&pdev->dev, "unable to find driver data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) sdma = devm_kzalloc(&pdev->dev, sizeof(*sdma), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) if (!sdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) spin_lock_init(&sdma->channel_0_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) sdma->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) sdma->drvdata = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) sdma->regs = devm_ioremap_resource(&pdev->dev, iores);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) if (IS_ERR(sdma->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) return PTR_ERR(sdma->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) sdma->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) if (IS_ERR(sdma->clk_ipg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) return PTR_ERR(sdma->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) sdma->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) if (IS_ERR(sdma->clk_ahb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) return PTR_ERR(sdma->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) ret = clk_prepare(sdma->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) ret = clk_prepare(sdma->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) goto err_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) ret = devm_request_irq(&pdev->dev, irq, sdma_int_handler, 0, "sdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) sdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) sdma->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) sdma->script_addrs = kzalloc(sizeof(*sdma->script_addrs), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) if (!sdma->script_addrs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) /* initially no scripts available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) saddr_arr = (s32 *)sdma->script_addrs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) for (i = 0; i < sizeof(*sdma->script_addrs) / sizeof(s32); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) saddr_arr[i] = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) dma_cap_set(DMA_SLAVE, sdma->dma_device.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) dma_cap_set(DMA_CYCLIC, sdma->dma_device.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) dma_cap_set(DMA_MEMCPY, sdma->dma_device.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) INIT_LIST_HEAD(&sdma->dma_device.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) /* Initialize channel parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) for (i = 0; i < MAX_DMA_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) struct sdma_channel *sdmac = &sdma->channel[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) sdmac->sdma = sdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) sdmac->channel = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) sdmac->vc.desc_free = sdma_desc_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) INIT_WORK(&sdmac->terminate_worker,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) sdma_channel_terminate_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) * Add the channel to the DMAC list. Do not add channel 0 though
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) * because we need it internally in the SDMA driver. This also means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) * that channel 0 in dmaengine counting matches sdma channel 1.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) if (i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) vchan_init(&sdmac->vc, &sdma->dma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) ret = sdma_init(sdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) goto err_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) ret = sdma_event_remap(sdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) goto err_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) if (sdma->drvdata->script_addrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) sdma_add_scripts(sdma, sdma->drvdata->script_addrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) if (pdata && pdata->script_addrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) sdma_add_scripts(sdma, pdata->script_addrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) sdma->dma_device.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) sdma->dma_device.device_alloc_chan_resources = sdma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) sdma->dma_device.device_free_chan_resources = sdma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) sdma->dma_device.device_tx_status = sdma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) sdma->dma_device.device_prep_slave_sg = sdma_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) sdma->dma_device.device_prep_dma_cyclic = sdma_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) sdma->dma_device.device_config = sdma_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) sdma->dma_device.device_terminate_all = sdma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) sdma->dma_device.device_synchronize = sdma_channel_synchronize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) sdma->dma_device.src_addr_widths = SDMA_DMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) sdma->dma_device.dst_addr_widths = SDMA_DMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) sdma->dma_device.directions = SDMA_DMA_DIRECTIONS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) sdma->dma_device.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) sdma->dma_device.device_prep_dma_memcpy = sdma_prep_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) sdma->dma_device.device_issue_pending = sdma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) sdma->dma_device.copy_align = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) dma_set_max_seg_size(sdma->dma_device.dev, SDMA_BD_MAX_CNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) platform_set_drvdata(pdev, sdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) ret = dma_async_device_register(&sdma->dma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) dev_err(&pdev->dev, "unable to register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) goto err_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) ret = of_dma_controller_register(np, sdma_xlate, sdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) dev_err(&pdev->dev, "failed to register controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) goto err_register;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) spba_bus = of_find_compatible_node(NULL, NULL, "fsl,spba-bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) ret = of_address_to_resource(spba_bus, 0, &spba_res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) sdma->spba_start_addr = spba_res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) sdma->spba_end_addr = spba_res.end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) of_node_put(spba_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) * Kick off firmware loading as the very last step:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) * attempt to load firmware only if we're not on the error path, because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) * the firmware callback requires a fully functional and allocated sdma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) * instance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) if (pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) ret = sdma_get_firmware(sdma, pdata->fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) dev_warn(&pdev->dev, "failed to get firmware from platform data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) * Because that device tree does not encode ROM script address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) * the RAM script in firmware is mandatory for device tree
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) * probe, otherwise it fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) ret = of_property_read_string(np, "fsl,sdma-ram-script-name",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) &fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) dev_warn(&pdev->dev, "failed to get firmware name\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) ret = sdma_get_firmware(sdma, fw_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) dev_warn(&pdev->dev, "failed to get firmware from device tree\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) err_register:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) dma_async_device_unregister(&sdma->dma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) err_init:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) kfree(sdma->script_addrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) clk_unprepare(sdma->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) err_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) clk_unprepare(sdma->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) static int sdma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) struct sdma_engine *sdma = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) devm_free_irq(&pdev->dev, sdma->irq, sdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) dma_async_device_unregister(&sdma->dma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) kfree(sdma->script_addrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) clk_unprepare(sdma->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) clk_unprepare(sdma->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) /* Kill the tasklet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) for (i = 0; i < MAX_DMA_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) struct sdma_channel *sdmac = &sdma->channel[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) tasklet_kill(&sdmac->vc.task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) sdma_free_chan_resources(&sdmac->vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) platform_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) static struct platform_driver sdma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) .name = "imx-sdma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) .of_match_table = sdma_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) .id_table = sdma_devtypes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) .remove = sdma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) .probe = sdma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) module_platform_driver(sdma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) MODULE_DESCRIPTION("i.MX SDMA driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) #if IS_ENABLED(CONFIG_SOC_IMX6Q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) MODULE_FIRMWARE("imx/sdma/sdma-imx6q.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) #if IS_ENABLED(CONFIG_SOC_IMX7D)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) MODULE_FIRMWARE("imx/sdma/sdma-imx7d.bin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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