^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) // drivers/dma/imx-dma.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) // This file contains a driver for the Freescale i.MX DMA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) // found on i.MX1/21/27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) // Copyright 2010 Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) // Copyright 2012 Javier Martin, Vista Silicon <javier.martin@vista-silicon.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <asm/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_data/dma-imx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include "dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMXDMA_MAX_CHAN_DESCRIPTORS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX_DMA_CHANNELS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX_DMA_2D_SLOTS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX_DMA_2D_SLOT_A 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX_DMA_2D_SLOT_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX_DMA_LENGTH_LOOP ((unsigned int)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX_DMA_MEMSIZE_32 (0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX_DMA_MEMSIZE_8 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX_DMA_MEMSIZE_16 (2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX_DMA_TYPE_LINEAR (0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX_DMA_TYPE_2D (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX_DMA_TYPE_FIFO (2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX_DMA_ERR_BURST (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX_DMA_ERR_REQUEST (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX_DMA_ERR_TRANSFER (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX_DMA_ERR_BUFFER (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX_DMA_ERR_TIMEOUT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DMA_DCR 0x00 /* Control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define DMA_DISR 0x04 /* Interrupt status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DMA_DIMR 0x08 /* Interrupt mask Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DMA_DBTOSR 0x0c /* Burst timeout status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DMA_DRTOSR 0x10 /* Request timeout Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DMA_DSESR 0x14 /* Transfer Error Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DMA_DBOSR 0x18 /* Buffer overflow status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DMA_DBTOCR 0x1c /* Burst timeout control Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define DMA_WSRA 0x40 /* W-Size Register A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DMA_XSRA 0x44 /* X-Size Register A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DMA_YSRA 0x48 /* Y-Size Register A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DMA_WSRB 0x4c /* W-Size Register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DMA_XSRB 0x50 /* X-Size Register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DMA_YSRB 0x54 /* Y-Size Register B */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DMA_SAR(x) (0x80 + ((x) << 6)) /* Source Address Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DMA_DAR(x) (0x84 + ((x) << 6)) /* Destination Address Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DMA_CNTR(x) (0x88 + ((x) << 6)) /* Count Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DMA_CCR(x) (0x8c + ((x) << 6)) /* Control Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DMA_RSSR(x) (0x90 + ((x) << 6)) /* Request source select Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DMA_BLR(x) (0x94 + ((x) << 6)) /* Burst length Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DMA_RTOR(x) (0x98 + ((x) << 6)) /* Request timeout Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DMA_BUCR(x) (0x98 + ((x) << 6)) /* Bus Utilization Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DMA_CCNR(x) (0x9C + ((x) << 6)) /* Channel counter Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DCR_DRST (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DCR_DEN (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DBTOCR_EN (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DBTOCR_CNT(x) ((x) & 0x7fff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CNTR_CNT(x) ((x) & 0xffffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CCR_ACRPT (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CCR_DMOD_LINEAR (0x0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CCR_DMOD_2D (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CCR_DMOD_FIFO (0x2 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CCR_DMOD_EOBFIFO (0x3 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CCR_SMOD_LINEAR (0x0 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CCR_SMOD_2D (0x1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CCR_SMOD_FIFO (0x2 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CCR_SMOD_EOBFIFO (0x3 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CCR_MDIR_DEC (1<<9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CCR_MSEL_B (1<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CCR_DSIZ_32 (0x0 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CCR_DSIZ_8 (0x1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CCR_DSIZ_16 (0x2 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CCR_SSIZ_32 (0x0 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CCR_SSIZ_8 (0x1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CCR_SSIZ_16 (0x2 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CCR_REN (1<<3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CCR_RPT (1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CCR_FRC (1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CCR_CEN (1<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define RTOR_EN (1<<15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define RTOR_CLK (1<<14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define RTOR_PSC (1<<13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) enum imxdma_prep_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) IMXDMA_DESC_MEMCPY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) IMXDMA_DESC_INTERLEAVED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) IMXDMA_DESC_SLAVE_SG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) IMXDMA_DESC_CYCLIC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct imx_dma_2d_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u16 xsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u16 ysr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u16 wsr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct imxdma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct dma_async_tx_descriptor desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) dma_addr_t src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) dma_addr_t dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) enum dma_transfer_direction direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) enum imxdma_prep_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* For memcpy and interleaved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int config_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int config_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* For interleaved transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned int y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* For slave sg and cyclic */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int sgcount;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct imxdma_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) int hw_chaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct timer_list watchdog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct imxdma_engine *imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) struct tasklet_struct dma_tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct list_head ld_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct list_head ld_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct list_head ld_active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) int descs_allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) enum dma_slave_buswidth word_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dma_addr_t per_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 watermark_level;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct dma_chan chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct dma_async_tx_descriptor desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int dma_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct scatterlist *sg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 ccr_from_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 ccr_to_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) bool enabled_2d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) int slot_2d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct dma_slave_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) enum imx_dma_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) IMX1_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) IMX21_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) IMX27_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct imxdma_engine {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct dma_device dma_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct clk *dma_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct clk *dma_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) struct imx_dma_2d_config slots_2d[IMX_DMA_2D_SLOTS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct imxdma_channel channel[IMX_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) enum imx_dma_type devtype;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int irq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct imxdma_filter_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) struct imxdma_engine *imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) int request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static const struct platform_device_id imx_dma_devtype[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) .name = "imx1-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) .driver_data = IMX1_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) .name = "imx21-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) .driver_data = IMX21_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) .name = "imx27-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) .driver_data = IMX27_DMA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_DEVICE_TABLE(platform, imx_dma_devtype);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static const struct of_device_id imx_dma_of_dev_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) .compatible = "fsl,imx1-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) .data = &imx_dma_devtype[IMX1_DMA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) .compatible = "fsl,imx21-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) .data = &imx_dma_devtype[IMX21_DMA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) .compatible = "fsl,imx27-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .data = &imx_dma_devtype[IMX27_DMA],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* sentinel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) MODULE_DEVICE_TABLE(of, imx_dma_of_dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static inline int is_imx1_dma(struct imxdma_engine *imxdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return imxdma->devtype == IMX1_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static inline int is_imx27_dma(struct imxdma_engine *imxdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) return imxdma->devtype == IMX27_DMA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static struct imxdma_channel *to_imxdma_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) return container_of(chan, struct imxdma_channel, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static inline bool imxdma_chan_is_doing_cyclic(struct imxdma_channel *imxdmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) struct imxdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) if (!list_empty(&imxdmac->ld_active)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (desc->type == IMXDMA_DESC_CYCLIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) static void imx_dmav1_writel(struct imxdma_engine *imxdma, unsigned val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) __raw_writel(val, imxdma->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static unsigned imx_dmav1_readl(struct imxdma_engine *imxdma, unsigned offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return __raw_readl(imxdma->base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int imxdma_hw_chain(struct imxdma_channel *imxdmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (is_imx27_dma(imxdma))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) return imxdmac->hw_chaining;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * imxdma_sg_next - prepare next chunk for scatter-gather DMA emulation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) static inline void imxdma_sg_next(struct imxdma_desc *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct scatterlist *sg = d->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) size_t now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) now = min_t(size_t, d->len, sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) if (d->len != IMX_DMA_LENGTH_LOOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) d->len -= now;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (d->direction == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) imx_dmav1_writel(imxdma, sg->dma_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) DMA_DAR(imxdmac->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) imx_dmav1_writel(imxdma, sg->dma_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) DMA_SAR(imxdmac->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) imx_dmav1_writel(imxdma, now, DMA_CNTR(imxdmac->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) dev_dbg(imxdma->dev, " %s channel: %d dst 0x%08x, src 0x%08x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "size 0x%08x\n", __func__, imxdmac->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) imx_dmav1_readl(imxdma, DMA_DAR(imxdmac->channel)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) imx_dmav1_readl(imxdma, DMA_SAR(imxdmac->channel)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) imx_dmav1_readl(imxdma, DMA_CNTR(imxdmac->channel)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) static void imxdma_enable_hw(struct imxdma_desc *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int channel = imxdmac->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ~(1 << channel), DMA_DIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) CCR_CEN | CCR_ACRPT, DMA_CCR(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) if (!is_imx1_dma(imxdma) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) d->sg && imxdma_hw_chain(imxdmac)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) d->sg = sg_next(d->sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (d->sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) imxdma_sg_next(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) tmp = imx_dmav1_readl(imxdma, DMA_CCR(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) imx_dmav1_writel(imxdma, tmp | CCR_RPT | CCR_ACRPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) DMA_CCR(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static void imxdma_disable_hw(struct imxdma_channel *imxdmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int channel = imxdmac->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev_dbg(imxdma->dev, "%s channel %d\n", __func__, channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (imxdma_hw_chain(imxdmac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) del_timer(&imxdmac->watchdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) local_irq_save(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_DIMR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) (1 << channel), DMA_DIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) imx_dmav1_writel(imxdma, imx_dmav1_readl(imxdma, DMA_CCR(channel)) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) ~CCR_CEN, DMA_CCR(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) imx_dmav1_writel(imxdma, 1 << channel, DMA_DISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) local_irq_restore(flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) static void imxdma_watchdog(struct timer_list *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct imxdma_channel *imxdmac = from_timer(imxdmac, t, watchdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) int channel = imxdmac->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) imx_dmav1_writel(imxdma, 0, DMA_CCR(channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* Tasklet watchdog error handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) tasklet_schedule(&imxdmac->dma_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dev_dbg(imxdma->dev, "channel %d: watchdog timeout!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) imxdmac->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) static irqreturn_t imxdma_err_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct imxdma_engine *imxdma = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) unsigned int err_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) int i, disr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) int errcode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) disr = imx_dmav1_readl(imxdma, DMA_DISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) err_mask = imx_dmav1_readl(imxdma, DMA_DBTOSR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) imx_dmav1_readl(imxdma, DMA_DRTOSR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) imx_dmav1_readl(imxdma, DMA_DSESR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) imx_dmav1_readl(imxdma, DMA_DBOSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!err_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) imx_dmav1_writel(imxdma, disr & err_mask, DMA_DISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) for (i = 0; i < IMX_DMA_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) if (!(err_mask & (1 << i)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) errcode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (imx_dmav1_readl(imxdma, DMA_DBTOSR) & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) imx_dmav1_writel(imxdma, 1 << i, DMA_DBTOSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) errcode |= IMX_DMA_ERR_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (imx_dmav1_readl(imxdma, DMA_DRTOSR) & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) imx_dmav1_writel(imxdma, 1 << i, DMA_DRTOSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) errcode |= IMX_DMA_ERR_REQUEST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (imx_dmav1_readl(imxdma, DMA_DSESR) & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) imx_dmav1_writel(imxdma, 1 << i, DMA_DSESR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) errcode |= IMX_DMA_ERR_TRANSFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) if (imx_dmav1_readl(imxdma, DMA_DBOSR) & (1 << i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) imx_dmav1_writel(imxdma, 1 << i, DMA_DBOSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) errcode |= IMX_DMA_ERR_BUFFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) /* Tasklet error handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) tasklet_schedule(&imxdma->channel[i].dma_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_warn(imxdma->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) "DMA timeout on channel %d -%s%s%s%s\n", i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) errcode & IMX_DMA_ERR_BURST ? " burst" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) errcode & IMX_DMA_ERR_REQUEST ? " request" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) errcode & IMX_DMA_ERR_TRANSFER ? " transfer" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) errcode & IMX_DMA_ERR_BUFFER ? " buffer" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static void dma_irq_handle_channel(struct imxdma_channel *imxdmac)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) int chno = imxdmac->channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) struct imxdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) spin_lock_irqsave(&imxdma->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (list_empty(&imxdmac->ld_active)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) spin_unlock_irqrestore(&imxdma->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) desc = list_first_entry(&imxdmac->ld_active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct imxdma_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) spin_unlock_irqrestore(&imxdma->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (desc->sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) desc->sg = sg_next(desc->sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if (desc->sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) imxdma_sg_next(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) tmp = imx_dmav1_readl(imxdma, DMA_CCR(chno));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (imxdma_hw_chain(imxdmac)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) /* FIXME: The timeout should probably be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) * configurable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) mod_timer(&imxdmac->watchdog,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) jiffies + msecs_to_jiffies(500));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) tmp |= CCR_CEN | CCR_RPT | CCR_ACRPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) imx_dmav1_writel(imxdma, tmp & ~CCR_CEN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) DMA_CCR(chno));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) tmp |= CCR_CEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) imx_dmav1_writel(imxdma, tmp, DMA_CCR(chno));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (imxdma_chan_is_doing_cyclic(imxdmac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /* Tasklet progression */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) tasklet_schedule(&imxdmac->dma_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (imxdma_hw_chain(imxdmac)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) del_timer(&imxdmac->watchdog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) imx_dmav1_writel(imxdma, 0, DMA_CCR(chno));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Tasklet irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) tasklet_schedule(&imxdmac->dma_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) static irqreturn_t dma_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) struct imxdma_engine *imxdma = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) int i, disr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) if (!is_imx1_dma(imxdma))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) imxdma_err_handler(irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) disr = imx_dmav1_readl(imxdma, DMA_DISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) dev_dbg(imxdma->dev, "%s called, disr=0x%08x\n", __func__, disr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) imx_dmav1_writel(imxdma, disr, DMA_DISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) for (i = 0; i < IMX_DMA_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) if (disr & (1 << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dma_irq_handle_channel(&imxdma->channel[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) static int imxdma_xfer_desc(struct imxdma_desc *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct imxdma_channel *imxdmac = to_imxdma_chan(d->desc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) int slot = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /* Configure and enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) switch (d->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) case IMXDMA_DESC_INTERLEAVED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) /* Try to get a free 2D slot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) for (i = 0; i < IMX_DMA_2D_SLOTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if ((imxdma->slots_2d[i].count > 0) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) ((imxdma->slots_2d[i].xsr != d->x) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) (imxdma->slots_2d[i].ysr != d->y) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) (imxdma->slots_2d[i].wsr != d->w)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) slot = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) if (slot < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) imxdma->slots_2d[slot].xsr = d->x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) imxdma->slots_2d[slot].ysr = d->y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) imxdma->slots_2d[slot].wsr = d->w;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) imxdma->slots_2d[slot].count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) imxdmac->slot_2d = slot;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) imxdmac->enabled_2d = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) if (slot == IMX_DMA_2D_SLOT_A) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) d->config_mem &= ~CCR_MSEL_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) d->config_port &= ~CCR_MSEL_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) imx_dmav1_writel(imxdma, d->x, DMA_XSRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) imx_dmav1_writel(imxdma, d->y, DMA_YSRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) imx_dmav1_writel(imxdma, d->w, DMA_WSRA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) d->config_mem |= CCR_MSEL_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) d->config_port |= CCR_MSEL_B;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) imx_dmav1_writel(imxdma, d->x, DMA_XSRB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) imx_dmav1_writel(imxdma, d->y, DMA_YSRB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) imx_dmav1_writel(imxdma, d->w, DMA_WSRB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) * We fall-through here intentionally, since a 2D transfer is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) * similar to MEMCPY just adding the 2D slot configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) case IMXDMA_DESC_MEMCPY:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) imx_dmav1_writel(imxdma, d->src, DMA_SAR(imxdmac->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) imx_dmav1_writel(imxdma, d->dest, DMA_DAR(imxdmac->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) imx_dmav1_writel(imxdma, d->config_mem | (d->config_port << 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) DMA_CCR(imxdmac->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) imx_dmav1_writel(imxdma, d->len, DMA_CNTR(imxdmac->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev_dbg(imxdma->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) "%s channel: %d dest=0x%08llx src=0x%08llx dma_length=%zu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) __func__, imxdmac->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) (unsigned long long)d->dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) (unsigned long long)d->src, d->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* Cyclic transfer is the same as slave_sg with special sg configuration. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) case IMXDMA_DESC_CYCLIC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) case IMXDMA_DESC_SLAVE_SG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) if (d->direction == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) imx_dmav1_writel(imxdma, imxdmac->per_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) DMA_SAR(imxdmac->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) imx_dmav1_writel(imxdma, imxdmac->ccr_from_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) DMA_CCR(imxdmac->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) dev_dbg(imxdma->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (dev2mem)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) __func__, imxdmac->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) d->sg, d->sgcount, d->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) (unsigned long long)imxdmac->per_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) } else if (d->direction == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) imx_dmav1_writel(imxdma, imxdmac->per_address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) DMA_DAR(imxdmac->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) imx_dmav1_writel(imxdma, imxdmac->ccr_to_device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) DMA_CCR(imxdmac->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) dev_dbg(imxdma->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) "%s channel: %d sg=%p sgcount=%d total length=%zu dev_addr=0x%08llx (mem2dev)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) __func__, imxdmac->channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) d->sg, d->sgcount, d->len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) (unsigned long long)imxdmac->per_address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) dev_err(imxdma->dev, "%s channel: %d bad dma mode\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) __func__, imxdmac->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) imxdma_sg_next(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) imxdma_enable_hw(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) static void imxdma_tasklet(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct imxdma_channel *imxdmac = from_tasklet(imxdmac, t, dma_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) struct imxdma_desc *desc, *next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) spin_lock_irqsave(&imxdma->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (list_empty(&imxdmac->ld_active)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* Someone might have called terminate all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) spin_unlock_irqrestore(&imxdma->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) desc = list_first_entry(&imxdmac->ld_active, struct imxdma_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /* If we are dealing with a cyclic descriptor, keep it on ld_active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * and dont mark the descriptor as complete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) * Only in non-cyclic cases it would be marked as complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (imxdma_chan_is_doing_cyclic(imxdmac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) dma_cookie_complete(&desc->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* Free 2D slot if it was an interleaved transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (imxdmac->enabled_2d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) imxdma->slots_2d[imxdmac->slot_2d].count--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) imxdmac->enabled_2d = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) list_move_tail(imxdmac->ld_active.next, &imxdmac->ld_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) if (!list_empty(&imxdmac->ld_queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) next_desc = list_first_entry(&imxdmac->ld_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct imxdma_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) list_move_tail(imxdmac->ld_queue.next, &imxdmac->ld_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (imxdma_xfer_desc(next_desc) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dev_warn(imxdma->dev, "%s: channel: %d couldn't xfer desc\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) __func__, imxdmac->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) spin_unlock_irqrestore(&imxdma->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) dmaengine_desc_get_callback_invoke(&desc->desc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) static int imxdma_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) imxdma_disable_hw(imxdmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) spin_lock_irqsave(&imxdma->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) spin_unlock_irqrestore(&imxdma->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int imxdma_config_write(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct dma_slave_config *dmaengine_cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) enum dma_transfer_direction direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned int mode = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) if (direction == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) imxdmac->per_address = dmaengine_cfg->src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) imxdmac->watermark_level = dmaengine_cfg->src_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) imxdmac->word_size = dmaengine_cfg->src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) imxdmac->per_address = dmaengine_cfg->dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) imxdmac->watermark_level = dmaengine_cfg->dst_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) imxdmac->word_size = dmaengine_cfg->dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) switch (imxdmac->word_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) mode = IMX_DMA_MEMSIZE_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) mode = IMX_DMA_MEMSIZE_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) mode = IMX_DMA_MEMSIZE_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) imxdmac->hw_chaining = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) imxdmac->ccr_from_device = (mode | IMX_DMA_TYPE_FIFO) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) ((IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) << 2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) CCR_REN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) imxdmac->ccr_to_device =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) (IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) ((mode | IMX_DMA_TYPE_FIFO) << 2) | CCR_REN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) imx_dmav1_writel(imxdma, imxdmac->dma_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) DMA_RSSR(imxdmac->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /* Set burst length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) imx_dmav1_writel(imxdma, imxdmac->watermark_level *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) imxdmac->word_size, DMA_BLR(imxdmac->channel));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) static int imxdma_config(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct dma_slave_config *dmaengine_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) memcpy(&imxdmac->config, dmaengine_cfg, sizeof(*dmaengine_cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static enum dma_status imxdma_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) return dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static dma_cookie_t imxdma_tx_submit(struct dma_async_tx_descriptor *tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) struct imxdma_channel *imxdmac = to_imxdma_chan(tx->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) spin_lock_irqsave(&imxdma->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) list_move_tail(imxdmac->ld_free.next, &imxdmac->ld_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) cookie = dma_cookie_assign(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) spin_unlock_irqrestore(&imxdma->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) return cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static int imxdma_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) struct imx_dma_data *data = chan->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) if (data != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) imxdmac->dma_request = data->dma_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) while (imxdmac->descs_allocated < IMXDMA_MAX_CHAN_DESCRIPTORS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct imxdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) desc = kzalloc(sizeof(*desc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) memset(&desc->desc, 0, sizeof(struct dma_async_tx_descriptor));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dma_async_tx_descriptor_init(&desc->desc, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) desc->desc.tx_submit = imxdma_tx_submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* txd.flags will be overwritten in prep funcs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) desc->desc.flags = DMA_CTRL_ACK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) desc->status = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) list_add_tail(&desc->node, &imxdmac->ld_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) imxdmac->descs_allocated++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (!imxdmac->descs_allocated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) return imxdmac->descs_allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) static void imxdma_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct imxdma_desc *desc, *_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) spin_lock_irqsave(&imxdma->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) imxdma_disable_hw(imxdmac);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) list_splice_tail_init(&imxdmac->ld_active, &imxdmac->ld_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) list_splice_tail_init(&imxdmac->ld_queue, &imxdmac->ld_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) spin_unlock_irqrestore(&imxdma->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) list_for_each_entry_safe(desc, _desc, &imxdmac->ld_free, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) imxdmac->descs_allocated--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) INIT_LIST_HEAD(&imxdmac->ld_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) kfree(imxdmac->sg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) imxdmac->sg_list = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) static struct dma_async_tx_descriptor *imxdma_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct dma_chan *chan, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) unsigned int sg_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) unsigned long flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) int i, dma_length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct imxdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) if (list_empty(&imxdmac->ld_free) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) imxdma_chan_is_doing_cyclic(imxdmac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) for_each_sg(sgl, sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dma_length += sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) imxdma_config_write(chan, &imxdmac->config, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) switch (imxdmac->word_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) if (sg_dma_len(sgl) & 3 || sgl->dma_address & 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) if (sg_dma_len(sgl) & 1 || sgl->dma_address & 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) desc->type = IMXDMA_DESC_SLAVE_SG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) desc->sg = sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) desc->sgcount = sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) desc->len = dma_length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) desc->direction = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (direction == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) desc->src = imxdmac->per_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) desc->dest = imxdmac->per_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) desc->desc.callback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) desc->desc.callback_param = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) return &desc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) static struct dma_async_tx_descriptor *imxdma_prep_dma_cyclic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) size_t period_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct imxdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) unsigned int periods = buf_len / period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) dev_dbg(imxdma->dev, "%s channel: %d buf_len=%zu period_len=%zu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) __func__, imxdmac->channel, buf_len, period_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) if (list_empty(&imxdmac->ld_free) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) imxdma_chan_is_doing_cyclic(imxdmac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) kfree(imxdmac->sg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) imxdmac->sg_list = kcalloc(periods + 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) sizeof(struct scatterlist), GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) if (!imxdmac->sg_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) sg_init_table(imxdmac->sg_list, periods);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) for (i = 0; i < periods; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) sg_assign_page(&imxdmac->sg_list[i], NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) imxdmac->sg_list[i].offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) imxdmac->sg_list[i].dma_address = dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) sg_dma_len(&imxdmac->sg_list[i]) = period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) dma_addr += period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /* close the loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) sg_chain(imxdmac->sg_list, periods + 1, imxdmac->sg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) desc->type = IMXDMA_DESC_CYCLIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) desc->sg = imxdmac->sg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) desc->sgcount = periods;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) desc->len = IMX_DMA_LENGTH_LOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) desc->direction = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (direction == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) desc->src = imxdmac->per_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) desc->dest = imxdmac->per_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) desc->desc.callback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) desc->desc.callback_param = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) imxdma_config_write(chan, &imxdmac->config, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) return &desc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) static struct dma_async_tx_descriptor *imxdma_prep_dma_memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct dma_chan *chan, dma_addr_t dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dma_addr_t src, size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) struct imxdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dev_dbg(imxdma->dev, "%s channel: %d src=0x%llx dst=0x%llx len=%zu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) __func__, imxdmac->channel, (unsigned long long)src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) (unsigned long long)dest, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) if (list_empty(&imxdmac->ld_free) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) imxdma_chan_is_doing_cyclic(imxdmac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) desc->type = IMXDMA_DESC_MEMCPY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) desc->src = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) desc->dest = dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) desc->len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) desc->direction = DMA_MEM_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) desc->config_port = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) desc->config_mem = IMX_DMA_MEMSIZE_32 | IMX_DMA_TYPE_LINEAR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) desc->desc.callback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) desc->desc.callback_param = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return &desc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) static struct dma_async_tx_descriptor *imxdma_prep_dma_interleaved(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) struct dma_chan *chan, struct dma_interleaved_template *xt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct imxdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) dev_dbg(imxdma->dev, "%s channel: %d src_start=0x%llx dst_start=0x%llx\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) " src_sgl=%s dst_sgl=%s numf=%zu frame_size=%zu\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) imxdmac->channel, (unsigned long long)xt->src_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) (unsigned long long) xt->dst_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) xt->src_sgl ? "true" : "false", xt->dst_sgl ? "true" : "false",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) xt->numf, xt->frame_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) if (list_empty(&imxdmac->ld_free) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) imxdma_chan_is_doing_cyclic(imxdmac))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (xt->frame_size != 1 || xt->numf <= 0 || xt->dir != DMA_MEM_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) desc = list_first_entry(&imxdmac->ld_free, struct imxdma_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) desc->type = IMXDMA_DESC_INTERLEAVED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) desc->src = xt->src_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) desc->dest = xt->dst_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) desc->x = xt->sgl[0].size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) desc->y = xt->numf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) desc->w = xt->sgl[0].icg + desc->x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) desc->len = desc->x * desc->y;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) desc->direction = DMA_MEM_TO_MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) desc->config_port = IMX_DMA_MEMSIZE_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) desc->config_mem = IMX_DMA_MEMSIZE_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) if (xt->src_sgl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) desc->config_mem |= IMX_DMA_TYPE_2D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (xt->dst_sgl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) desc->config_port |= IMX_DMA_TYPE_2D;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) desc->desc.callback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) desc->desc.callback_param = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) return &desc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) static void imxdma_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) struct imxdma_channel *imxdmac = to_imxdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) struct imxdma_engine *imxdma = imxdmac->imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) struct imxdma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) spin_lock_irqsave(&imxdma->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) if (list_empty(&imxdmac->ld_active) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) !list_empty(&imxdmac->ld_queue)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) desc = list_first_entry(&imxdmac->ld_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) struct imxdma_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (imxdma_xfer_desc(desc) < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) dev_warn(imxdma->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) "%s: channel: %d couldn't issue DMA xfer\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) __func__, imxdmac->channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) list_move_tail(imxdmac->ld_queue.next,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) &imxdmac->ld_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) spin_unlock_irqrestore(&imxdma->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static bool imxdma_filter_fn(struct dma_chan *chan, void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) struct imxdma_filter_data *fdata = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct imxdma_channel *imxdma_chan = to_imxdma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (chan->device->dev != fdata->imxdma->dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) imxdma_chan->dma_request = fdata->request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) chan->private = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) static struct dma_chan *imxdma_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) int count = dma_spec->args_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) struct imxdma_engine *imxdma = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) struct imxdma_filter_data fdata = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) .imxdma = imxdma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) if (count != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) fdata.request = dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) return dma_request_channel(imxdma->dma_device.cap_mask,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) imxdma_filter_fn, &fdata);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) static int __init imxdma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) struct imxdma_engine *imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) const struct of_device_id *of_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) int irq, irq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) of_id = of_match_device(imx_dma_of_dev_id, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) pdev->id_entry = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) imxdma = devm_kzalloc(&pdev->dev, sizeof(*imxdma), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (!imxdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) imxdma->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) imxdma->devtype = pdev->id_entry->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) imxdma->base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) if (IS_ERR(imxdma->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return PTR_ERR(imxdma->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) imxdma->dma_ipg = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) if (IS_ERR(imxdma->dma_ipg))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) return PTR_ERR(imxdma->dma_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) imxdma->dma_ahb = devm_clk_get(&pdev->dev, "ahb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) if (IS_ERR(imxdma->dma_ahb))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) return PTR_ERR(imxdma->dma_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ret = clk_prepare_enable(imxdma->dma_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) ret = clk_prepare_enable(imxdma->dma_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) goto disable_dma_ipg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) /* reset DMA module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) imx_dmav1_writel(imxdma, DCR_DRST, DMA_DCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) if (is_imx1_dma(imxdma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) ret = devm_request_irq(&pdev->dev, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) dma_irq_handler, 0, "DMA", imxdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) dev_warn(imxdma->dev, "Can't register IRQ for DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) goto disable_dma_ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) imxdma->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) irq_err = platform_get_irq(pdev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) if (irq_err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) ret = irq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) goto disable_dma_ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) ret = devm_request_irq(&pdev->dev, irq_err,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) imxdma_err_handler, 0, "DMA", imxdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) dev_warn(imxdma->dev, "Can't register ERRIRQ for DMA\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) goto disable_dma_ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) imxdma->irq_err = irq_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) /* enable DMA module */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) imx_dmav1_writel(imxdma, DCR_DEN, DMA_DCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) /* clear all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) /* disable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) imx_dmav1_writel(imxdma, (1 << IMX_DMA_CHANNELS) - 1, DMA_DIMR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) INIT_LIST_HEAD(&imxdma->dma_device.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) dma_cap_set(DMA_SLAVE, imxdma->dma_device.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) dma_cap_set(DMA_CYCLIC, imxdma->dma_device.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) dma_cap_set(DMA_MEMCPY, imxdma->dma_device.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) dma_cap_set(DMA_INTERLEAVE, imxdma->dma_device.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) /* Initialize 2D global parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) for (i = 0; i < IMX_DMA_2D_SLOTS; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) imxdma->slots_2d[i].count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) spin_lock_init(&imxdma->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) /* Initialize channel parameters */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) for (i = 0; i < IMX_DMA_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct imxdma_channel *imxdmac = &imxdma->channel[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (!is_imx1_dma(imxdma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) ret = devm_request_irq(&pdev->dev, irq + i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) dma_irq_handler, 0, "DMA", imxdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) dev_warn(imxdma->dev, "Can't register IRQ %d "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) "for DMA channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) irq + i, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) goto disable_dma_ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) imxdmac->irq = irq + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) timer_setup(&imxdmac->watchdog, imxdma_watchdog, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) imxdmac->imxdma = imxdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) INIT_LIST_HEAD(&imxdmac->ld_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) INIT_LIST_HEAD(&imxdmac->ld_free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) INIT_LIST_HEAD(&imxdmac->ld_active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) tasklet_setup(&imxdmac->dma_tasklet, imxdma_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) imxdmac->chan.device = &imxdma->dma_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) dma_cookie_init(&imxdmac->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) imxdmac->channel = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* Add the channel to the DMAC list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) list_add_tail(&imxdmac->chan.device_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) &imxdma->dma_device.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) imxdma->dma_device.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) imxdma->dma_device.device_alloc_chan_resources = imxdma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) imxdma->dma_device.device_free_chan_resources = imxdma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) imxdma->dma_device.device_tx_status = imxdma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) imxdma->dma_device.device_prep_slave_sg = imxdma_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) imxdma->dma_device.device_prep_dma_cyclic = imxdma_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) imxdma->dma_device.device_prep_dma_memcpy = imxdma_prep_dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) imxdma->dma_device.device_prep_interleaved_dma = imxdma_prep_dma_interleaved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) imxdma->dma_device.device_config = imxdma_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) imxdma->dma_device.device_terminate_all = imxdma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) imxdma->dma_device.device_issue_pending = imxdma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) platform_set_drvdata(pdev, imxdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) imxdma->dma_device.copy_align = DMAENGINE_ALIGN_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) dma_set_max_seg_size(imxdma->dma_device.dev, 0xffffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) ret = dma_async_device_register(&imxdma->dma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) dev_err(&pdev->dev, "unable to register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) goto disable_dma_ahb_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) if (pdev->dev.of_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) ret = of_dma_controller_register(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) imxdma_xlate, imxdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) dev_err(&pdev->dev, "unable to register of_dma_controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) goto err_of_dma_controller;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) err_of_dma_controller:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) dma_async_device_unregister(&imxdma->dma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) disable_dma_ahb_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) clk_disable_unprepare(imxdma->dma_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) disable_dma_ipg_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) clk_disable_unprepare(imxdma->dma_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) static void imxdma_free_irq(struct platform_device *pdev, struct imxdma_engine *imxdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) if (is_imx1_dma(imxdma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) disable_irq(imxdma->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) disable_irq(imxdma->irq_err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) for (i = 0; i < IMX_DMA_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) struct imxdma_channel *imxdmac = &imxdma->channel[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) if (!is_imx1_dma(imxdma))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) disable_irq(imxdmac->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) tasklet_kill(&imxdmac->dma_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static int imxdma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) struct imxdma_engine *imxdma = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) imxdma_free_irq(pdev, imxdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) dma_async_device_unregister(&imxdma->dma_device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (pdev->dev.of_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) of_dma_controller_free(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) clk_disable_unprepare(imxdma->dma_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) clk_disable_unprepare(imxdma->dma_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) static struct platform_driver imxdma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .name = "imx-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) .of_match_table = imx_dma_of_dev_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) .id_table = imx_dma_devtype,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) .remove = imxdma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) static int __init imxdma_module_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) return platform_driver_probe(&imxdma_driver, imxdma_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) subsys_initcall(imxdma_module_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) MODULE_AUTHOR("Sascha Hauer, Pengutronix <s.hauer@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) MODULE_DESCRIPTION("i.MX dma driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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