^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * IMG Multi-threaded DMA Controller (MDC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2009,2012,2013 Imagination Technologies Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 Google, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mfd/syscon.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/regmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include "virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MDC_MAX_DMA_CHANNELS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MDC_GENERAL_CONFIG 0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MDC_GENERAL_CONFIG_LIST_IEN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MDC_GENERAL_CONFIG_IEN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MDC_GENERAL_CONFIG_LEVEL_INT BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MDC_GENERAL_CONFIG_INC_W BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MDC_GENERAL_CONFIG_INC_R BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MDC_GENERAL_CONFIG_PHYSICAL_W BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MDC_GENERAL_CONFIG_WIDTH_W_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MDC_GENERAL_CONFIG_WIDTH_W_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MDC_GENERAL_CONFIG_PHYSICAL_R BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MDC_GENERAL_CONFIG_WIDTH_R_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MDC_GENERAL_CONFIG_WIDTH_R_MASK 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MDC_READ_PORT_CONFIG 0x004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MDC_READ_PORT_CONFIG_STHREAD_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MDC_READ_PORT_CONFIG_STHREAD_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MDC_READ_PORT_CONFIG_RTHREAD_SHIFT 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MDC_READ_PORT_CONFIG_RTHREAD_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MDC_READ_PORT_CONFIG_WTHREAD_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MDC_READ_PORT_CONFIG_WTHREAD_MASK 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MDC_READ_PORT_CONFIG_BURST_SIZE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MDC_READ_PORT_CONFIG_BURST_SIZE_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MDC_READ_PORT_CONFIG_DREQ_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MDC_READ_ADDRESS 0x008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MDC_WRITE_ADDRESS 0x00c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MDC_TRANSFER_SIZE 0x010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MDC_TRANSFER_SIZE_MASK 0xffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MDC_LIST_NODE_ADDRESS 0x014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MDC_CMDS_PROCESSED 0x018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MDC_CMDS_PROCESSED_CMDS_PROCESSED_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MDC_CMDS_PROCESSED_CMDS_PROCESSED_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MDC_CMDS_PROCESSED_INT_ACTIVE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MDC_CMDS_PROCESSED_CMDS_DONE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define MDC_CMDS_PROCESSED_CMDS_DONE_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define MDC_CONTROL_AND_STATUS 0x01c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define MDC_CONTROL_AND_STATUS_CANCEL BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define MDC_CONTROL_AND_STATUS_LIST_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define MDC_CONTROL_AND_STATUS_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define MDC_ACTIVE_TRANSFER_SIZE 0x030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define MDC_GLOBAL_CONFIG_A 0x900
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define MDC_GLOBAL_CONFIG_A_THREAD_ID_WIDTH_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define MDC_GLOBAL_CONFIG_A_THREAD_ID_WIDTH_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MDC_GLOBAL_CONFIG_A_DMA_CONTEXTS_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define MDC_GLOBAL_CONFIG_A_DMA_CONTEXTS_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define MDC_GLOBAL_CONFIG_A_SYS_DAT_WIDTH_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define MDC_GLOBAL_CONFIG_A_SYS_DAT_WIDTH_MASK 0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct mdc_hw_list_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 gen_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 readport_conf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 read_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 write_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 node_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 cmds_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 ctrl_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Not part of the list descriptor, but instead used by the CPU to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * traverse the list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct mdc_hw_list_desc *next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct mdc_tx_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) struct mdc_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct virt_dma_desc vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) dma_addr_t list_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct mdc_hw_list_desc *list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) bool cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bool cmd_loaded;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int list_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int list_period_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) size_t list_xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int list_cmds_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct mdc_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct mdc_dma *mdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct virt_dma_chan vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) struct dma_slave_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) struct mdc_tx_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int periph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int thread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int chan_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct mdc_dma_soc_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void (*enable_chan)(struct mdc_chan *mchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) void (*disable_chan)(struct mdc_chan *mchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct mdc_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct dma_device dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct dma_pool *desc_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct regmap *periph_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int nr_threads;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int max_burst_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned int max_xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) const struct mdc_dma_soc_data *soc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) struct mdc_chan channels[MDC_MAX_DMA_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) static inline u32 mdc_readl(struct mdc_dma *mdma, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return readl(mdma->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) static inline void mdc_writel(struct mdc_dma *mdma, u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) writel(val, mdma->regs + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static inline u32 mdc_chan_readl(struct mdc_chan *mchan, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return mdc_readl(mchan->mdma, mchan->chan_nr * 0x040 + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) static inline void mdc_chan_writel(struct mdc_chan *mchan, u32 val, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) mdc_writel(mchan->mdma, val, mchan->chan_nr * 0x040 + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) static inline struct mdc_chan *to_mdc_chan(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return container_of(to_virt_chan(c), struct mdc_chan, vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static inline struct mdc_tx_desc *to_mdc_desc(struct dma_async_tx_descriptor *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct virt_dma_desc *vdesc = container_of(t, struct virt_dma_desc, tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return container_of(vdesc, struct mdc_tx_desc, vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static inline struct device *mdma2dev(struct mdc_dma *mdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return mdma->dma_dev.dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static inline unsigned int to_mdc_width(unsigned int bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return ffs(bytes) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) static inline void mdc_set_read_width(struct mdc_hw_list_desc *ldesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) unsigned int bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) ldesc->gen_conf |= to_mdc_width(bytes) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) MDC_GENERAL_CONFIG_WIDTH_R_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static inline void mdc_set_write_width(struct mdc_hw_list_desc *ldesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) unsigned int bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) ldesc->gen_conf |= to_mdc_width(bytes) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) MDC_GENERAL_CONFIG_WIDTH_W_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static void mdc_list_desc_config(struct mdc_chan *mchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct mdc_hw_list_desc *ldesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) enum dma_transfer_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) dma_addr_t src, dma_addr_t dst, size_t len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct mdc_dma *mdma = mchan->mdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) unsigned int max_burst, burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) ldesc->gen_conf = MDC_GENERAL_CONFIG_IEN | MDC_GENERAL_CONFIG_LIST_IEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) MDC_GENERAL_CONFIG_LEVEL_INT | MDC_GENERAL_CONFIG_PHYSICAL_W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) MDC_GENERAL_CONFIG_PHYSICAL_R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) ldesc->readport_conf =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) (mchan->thread << MDC_READ_PORT_CONFIG_STHREAD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) (mchan->thread << MDC_READ_PORT_CONFIG_RTHREAD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) (mchan->thread << MDC_READ_PORT_CONFIG_WTHREAD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) ldesc->read_addr = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) ldesc->write_addr = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ldesc->xfer_size = len - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ldesc->node_addr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) ldesc->cmds_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) ldesc->ctrl_status = MDC_CONTROL_AND_STATUS_LIST_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MDC_CONTROL_AND_STATUS_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ldesc->next_desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) if (IS_ALIGNED(dst, mdma->bus_width) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) IS_ALIGNED(src, mdma->bus_width))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) max_burst = mdma->bus_width * mdma->max_burst_mult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) max_burst = mdma->bus_width * (mdma->max_burst_mult - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) ldesc->gen_conf |= MDC_GENERAL_CONFIG_INC_R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) ldesc->readport_conf |= MDC_READ_PORT_CONFIG_DREQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) mdc_set_read_width(ldesc, mdma->bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) mdc_set_write_width(ldesc, mchan->config.dst_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) burst_size = min(max_burst, mchan->config.dst_maxburst *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) mchan->config.dst_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) } else if (dir == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) ldesc->gen_conf |= MDC_GENERAL_CONFIG_INC_W;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) ldesc->readport_conf |= MDC_READ_PORT_CONFIG_DREQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) mdc_set_read_width(ldesc, mchan->config.src_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) mdc_set_write_width(ldesc, mdma->bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) burst_size = min(max_burst, mchan->config.src_maxburst *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) mchan->config.src_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) ldesc->gen_conf |= MDC_GENERAL_CONFIG_INC_R |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) MDC_GENERAL_CONFIG_INC_W;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) mdc_set_read_width(ldesc, mdma->bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) mdc_set_write_width(ldesc, mdma->bus_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) burst_size = max_burst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) ldesc->readport_conf |= (burst_size - 1) <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) MDC_READ_PORT_CONFIG_BURST_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) static void mdc_list_desc_free(struct mdc_tx_desc *mdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) struct mdc_dma *mdma = mdesc->chan->mdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct mdc_hw_list_desc *curr, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dma_addr_t curr_phys, next_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) curr = mdesc->list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) curr_phys = mdesc->list_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) while (curr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) next = curr->next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) next_phys = curr->node_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dma_pool_free(mdma->desc_pool, curr, curr_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) curr = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) curr_phys = next_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) static void mdc_desc_free(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct mdc_tx_desc *mdesc = to_mdc_desc(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) mdc_list_desc_free(mdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) kfree(mdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) static struct dma_async_tx_descriptor *mdc_prep_dma_memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct dma_chan *chan, dma_addr_t dest, dma_addr_t src, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct mdc_chan *mchan = to_mdc_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct mdc_dma *mdma = mchan->mdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) struct mdc_tx_desc *mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct mdc_hw_list_desc *curr, *prev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) dma_addr_t curr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (!len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mdesc = kzalloc(sizeof(*mdesc), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (!mdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) mdesc->chan = mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) mdesc->list_xfer_size = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) while (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) size_t xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) curr = dma_pool_alloc(mdma->desc_pool, GFP_NOWAIT, &curr_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (!curr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) goto free_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (prev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) prev->node_addr = curr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) prev->next_desc = curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) mdesc->list_phys = curr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) mdesc->list = curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) xfer_size = min_t(size_t, mdma->max_xfer_size, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) mdc_list_desc_config(mchan, curr, DMA_MEM_TO_MEM, src, dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) xfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) prev = curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mdesc->list_len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) src += xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dest += xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) len -= xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return vchan_tx_prep(&mchan->vc, &mdesc->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) free_desc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) mdc_desc_free(&mdesc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int mdc_check_slave_width(struct mdc_chan *mchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) enum dma_transfer_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) enum dma_slave_buswidth width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) if (dir == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) width = mchan->config.dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) width = mchan->config.src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) case DMA_SLAVE_BUSWIDTH_8_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (width > mchan->mdma->bus_width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) static struct dma_async_tx_descriptor *mdc_prep_dma_cyclic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) size_t period_len, enum dma_transfer_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) struct mdc_chan *mchan = to_mdc_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) struct mdc_dma *mdma = mchan->mdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) struct mdc_tx_desc *mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct mdc_hw_list_desc *curr, *prev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dma_addr_t curr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) if (!buf_len && !period_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!is_slave_direction(dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (mdc_check_slave_width(mchan, dir) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) mdesc = kzalloc(sizeof(*mdesc), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (!mdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) mdesc->chan = mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) mdesc->cyclic = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) mdesc->list_xfer_size = buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) mdesc->list_period_len = DIV_ROUND_UP(period_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) mdma->max_xfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) while (buf_len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) size_t remainder = min(period_len, buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) while (remainder > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) size_t xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) curr = dma_pool_alloc(mdma->desc_pool, GFP_NOWAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) &curr_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) if (!curr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) goto free_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!prev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) mdesc->list_phys = curr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) mdesc->list = curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) prev->node_addr = curr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) prev->next_desc = curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) xfer_size = min_t(size_t, mdma->max_xfer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) remainder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) mdc_list_desc_config(mchan, curr, dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) buf_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) mchan->config.dst_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) xfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) mdc_list_desc_config(mchan, curr, dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) mchan->config.src_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) buf_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) xfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) prev = curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) mdesc->list_len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) buf_addr += xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) buf_len -= xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) remainder -= xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) prev->node_addr = mdesc->list_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) return vchan_tx_prep(&mchan->vc, &mdesc->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) free_desc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) mdc_desc_free(&mdesc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) static struct dma_async_tx_descriptor *mdc_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct dma_chan *chan, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned int sg_len, enum dma_transfer_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned long flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) struct mdc_chan *mchan = to_mdc_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) struct mdc_dma *mdma = mchan->mdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct mdc_tx_desc *mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct mdc_hw_list_desc *curr, *prev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dma_addr_t curr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (!sgl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (!is_slave_direction(dir))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (mdc_check_slave_width(mchan, dir) < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) mdesc = kzalloc(sizeof(*mdesc), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) if (!mdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) mdesc->chan = mchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) for_each_sg(sgl, sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) dma_addr_t buf = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) size_t buf_len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) while (buf_len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) size_t xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) curr = dma_pool_alloc(mdma->desc_pool, GFP_NOWAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) &curr_phys);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (!curr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) goto free_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (!prev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) mdesc->list_phys = curr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) mdesc->list = curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) prev->node_addr = curr_phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) prev->next_desc = curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) xfer_size = min_t(size_t, mdma->max_xfer_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) buf_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) mdc_list_desc_config(mchan, curr, dir, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) mchan->config.dst_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) xfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) mdc_list_desc_config(mchan, curr, dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) mchan->config.src_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) buf, xfer_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) prev = curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) mdesc->list_len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) mdesc->list_xfer_size += xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) buf += xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) buf_len -= xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return vchan_tx_prep(&mchan->vc, &mdesc->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) free_desc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) mdc_desc_free(&mdesc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static void mdc_issue_desc(struct mdc_chan *mchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct mdc_dma *mdma = mchan->mdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) struct virt_dma_desc *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct mdc_tx_desc *mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) vd = vchan_next_desc(&mchan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) if (!vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) list_del(&vd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mdesc = to_mdc_desc(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) mchan->desc = mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev_dbg(mdma2dev(mdma), "Issuing descriptor on channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mchan->chan_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) mdma->soc->enable_chan(mchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) val = mdc_chan_readl(mchan, MDC_GENERAL_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) val |= MDC_GENERAL_CONFIG_LIST_IEN | MDC_GENERAL_CONFIG_IEN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) MDC_GENERAL_CONFIG_LEVEL_INT | MDC_GENERAL_CONFIG_PHYSICAL_W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) MDC_GENERAL_CONFIG_PHYSICAL_R;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) mdc_chan_writel(mchan, val, MDC_GENERAL_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) val = (mchan->thread << MDC_READ_PORT_CONFIG_STHREAD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) (mchan->thread << MDC_READ_PORT_CONFIG_RTHREAD_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) (mchan->thread << MDC_READ_PORT_CONFIG_WTHREAD_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mdc_chan_writel(mchan, val, MDC_READ_PORT_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) mdc_chan_writel(mchan, mdesc->list_phys, MDC_LIST_NODE_ADDRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) val = mdc_chan_readl(mchan, MDC_CONTROL_AND_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) val |= MDC_CONTROL_AND_STATUS_LIST_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mdc_chan_writel(mchan, val, MDC_CONTROL_AND_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static void mdc_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) struct mdc_chan *mchan = to_mdc_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) spin_lock_irqsave(&mchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (vchan_issue_pending(&mchan->vc) && !mchan->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) mdc_issue_desc(mchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) spin_unlock_irqrestore(&mchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static enum dma_status mdc_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dma_cookie_t cookie, struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct mdc_chan *mchan = to_mdc_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) struct mdc_tx_desc *mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) struct virt_dma_desc *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) size_t bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ret == DMA_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) if (!txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) spin_lock_irqsave(&mchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) vd = vchan_find_desc(&mchan->vc, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (vd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) mdesc = to_mdc_desc(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) bytes = mdesc->list_xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) } else if (mchan->desc && mchan->desc->vd.tx.cookie == cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct mdc_hw_list_desc *ldesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 val1, val2, done, processed, residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int i, cmds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) mdesc = mchan->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * Determine the number of commands that haven't been
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * processed (handled by the IRQ handler) yet.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) val1 = mdc_chan_readl(mchan, MDC_CMDS_PROCESSED) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ~MDC_CMDS_PROCESSED_INT_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) residue = mdc_chan_readl(mchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MDC_ACTIVE_TRANSFER_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) val2 = mdc_chan_readl(mchan, MDC_CMDS_PROCESSED) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) ~MDC_CMDS_PROCESSED_INT_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) } while (val1 != val2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) done = (val1 >> MDC_CMDS_PROCESSED_CMDS_DONE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) MDC_CMDS_PROCESSED_CMDS_DONE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) processed = (val1 >> MDC_CMDS_PROCESSED_CMDS_PROCESSED_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) MDC_CMDS_PROCESSED_CMDS_PROCESSED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) cmds = (done - processed) %
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) (MDC_CMDS_PROCESSED_CMDS_DONE_MASK + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) * If the command loaded event hasn't been processed yet, then
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) * the difference above includes an extra command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!mdesc->cmd_loaded)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) cmds--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) cmds += mdesc->list_cmds_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) bytes = mdesc->list_xfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) ldesc = mdesc->list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) for (i = 0; i < cmds; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) bytes -= ldesc->xfer_size + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ldesc = ldesc->next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (ldesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (residue != MDC_TRANSFER_SIZE_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) bytes -= ldesc->xfer_size - residue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) bytes -= ldesc->xfer_size + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) spin_unlock_irqrestore(&mchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) dma_set_residue(txstate, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static unsigned int mdc_get_new_events(struct mdc_chan *mchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) u32 val, processed, done1, done2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) unsigned int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) val = mdc_chan_readl(mchan, MDC_CMDS_PROCESSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) processed = (val >> MDC_CMDS_PROCESSED_CMDS_PROCESSED_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) MDC_CMDS_PROCESSED_CMDS_PROCESSED_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) * CMDS_DONE may have incremented between reading CMDS_PROCESSED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) * and clearing INT_ACTIVE. Re-read CMDS_PROCESSED to ensure we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) * didn't miss a command completion.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) val = mdc_chan_readl(mchan, MDC_CMDS_PROCESSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) done1 = (val >> MDC_CMDS_PROCESSED_CMDS_DONE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) MDC_CMDS_PROCESSED_CMDS_DONE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) val &= ~((MDC_CMDS_PROCESSED_CMDS_PROCESSED_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) MDC_CMDS_PROCESSED_CMDS_PROCESSED_SHIFT) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) MDC_CMDS_PROCESSED_INT_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) val |= done1 << MDC_CMDS_PROCESSED_CMDS_PROCESSED_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) mdc_chan_writel(mchan, val, MDC_CMDS_PROCESSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) val = mdc_chan_readl(mchan, MDC_CMDS_PROCESSED);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) done2 = (val >> MDC_CMDS_PROCESSED_CMDS_DONE_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) MDC_CMDS_PROCESSED_CMDS_DONE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) } while (done1 != done2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (done1 >= processed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) ret = done1 - processed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) ret = ((MDC_CMDS_PROCESSED_CMDS_PROCESSED_MASK + 1) -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) processed) + done1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static int mdc_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct mdc_chan *mchan = to_mdc_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) spin_lock_irqsave(&mchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) mdc_chan_writel(mchan, MDC_CONTROL_AND_STATUS_CANCEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) MDC_CONTROL_AND_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) if (mchan->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) vchan_terminate_vdesc(&mchan->desc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) mchan->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) vchan_get_all_descriptors(&mchan->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) mdc_get_new_events(mchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) spin_unlock_irqrestore(&mchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) vchan_dma_desc_free_list(&mchan->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static void mdc_synchronize(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct mdc_chan *mchan = to_mdc_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) vchan_synchronize(&mchan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) static int mdc_slave_config(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) struct dma_slave_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct mdc_chan *mchan = to_mdc_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) spin_lock_irqsave(&mchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) mchan->config = *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) spin_unlock_irqrestore(&mchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static int mdc_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct mdc_chan *mchan = to_mdc_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct device *dev = mdma2dev(mchan->mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static void mdc_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct mdc_chan *mchan = to_mdc_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct mdc_dma *mdma = mchan->mdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct device *dev = mdma2dev(mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) mdc_terminate_all(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) mdma->soc->disable_chan(mchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) pm_runtime_put(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static irqreturn_t mdc_chan_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) struct mdc_chan *mchan = (struct mdc_chan *)dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct mdc_tx_desc *mdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) unsigned int i, new_events;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) spin_lock(&mchan->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) dev_dbg(mdma2dev(mchan->mdma), "IRQ on channel %d\n", mchan->chan_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) new_events = mdc_get_new_events(mchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (!new_events)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) mdesc = mchan->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (!mdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) dev_warn(mdma2dev(mchan->mdma),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) "IRQ with no active descriptor on channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) mchan->chan_nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) for (i = 0; i < new_events; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) * The first interrupt in a transfer indicates that the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * command list has been loaded, not that a command has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * been completed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) if (!mdesc->cmd_loaded) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) mdesc->cmd_loaded = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) mdesc->list_cmds_done++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) if (mdesc->cyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) mdesc->list_cmds_done %= mdesc->list_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (mdesc->list_cmds_done % mdesc->list_period_len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) vchan_cyclic_callback(&mdesc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) } else if (mdesc->list_cmds_done == mdesc->list_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) mchan->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) vchan_cookie_complete(&mdesc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) mdc_issue_desc(mchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) spin_unlock(&mchan->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static struct dma_chan *mdc_of_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) struct mdc_dma *mdma = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) if (dma_spec->args_count != 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) list_for_each_entry(chan, &mdma->dma_dev.channels, device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct mdc_chan *mchan = to_mdc_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (!(dma_spec->args[1] & BIT(mchan->chan_nr)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) if (dma_get_slave_channel(chan)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) mchan->periph = dma_spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) mchan->thread = dma_spec->args[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define PISTACHIO_CR_PERIPH_DMA_ROUTE(ch) (0x120 + 0x4 * ((ch) / 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #define PISTACHIO_CR_PERIPH_DMA_ROUTE_SHIFT(ch) (8 * ((ch) % 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define PISTACHIO_CR_PERIPH_DMA_ROUTE_MASK 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static void pistachio_mdc_enable_chan(struct mdc_chan *mchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct mdc_dma *mdma = mchan->mdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) regmap_update_bits(mdma->periph_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) PISTACHIO_CR_PERIPH_DMA_ROUTE(mchan->chan_nr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) PISTACHIO_CR_PERIPH_DMA_ROUTE_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) PISTACHIO_CR_PERIPH_DMA_ROUTE_SHIFT(mchan->chan_nr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) mchan->periph <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) PISTACHIO_CR_PERIPH_DMA_ROUTE_SHIFT(mchan->chan_nr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static void pistachio_mdc_disable_chan(struct mdc_chan *mchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct mdc_dma *mdma = mchan->mdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) regmap_update_bits(mdma->periph_regs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) PISTACHIO_CR_PERIPH_DMA_ROUTE(mchan->chan_nr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) PISTACHIO_CR_PERIPH_DMA_ROUTE_MASK <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) PISTACHIO_CR_PERIPH_DMA_ROUTE_SHIFT(mchan->chan_nr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static const struct mdc_dma_soc_data pistachio_mdc_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) .enable_chan = pistachio_mdc_enable_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) .disable_chan = pistachio_mdc_disable_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static const struct of_device_id mdc_dma_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) { .compatible = "img,pistachio-mdc-dma", .data = &pistachio_mdc_data, },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) MODULE_DEVICE_TABLE(of, mdc_dma_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) static int img_mdc_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) struct mdc_dma *mdma = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) clk_disable_unprepare(mdma->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) static int img_mdc_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct mdc_dma *mdma = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) return clk_prepare_enable(mdma->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) static int mdc_dma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) struct mdc_dma *mdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) mdma = devm_kzalloc(&pdev->dev, sizeof(*mdma), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (!mdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) platform_set_drvdata(pdev, mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) mdma->soc = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) mdma->regs = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) if (IS_ERR(mdma->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) return PTR_ERR(mdma->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) mdma->periph_regs = syscon_regmap_lookup_by_phandle(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) "img,cr-periph");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (IS_ERR(mdma->periph_regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return PTR_ERR(mdma->periph_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) mdma->clk = devm_clk_get(&pdev->dev, "sys");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (IS_ERR(mdma->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) return PTR_ERR(mdma->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dma_cap_zero(mdma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dma_cap_set(DMA_SLAVE, mdma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) dma_cap_set(DMA_PRIVATE, mdma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dma_cap_set(DMA_CYCLIC, mdma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dma_cap_set(DMA_MEMCPY, mdma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) val = mdc_readl(mdma, MDC_GLOBAL_CONFIG_A);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) mdma->nr_channels = (val >> MDC_GLOBAL_CONFIG_A_DMA_CONTEXTS_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) MDC_GLOBAL_CONFIG_A_DMA_CONTEXTS_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) mdma->nr_threads =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) 1 << ((val >> MDC_GLOBAL_CONFIG_A_THREAD_ID_WIDTH_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) MDC_GLOBAL_CONFIG_A_THREAD_ID_WIDTH_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) mdma->bus_width =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) (1 << ((val >> MDC_GLOBAL_CONFIG_A_SYS_DAT_WIDTH_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) MDC_GLOBAL_CONFIG_A_SYS_DAT_WIDTH_MASK)) / 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) * Although transfer sizes of up to MDC_TRANSFER_SIZE_MASK + 1 bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) * are supported, this makes it possible for the value reported in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) * MDC_ACTIVE_TRANSFER_SIZE to be ambiguous - an active transfer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * of MDC_TRANSFER_SIZE_MASK may indicate either that 0 bytes or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * MDC_TRANSFER_SIZE_MASK + 1 bytes are remaining. To eliminate this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) * ambiguity, restrict transfer sizes to one bus-width less than the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) * actual maximum.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) mdma->max_xfer_size = MDC_TRANSFER_SIZE_MASK + 1 - mdma->bus_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) of_property_read_u32(pdev->dev.of_node, "dma-channels",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) &mdma->nr_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) ret = of_property_read_u32(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) "img,max-burst-multiplier",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) &mdma->max_burst_mult);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) mdma->dma_dev.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) mdma->dma_dev.device_prep_slave_sg = mdc_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) mdma->dma_dev.device_prep_dma_cyclic = mdc_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) mdma->dma_dev.device_prep_dma_memcpy = mdc_prep_dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) mdma->dma_dev.device_alloc_chan_resources = mdc_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) mdma->dma_dev.device_free_chan_resources = mdc_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) mdma->dma_dev.device_tx_status = mdc_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) mdma->dma_dev.device_issue_pending = mdc_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) mdma->dma_dev.device_terminate_all = mdc_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) mdma->dma_dev.device_synchronize = mdc_synchronize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) mdma->dma_dev.device_config = mdc_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) mdma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) mdma->dma_dev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) for (i = 1; i <= mdma->bus_width; i <<= 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) mdma->dma_dev.src_addr_widths |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) mdma->dma_dev.dst_addr_widths |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) INIT_LIST_HEAD(&mdma->dma_dev.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) for (i = 0; i < mdma->nr_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) struct mdc_chan *mchan = &mdma->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) mchan->mdma = mdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) mchan->chan_nr = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) mchan->irq = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (mchan->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) return mchan->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) ret = devm_request_irq(&pdev->dev, mchan->irq, mdc_chan_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) IRQ_TYPE_LEVEL_HIGH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dev_name(&pdev->dev), mchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) mchan->vc.desc_free = mdc_desc_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) vchan_init(&mchan->vc, &mdma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) mdma->desc_pool = dmam_pool_create(dev_name(&pdev->dev), &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) sizeof(struct mdc_hw_list_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) 4, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) if (!mdma->desc_pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) pm_runtime_enable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) if (!pm_runtime_enabled(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) ret = img_mdc_runtime_resume(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) ret = dma_async_device_register(&mdma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) goto suspend;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) ret = of_dma_controller_register(pdev->dev.of_node, mdc_of_xlate, mdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) goto unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) dev_info(&pdev->dev, "MDC with %u channels and %u threads\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) mdma->nr_channels, mdma->nr_threads);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dma_async_device_unregister(&mdma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) suspend:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (!pm_runtime_enabled(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) img_mdc_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) static int mdc_dma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct mdc_dma *mdma = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct mdc_chan *mchan, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) of_dma_controller_free(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dma_async_device_unregister(&mdma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) list_for_each_entry_safe(mchan, next, &mdma->dma_dev.channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) vc.chan.device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) list_del(&mchan->vc.chan.device_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) devm_free_irq(&pdev->dev, mchan->irq, mchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) tasklet_kill(&mchan->vc.task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) if (!pm_runtime_status_suspended(&pdev->dev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) img_mdc_runtime_suspend(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) static int img_mdc_suspend_late(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) struct mdc_dma *mdma = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) /* Check that all channels are idle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) for (i = 0; i < mdma->nr_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct mdc_chan *mchan = &mdma->channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) if (unlikely(mchan->desc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) static int img_mdc_resume_early(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) return pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) static const struct dev_pm_ops img_mdc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) SET_RUNTIME_PM_OPS(img_mdc_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) img_mdc_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) SET_LATE_SYSTEM_SLEEP_PM_OPS(img_mdc_suspend_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) img_mdc_resume_early)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) static struct platform_driver mdc_dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .name = "img-mdc-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) .pm = &img_mdc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) .of_match_table = of_match_ptr(mdc_dma_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .probe = mdc_dma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .remove = mdc_dma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) module_platform_driver(mdc_dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) MODULE_DESCRIPTION("IMG Multi-threaded DMA Controller (MDC) driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) MODULE_AUTHOR("Andrew Bresticker <abrestic@chromium.org>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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