^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright(c) 2019 Intel Corporation. All rights rsvd. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #ifndef _IDXD_REGISTERS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define _IDXD_REGISTERS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) /* PCI Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define PCI_DEVICE_ID_INTEL_DSA_SPR0 0x0b25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define IDXD_MMIO_BAR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define IDXD_WQ_BAR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define IDXD_PORTAL_SIZE PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* MMIO Device BAR0 Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IDXD_VER_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IDXD_VER_MAJOR_MASK 0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IDXD_VER_MINOR_MASK 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define GET_IDXD_VER_MAJOR(x) (((x) & IDXD_VER_MAJOR_MASK) >> 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define GET_IDXD_VER_MINOR(x) ((x) & IDXD_VER_MINOR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) union gen_cap_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u64 block_on_fault:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) u64 overlap_copy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u64 cache_control_mem:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u64 cache_control_cache:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) u64 rsvd:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) u64 int_handle_req:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u64 dest_readback:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u64 drain_readback:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u64 rsvd2:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u64 max_xfer_shift:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u64 max_batch_shift:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u64 max_ims_mult:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u64 config_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u64 max_descs_per_engine:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u64 rsvd3:24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u64 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IDXD_GENCAP_OFFSET 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) union wq_cap_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u64 total_wq_size:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u64 num_wqs:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u64 wqcfg_size:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u64 rsvd:20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u64 shared_mode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u64 dedicated_mode:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u64 rsvd2:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u64 priority:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u64 occupancy:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u64 occupancy_int:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u64 rsvd3:10;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u64 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IDXD_WQCAP_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IDXD_WQCFG_MIN 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) union group_cap_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u64 num_groups:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u64 total_tokens:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u64 token_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u64 token_limit:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u64 rsvd:46;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u64 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IDXD_GRPCAP_OFFSET 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) union engine_cap_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) u64 num_engines:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u64 rsvd:56;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u64 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IDXD_ENGCAP_OFFSET 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IDXD_OPCAP_NOOP 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IDXD_OPCAP_BATCH 0x0002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IDXD_OPCAP_MEMMOVE 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct opcap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u64 bits[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IDXD_OPCAP_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IDXD_TABLE_OFFSET 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) union offsets_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u64 grpcfg:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u64 wqcfg:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u64 msix_perm:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u64 ims:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) u64 perfmon:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u64 rsvd:48;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u64 bits[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IDXD_GENCFG_OFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) union gencfg_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 token_limit:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 rsvd:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 user_int_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 rsvd2:19;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IDXD_GENCTRL_OFFSET 0x88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) union genctrl_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 softerr_int_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 rsvd:31;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IDXD_GENSTATS_OFFSET 0x90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) union gensts_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 state:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 reset_type:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 rsvd:28;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) enum idxd_device_status_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) IDXD_DEVICE_STATE_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) IDXD_DEVICE_STATE_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) IDXD_DEVICE_STATE_DRAIN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) IDXD_DEVICE_STATE_HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) enum idxd_device_reset_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) IDXD_DEVICE_RESET_SOFTWARE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) IDXD_DEVICE_RESET_FLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) IDXD_DEVICE_RESET_WARM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) IDXD_DEVICE_RESET_COLD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IDXD_INTCAUSE_OFFSET 0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IDXD_INTC_ERR 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IDXD_INTC_CMD 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IDXD_INTC_OCCUPY 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IDXD_INTC_PERFMON_OVFL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IDXD_CMD_OFFSET 0xa0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) union idxd_command_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 operand:20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) u32 cmd:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) u32 rsvd:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u32 int_req:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) u32 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) enum idxd_cmd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) IDXD_CMD_ENABLE_DEVICE = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) IDXD_CMD_DISABLE_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) IDXD_CMD_DRAIN_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) IDXD_CMD_ABORT_ALL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) IDXD_CMD_RESET_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) IDXD_CMD_ENABLE_WQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) IDXD_CMD_DISABLE_WQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) IDXD_CMD_DRAIN_WQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) IDXD_CMD_ABORT_WQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) IDXD_CMD_RESET_WQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) IDXD_CMD_DRAIN_PASID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) IDXD_CMD_ABORT_PASID,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) IDXD_CMD_REQUEST_INT_HANDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IDXD_CMDSTS_OFFSET 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) union cmdsts_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u8 err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u16 result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) u8 rsvd:7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u8 active:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IDXD_CMDSTS_ACTIVE 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) enum idxd_cmdsts_err {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) IDXD_CMDSTS_SUCCESS = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) IDXD_CMDSTS_INVAL_CMD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) IDXD_CMDSTS_INVAL_WQIDX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) IDXD_CMDSTS_HW_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* enable device errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) IDXD_CMDSTS_ERR_DEV_ENABLED = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) IDXD_CMDSTS_ERR_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) IDXD_CMDSTS_ERR_BUSMASTER_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) IDXD_CMDSTS_ERR_PASID_INVAL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) IDXD_CMDSTS_ERR_WQ_SIZE_ERANGE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) IDXD_CMDSTS_ERR_GRP_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) IDXD_CMDSTS_ERR_GRP_CONFIG2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) IDXD_CMDSTS_ERR_GRP_CONFIG3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) IDXD_CMDSTS_ERR_GRP_CONFIG4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* enable wq errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) IDXD_CMDSTS_ERR_DEV_NOTEN = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) IDXD_CMDSTS_ERR_WQ_ENABLED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) IDXD_CMDSTS_ERR_WQ_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) IDXD_CMDSTS_ERR_WQ_PRIOR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) IDXD_CMDSTS_ERR_WQ_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) IDXD_CMDSTS_ERR_BOF_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) IDXD_CMDSTS_ERR_PASID_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) IDXD_CMDSTS_ERR_MAX_BATCH_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) IDXD_CMDSTS_ERR_MAX_XFER_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* disable device errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) IDXD_CMDSTS_ERR_DIS_DEV_EN = 0x31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* disable WQ, drain WQ, abort WQ, reset WQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) IDXD_CMDSTS_ERR_DEV_NOT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* request interrupt handle */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) IDXD_CMDSTS_ERR_INVAL_INT_IDX = 0x41,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) IDXD_CMDSTS_ERR_NO_HANDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IDXD_SWERR_OFFSET 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IDXD_SWERR_VALID 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IDXD_SWERR_OVERFLOW 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IDXD_SWERR_ACK (IDXD_SWERR_VALID | IDXD_SWERR_OVERFLOW)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) union sw_err_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u64 valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u64 overflow:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u64 desc_valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u64 wq_idx_valid:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) u64 batch:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) u64 fault_rw:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u64 priv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u64 rsvd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) u64 error:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u64 wq_idx:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u64 rsvd2:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u64 operation:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) u64 pasid:20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) u64 rsvd3:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u64 batch_idx:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) u64 rsvd4:16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u64 invalid_flags:32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) u64 fault_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u64 rsvd5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) u64 bits[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) union msix_perm {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) u32 rsvd:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) u32 ignore:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 pasid_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) u32 rsvd2:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 pasid:20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) u32 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) union group_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) u32 tc_a:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) u32 tc_b:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u32 rsvd:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) u32 use_token_limit:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) u32 tokens_reserved:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) u32 rsvd2:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) u32 tokens_allowed:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) u32 rsvd3:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) u32 bits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct grpcfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) u64 wqs[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) u64 engines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) union group_flags flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) union wqcfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* bytes 0-3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) u16 wq_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) u16 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* bytes 4-7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) u16 wq_thresh;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u16 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* bytes 8-11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) u32 mode:1; /* shared or dedicated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 bof:1; /* block on fault */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) u32 rsvd2:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) u32 priority:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) u32 pasid:20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 pasid_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) u32 priv:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) u32 rsvd3:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* bytes 12-15 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) u32 max_xfer_shift:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) u32 max_batch_shift:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) u32 rsvd4:23;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* bytes 16-19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) u16 occupancy_inth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u16 occupancy_table_sel:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) u16 rsvd5:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* bytes 20-23 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) u16 occupancy_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u16 occupancy_int_en:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u16 rsvd6:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* bytes 24-27 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u16 occupancy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) u16 occupancy_int:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u16 rsvd7:12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u16 mode_support:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) u16 wq_state:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* bytes 28-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) u32 rsvd8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 bits[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * This macro calculates the offset into the WQCFG register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * idxd - struct idxd *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * n - wq id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * ofs - the index of the 32b dword for the config register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * The WQCFG register block is divided into groups per each wq. The n index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * allows us to move to the register group that's for that particular wq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * Each register is 32bits. The ofs gives us the number of register to access.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define WQCFG_OFFSET(_idxd_dev, n, ofs) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) ({\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) typeof(_idxd_dev) __idxd_dev = (_idxd_dev); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) (__idxd_dev)->wqcfg_offset + (n) * (__idxd_dev)->wqcfg_size + sizeof(u32) * (ofs); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define WQCFG_STRIDES(_idxd_dev) ((_idxd_dev)->wqcfg_size / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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