Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Driver for the Intel integrated DMA 64-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2015 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef __DMA_IDMA64_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define __DMA_IDMA64_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/io-64-nonatomic-lo-hi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #include "virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* Channel registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define IDMA64_CH_SAR		0x00	/* Source Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define IDMA64_CH_DAR		0x08	/* Destination Address Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define IDMA64_CH_LLP		0x10	/* Linked List Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define IDMA64_CH_CTL_LO	0x18	/* Control Register Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define IDMA64_CH_CTL_HI	0x1c	/* Control Register High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define IDMA64_CH_SSTAT		0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define IDMA64_CH_DSTAT		0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define IDMA64_CH_SSTATAR	0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define IDMA64_CH_DSTATAR	0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define IDMA64_CH_CFG_LO	0x40	/* Configuration Register Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define IDMA64_CH_CFG_HI	0x44	/* Configuration Register High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define IDMA64_CH_SGR		0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define IDMA64_CH_DSR		0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define IDMA64_CH_LENGTH	0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) /* Bitfields in CTL_LO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define IDMA64C_CTLL_INT_EN		(1 << 0)	/* irqs enabled? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define IDMA64C_CTLL_DST_WIDTH(x)	((x) << 1)	/* bytes per element */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define IDMA64C_CTLL_SRC_WIDTH(x)	((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define IDMA64C_CTLL_DST_INC		(0 << 8)	/* DAR update/not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define IDMA64C_CTLL_DST_FIX		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define IDMA64C_CTLL_SRC_INC		(0 << 10)	/* SAR update/not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define IDMA64C_CTLL_SRC_FIX		(1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define IDMA64C_CTLL_DST_MSIZE(x)	((x) << 11)	/* burst, #elements */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define IDMA64C_CTLL_SRC_MSIZE(x)	((x) << 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define IDMA64C_CTLL_FC_M2P		(1 << 20)	/* mem-to-periph */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define IDMA64C_CTLL_FC_P2M		(2 << 20)	/* periph-to-mem */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define IDMA64C_CTLL_LLP_D_EN		(1 << 27)	/* dest block chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define IDMA64C_CTLL_LLP_S_EN		(1 << 28)	/* src block chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) /* Bitfields in CTL_HI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define IDMA64C_CTLH_BLOCK_TS_MASK	((1 << 17) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define IDMA64C_CTLH_BLOCK_TS(x)	((x) & IDMA64C_CTLH_BLOCK_TS_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define IDMA64C_CTLH_DONE		(1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* Bitfields in CFG_LO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define IDMA64C_CFGL_DST_BURST_ALIGN	(1 << 0)	/* dst burst align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define IDMA64C_CFGL_SRC_BURST_ALIGN	(1 << 1)	/* src burst align */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define IDMA64C_CFGL_CH_SUSP		(1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define IDMA64C_CFGL_FIFO_EMPTY		(1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define IDMA64C_CFGL_CH_DRAIN		(1 << 10)	/* drain FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define IDMA64C_CFGL_DST_OPT_BL		(1 << 20)	/* optimize dst burst length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define IDMA64C_CFGL_SRC_OPT_BL		(1 << 21)	/* optimize src burst length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) /* Bitfields in CFG_HI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define IDMA64C_CFGH_SRC_PER(x)		((x) << 0)	/* src peripheral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define IDMA64C_CFGH_DST_PER(x)		((x) << 4)	/* dst peripheral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define IDMA64C_CFGH_RD_ISSUE_THD(x)	((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IDMA64C_CFGH_WR_ISSUE_THD(x)	((x) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) /* Interrupt registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define IDMA64_INT_XFER		0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define IDMA64_INT_BLOCK	0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define IDMA64_INT_SRC_TRAN	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define IDMA64_INT_DST_TRAN	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define IDMA64_INT_ERROR	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define IDMA64_RAW(x)		(0x2c0 + IDMA64_INT_##x)	/* r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define IDMA64_STATUS(x)	(0x2e8 + IDMA64_INT_##x)	/* r (raw & mask) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define IDMA64_MASK(x)		(0x310 + IDMA64_INT_##x)	/* rw (set = irq enabled) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define IDMA64_CLEAR(x)		(0x338 + IDMA64_INT_##x)	/* w (ack, affects "raw") */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* Common registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define IDMA64_STATUS_INT	0x360	/* r */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define IDMA64_CFG		0x398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define IDMA64_CH_EN		0x3a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* Bitfields in CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define IDMA64_CFG_DMA_EN		(1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) /* Hardware descriptor for Linked LIst transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) struct idma64_lli {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u64		sar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	u64		dar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	u64		llp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 	u32		ctllo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 	u32		ctlhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 	u32		sstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	u32		dstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct idma64_hw_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	struct idma64_lli *lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	dma_addr_t llp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) 	dma_addr_t phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 	unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct idma64_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	struct virt_dma_desc vdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	enum dma_transfer_direction direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	struct idma64_hw_desc *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	unsigned int ndesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	size_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static inline struct idma64_desc *to_idma64_desc(struct virt_dma_desc *vdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	return container_of(vdesc, struct idma64_desc, vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct idma64_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	struct virt_dma_chan vchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	/* hardware configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	enum dma_transfer_direction direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	unsigned int mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	struct dma_slave_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	void *pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	struct idma64_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static inline struct idma64_chan *to_idma64_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 	return container_of(chan, struct idma64_chan, vchan.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define channel_set_bit(idma64, reg, mask)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	dma_writel(idma64, reg, ((mask) << 8) | (mask))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define channel_clear_bit(idma64, reg, mask)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	dma_writel(idma64, reg, ((mask) << 8) | 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static inline u32 idma64c_readl(struct idma64_chan *idma64c, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	return readl(idma64c->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) static inline void idma64c_writel(struct idma64_chan *idma64c, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 				  u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	writel(value, idma64c->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define channel_readl(idma64c, reg)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	idma64c_readl(idma64c, IDMA64_CH_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define channel_writel(idma64c, reg, value)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	idma64c_writel(idma64c, IDMA64_CH_##reg, (value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline u64 idma64c_readq(struct idma64_chan *idma64c, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	return lo_hi_readq(idma64c->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline void idma64c_writeq(struct idma64_chan *idma64c, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 				  u64 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 	lo_hi_writeq(value, idma64c->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define channel_readq(idma64c, reg)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	idma64c_readq(idma64c, IDMA64_CH_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define channel_writeq(idma64c, reg, value)	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	idma64c_writeq(idma64c, IDMA64_CH_##reg, (value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct idma64 {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	struct dma_device dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	/* channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	unsigned short all_chan_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct idma64_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static inline struct idma64 *to_idma64(struct dma_device *ddev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	return container_of(ddev, struct idma64, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static inline u32 idma64_readl(struct idma64 *idma64, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	return readl(idma64->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static inline void idma64_writel(struct idma64 *idma64, int offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	writel(value, idma64->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define dma_readl(idma64, reg)			\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	idma64_readl(idma64, IDMA64_##reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define dma_writel(idma64, reg, value)		\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	idma64_writel(idma64, IDMA64_##reg, (value))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)  * struct idma64_chip - representation of iDMA 64-bit controller hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)  * @dev:		struct device of the DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)  * @sysdev:		struct device of the physical device that does DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)  * @irq:		irq line
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)  * @regs:		memory mapped I/O space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)  * @idma64:		struct idma64 that is filed by idma64_probe()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct idma64_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	struct device	*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct device	*sysdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	int		irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 	void __iomem	*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	struct idma64	*idma64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #endif /* __DMA_IDMA64_H__ */