^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Core driver for the Intel integrated DMA 64-bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/dma/idma64.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "idma64.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) /* For now we support only two channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IDMA64_NR_CHAN 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) static struct device *chan2dev(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return &chan->dev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) static void idma64_off(struct idma64 *idma64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) unsigned short count = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) dma_writel(idma64, CFG, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) channel_clear_bit(idma64, MASK(XFER), idma64->all_chan_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) channel_clear_bit(idma64, MASK(BLOCK), idma64->all_chan_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) channel_clear_bit(idma64, MASK(SRC_TRAN), idma64->all_chan_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) channel_clear_bit(idma64, MASK(DST_TRAN), idma64->all_chan_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) channel_clear_bit(idma64, MASK(ERROR), idma64->all_chan_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) } while (dma_readl(idma64, CFG) & IDMA64_CFG_DMA_EN && --count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static void idma64_on(struct idma64 *idma64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) dma_writel(idma64, CFG, IDMA64_CFG_DMA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) static void idma64_chan_init(struct idma64 *idma64, struct idma64_chan *idma64c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 cfghi = IDMA64C_CFGH_SRC_PER(1) | IDMA64C_CFGH_DST_PER(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 cfglo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /* Set default burst alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) cfglo |= IDMA64C_CFGL_DST_BURST_ALIGN | IDMA64C_CFGL_SRC_BURST_ALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) channel_writel(idma64c, CFG_LO, cfglo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) channel_writel(idma64c, CFG_HI, cfghi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* Enable interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) channel_set_bit(idma64, MASK(XFER), idma64c->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) channel_set_bit(idma64, MASK(ERROR), idma64c->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Enforce the controller to be turned on.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * The iDMA is turned off in ->probe() and looses context during system
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * suspend / resume cycle. That's why we have to enable it each time we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * use it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) idma64_on(idma64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) static void idma64_chan_stop(struct idma64 *idma64, struct idma64_chan *idma64c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) channel_clear_bit(idma64, CH_EN, idma64c->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) static void idma64_chan_start(struct idma64 *idma64, struct idma64_chan *idma64c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct idma64_desc *desc = idma64c->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct idma64_hw_desc *hw = &desc->hw[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) channel_writeq(idma64c, SAR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) channel_writeq(idma64c, DAR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) channel_writel(idma64c, CTL_HI, IDMA64C_CTLH_BLOCK_TS(~0UL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) channel_writel(idma64c, CTL_LO, IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) channel_writeq(idma64c, LLP, hw->llp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) channel_set_bit(idma64, CH_EN, idma64c->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void idma64_stop_transfer(struct idma64_chan *idma64c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) idma64_chan_stop(idma64, idma64c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static void idma64_start_transfer(struct idma64_chan *idma64c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct idma64 *idma64 = to_idma64(idma64c->vchan.chan.device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct virt_dma_desc *vdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* Get the next descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) vdesc = vchan_next_desc(&idma64c->vchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!vdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) idma64c->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) list_del(&vdesc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) idma64c->desc = to_idma64_desc(vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Configure the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) idma64_chan_init(idma64, idma64c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Start the channel with a new descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) idma64_chan_start(idma64, idma64c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void idma64_chan_irq(struct idma64 *idma64, unsigned short c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) u32 status_err, u32 status_xfer)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct idma64_chan *idma64c = &idma64->chan[c];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct idma64_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) spin_lock(&idma64c->vchan.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) desc = idma64c->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if (status_err & (1 << c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dma_writel(idma64, CLEAR(ERROR), idma64c->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) desc->status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) } else if (status_xfer & (1 << c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dma_writel(idma64, CLEAR(XFER), idma64c->mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) desc->status = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) vchan_cookie_complete(&desc->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) idma64_start_transfer(idma64c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* idma64_start_transfer() updates idma64c->desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (idma64c->desc == NULL || desc->status == DMA_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) idma64_stop_transfer(idma64c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) spin_unlock(&idma64c->vchan.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static irqreturn_t idma64_irq(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct idma64 *idma64 = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 status = dma_readl(idma64, STATUS_INT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u32 status_xfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u32 status_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) unsigned short i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) dev_vdbg(idma64->dma.dev, "%s: status=%#x\n", __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Check if we have any interrupt from the DMA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) if (!status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) status_xfer = dma_readl(idma64, RAW(XFER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) status_err = dma_readl(idma64, RAW(ERROR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) for (i = 0; i < idma64->dma.chancnt; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) idma64_chan_irq(idma64, i, status_err, status_xfer);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static struct idma64_desc *idma64_alloc_desc(unsigned int ndesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct idma64_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) desc->hw = kcalloc(ndesc, sizeof(*desc->hw), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (!desc->hw) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void idma64_desc_free(struct idma64_chan *idma64c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) struct idma64_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct idma64_hw_desc *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (desc->ndesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned int i = desc->ndesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) hw = &desc->hw[--i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dma_pool_free(idma64c->pool, hw->lli, hw->llp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) } while (i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) kfree(desc->hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void idma64_vdesc_free(struct virt_dma_desc *vdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct idma64_chan *idma64c = to_idma64_chan(vdesc->tx.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) idma64_desc_free(idma64c, to_idma64_desc(vdesc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void idma64_hw_desc_fill(struct idma64_hw_desc *hw,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) struct dma_slave_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) enum dma_transfer_direction direction, u64 llp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct idma64_lli *lli = hw->lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) u64 sar, dar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 ctlhi = IDMA64C_CTLH_BLOCK_TS(hw->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) u32 ctllo = IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 src_width, dst_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (direction == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) sar = hw->phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dar = config->dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) ctllo |= IDMA64C_CTLL_DST_FIX | IDMA64C_CTLL_SRC_INC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) IDMA64C_CTLL_FC_M2P;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) src_width = __ffs(sar | hw->len | 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dst_width = __ffs(config->dst_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) } else { /* DMA_DEV_TO_MEM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) sar = config->src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) dar = hw->phys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ctllo |= IDMA64C_CTLL_DST_INC | IDMA64C_CTLL_SRC_FIX |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) IDMA64C_CTLL_FC_P2M;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) src_width = __ffs(config->src_addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dst_width = __ffs(dar | hw->len | 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) lli->sar = sar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) lli->dar = dar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) lli->ctlhi = ctlhi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) lli->ctllo = ctllo |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) IDMA64C_CTLL_SRC_MSIZE(config->src_maxburst) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) IDMA64C_CTLL_DST_MSIZE(config->dst_maxburst) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) IDMA64C_CTLL_DST_WIDTH(dst_width) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) IDMA64C_CTLL_SRC_WIDTH(src_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) lli->llp = llp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static void idma64_desc_fill(struct idma64_chan *idma64c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct idma64_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) struct dma_slave_config *config = &idma64c->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) unsigned int i = desc->ndesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct idma64_hw_desc *hw = &desc->hw[i - 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct idma64_lli *lli = hw->lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) u64 llp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* Fill the hardware descriptors and link them to a list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) hw = &desc->hw[--i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) idma64_hw_desc_fill(hw, config, desc->direction, llp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) llp = hw->llp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) desc->length += hw->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) } while (i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /* Trigger an interrupt after the last block is transfered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) lli->ctllo |= IDMA64C_CTLL_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* Disable LLP transfer in the last block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) lli->ctllo &= ~(IDMA64C_CTLL_LLP_S_EN | IDMA64C_CTLL_LLP_D_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) static struct dma_async_tx_descriptor *idma64_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct dma_chan *chan, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) unsigned int sg_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) unsigned long flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct idma64_chan *idma64c = to_idma64_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) struct idma64_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) desc = idma64_alloc_desc(sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) for_each_sg(sgl, sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) struct idma64_hw_desc *hw = &desc->hw[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* Allocate DMA capable memory for hardware descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) hw->lli = dma_pool_alloc(idma64c->pool, GFP_NOWAIT, &hw->llp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) if (!hw->lli) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) desc->ndesc = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) idma64_desc_free(idma64c, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) hw->phys = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) hw->len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) desc->ndesc = sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) desc->direction = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) desc->status = DMA_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) idma64_desc_fill(idma64c, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return vchan_tx_prep(&idma64c->vchan, &desc->vdesc, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static void idma64_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct idma64_chan *idma64c = to_idma64_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) spin_lock_irqsave(&idma64c->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (vchan_issue_pending(&idma64c->vchan) && !idma64c->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) idma64_start_transfer(idma64c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static size_t idma64_active_desc_size(struct idma64_chan *idma64c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) struct idma64_desc *desc = idma64c->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct idma64_hw_desc *hw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) size_t bytes = desc->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) u64 llp = channel_readq(idma64c, LLP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) u32 ctlhi = channel_readl(idma64c, CTL_HI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) hw = &desc->hw[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) if (hw->llp == llp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) bytes -= hw->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) } while (++i < desc->ndesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (!i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) return bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* The current chunk is not fully transfered yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) bytes += desc->hw[--i].len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) return bytes - IDMA64C_CTLH_BLOCK_TS(ctlhi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) static enum dma_status idma64_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dma_cookie_t cookie, struct dma_tx_state *state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) struct idma64_chan *idma64c = to_idma64_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct virt_dma_desc *vdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) size_t bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) status = dma_cookie_status(chan, cookie, state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (status == DMA_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) spin_lock_irqsave(&idma64c->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) vdesc = vchan_find_desc(&idma64c->vchan, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (idma64c->desc && cookie == idma64c->desc->vdesc.tx.cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) bytes = idma64_active_desc_size(idma64c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dma_set_residue(state, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) status = idma64c->desc->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) } else if (vdesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) bytes = to_idma64_desc(vdesc)->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) dma_set_residue(state, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static void convert_burst(u32 *maxburst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (*maxburst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) *maxburst = __fls(*maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) *maxburst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static int idma64_slave_config(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct dma_slave_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) struct idma64_chan *idma64c = to_idma64_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) memcpy(&idma64c->config, config, sizeof(idma64c->config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) convert_burst(&idma64c->config.src_maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) convert_burst(&idma64c->config.dst_maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) static void idma64_chan_deactivate(struct idma64_chan *idma64c, bool drain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned short count = 100;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 cfglo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) cfglo = channel_readl(idma64c, CFG_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) if (drain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) cfglo |= IDMA64C_CFGL_CH_DRAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) cfglo &= ~IDMA64C_CFGL_CH_DRAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) channel_writel(idma64c, CFG_LO, cfglo | IDMA64C_CFGL_CH_SUSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) cfglo = channel_readl(idma64c, CFG_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) } while (!(cfglo & IDMA64C_CFGL_FIFO_EMPTY) && --count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void idma64_chan_activate(struct idma64_chan *idma64c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u32 cfglo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) cfglo = channel_readl(idma64c, CFG_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) channel_writel(idma64c, CFG_LO, cfglo & ~IDMA64C_CFGL_CH_SUSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) static int idma64_pause(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) struct idma64_chan *idma64c = to_idma64_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) spin_lock_irqsave(&idma64c->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) if (idma64c->desc && idma64c->desc->status == DMA_IN_PROGRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) idma64_chan_deactivate(idma64c, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) idma64c->desc->status = DMA_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) static int idma64_resume(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) struct idma64_chan *idma64c = to_idma64_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) spin_lock_irqsave(&idma64c->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (idma64c->desc && idma64c->desc->status == DMA_PAUSED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) idma64c->desc->status = DMA_IN_PROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) idma64_chan_activate(idma64c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int idma64_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) struct idma64_chan *idma64c = to_idma64_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) spin_lock_irqsave(&idma64c->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) idma64_chan_deactivate(idma64c, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) idma64_stop_transfer(idma64c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) if (idma64c->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) idma64_vdesc_free(&idma64c->desc->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) idma64c->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) vchan_get_all_descriptors(&idma64c->vchan, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) spin_unlock_irqrestore(&idma64c->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) vchan_dma_desc_free_list(&idma64c->vchan, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) static void idma64_synchronize(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) struct idma64_chan *idma64c = to_idma64_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) vchan_synchronize(&idma64c->vchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static int idma64_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) struct idma64_chan *idma64c = to_idma64_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /* Create a pool of consistent memory blocks for hardware descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) idma64c->pool = dma_pool_create(dev_name(chan2dev(chan)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) sizeof(struct idma64_lli), 8, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) if (!idma64c->pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) dev_err(chan2dev(chan), "No memory for descriptors\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) static void idma64_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) struct idma64_chan *idma64c = to_idma64_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) vchan_free_chan_resources(to_virt_chan(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dma_pool_destroy(idma64c->pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) idma64c->pool = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define IDMA64_BUSWIDTHS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) static int idma64_probe(struct idma64_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct idma64 *idma64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) unsigned short nr_chan = IDMA64_NR_CHAN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) unsigned short i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) idma64 = devm_kzalloc(chip->dev, sizeof(*idma64), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!idma64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) idma64->regs = chip->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) chip->idma64 = idma64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) idma64->chan = devm_kcalloc(chip->dev, nr_chan, sizeof(*idma64->chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) if (!idma64->chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) idma64->all_chan_mask = (1 << nr_chan) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Turn off iDMA controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) idma64_off(idma64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) ret = devm_request_irq(chip->dev, chip->irq, idma64_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) dev_name(chip->dev), idma64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) INIT_LIST_HEAD(&idma64->dma.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) for (i = 0; i < nr_chan; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct idma64_chan *idma64c = &idma64->chan[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) idma64c->vchan.desc_free = idma64_vdesc_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) vchan_init(&idma64c->vchan, &idma64->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) idma64c->regs = idma64->regs + i * IDMA64_CH_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) idma64c->mask = BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) dma_cap_set(DMA_SLAVE, idma64->dma.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) dma_cap_set(DMA_PRIVATE, idma64->dma.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) idma64->dma.device_alloc_chan_resources = idma64_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) idma64->dma.device_free_chan_resources = idma64_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) idma64->dma.device_prep_slave_sg = idma64_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) idma64->dma.device_issue_pending = idma64_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) idma64->dma.device_tx_status = idma64_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) idma64->dma.device_config = idma64_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) idma64->dma.device_pause = idma64_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) idma64->dma.device_resume = idma64_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) idma64->dma.device_terminate_all = idma64_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) idma64->dma.device_synchronize = idma64_synchronize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) idma64->dma.src_addr_widths = IDMA64_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) idma64->dma.dst_addr_widths = IDMA64_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) idma64->dma.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) idma64->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) idma64->dma.dev = chip->sysdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dma_set_max_seg_size(idma64->dma.dev, IDMA64C_CTLH_BLOCK_TS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret = dma_async_device_register(&idma64->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) dev_info(chip->dev, "Found Intel integrated DMA 64-bit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) static int idma64_remove(struct idma64_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct idma64 *idma64 = chip->idma64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) unsigned short i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dma_async_device_unregister(&idma64->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) * Explicitly call devm_request_irq() to avoid the side effects with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) * the scheduled tasklets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) devm_free_irq(chip->dev, chip->irq, idma64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) for (i = 0; i < idma64->dma.chancnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct idma64_chan *idma64c = &idma64->chan[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) tasklet_kill(&idma64c->vchan.task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /* ---------------------------------------------------------------------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static int idma64_platform_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct idma64_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct device *sysdev = dev->parent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct resource *mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) chip->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (chip->irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return chip->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) chip->regs = devm_ioremap_resource(dev, mem);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) if (IS_ERR(chip->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) return PTR_ERR(chip->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) ret = dma_coerce_mask_and_coherent(sysdev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) chip->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) chip->sysdev = sysdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = idma64_probe(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) platform_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) static int idma64_platform_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) struct idma64_chip *chip = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return idma64_remove(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static int idma64_pm_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct idma64_chip *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) idma64_off(chip->idma64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) static int idma64_pm_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct idma64_chip *chip = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) idma64_on(chip->idma64);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #endif /* CONFIG_PM_SLEEP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) static const struct dev_pm_ops idma64_dev_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) SET_SYSTEM_SLEEP_PM_OPS(idma64_pm_suspend, idma64_pm_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) static struct platform_driver idma64_platform_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .probe = idma64_platform_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) .remove = idma64_platform_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .name = LPSS_IDMA64_DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .pm = &idma64_dev_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) module_platform_driver(idma64_platform_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) MODULE_DESCRIPTION("iDMA64 core driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) MODULE_AUTHOR("Andy Shevchenko <andriy.shevchenko@linux.intel.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) MODULE_ALIAS("platform:" LPSS_IDMA64_DRIVER_NAME);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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