^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for the High Speed UART DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2015 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Partially based on the bits found in drivers/tty/serial/mfd.c.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __DMA_HSU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __DMA_HSU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dma/hsu.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "../virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define HSU_CH_SR 0x00 /* channel status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define HSU_CH_CR 0x04 /* channel control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HSU_CH_DCR 0x08 /* descriptor control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HSU_CH_BSR 0x10 /* FIFO buffer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HSU_CH_MTSR 0x14 /* minimum transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define HSU_CH_DxSAR(x) (0x20 + 8 * (x)) /* desc start addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HSU_CH_DxTSR(x) (0x24 + 8 * (x)) /* desc transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define HSU_CH_D0SAR 0x20 /* desc 0 start addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HSU_CH_D0TSR 0x24 /* desc 0 transfer size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HSU_CH_D1SAR 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define HSU_CH_D1TSR 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define HSU_CH_D2SAR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define HSU_CH_D2TSR 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HSU_CH_D3SAR 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HSU_CH_D3TSR 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HSU_DMA_CHAN_NR_DESC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HSU_DMA_CHAN_LENGTH 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Bits in HSU_CH_SR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HSU_CH_SR_DESCTO(x) BIT(8 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HSU_CH_SR_DESCTO_ANY (BIT(11) | BIT(10) | BIT(9) | BIT(8))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HSU_CH_SR_CHE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HSU_CH_SR_DESCE(x) BIT(16 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HSU_CH_SR_DESCE_ANY (BIT(19) | BIT(18) | BIT(17) | BIT(16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HSU_CH_SR_CDESC_ANY (BIT(31) | BIT(30))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Bits in HSU_CH_CR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HSU_CH_CR_CHA BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HSU_CH_CR_CHD BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* Bits in HSU_CH_DCR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HSU_CH_DCR_DESCA(x) BIT(0 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HSU_CH_DCR_CHSOD(x) BIT(8 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HSU_CH_DCR_CHSOTO BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HSU_CH_DCR_CHSOE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HSU_CH_DCR_CHDI(x) BIT(16 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HSU_CH_DCR_CHEI BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HSU_CH_DCR_CHTOI(x) BIT(24 + (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Bits in HSU_CH_DxTSR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HSU_CH_DxTSR_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HSU_CH_DxTSR_TSR(x) ((x) & HSU_CH_DxTSR_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct hsu_dma_sg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) struct hsu_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct virt_dma_desc vdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) enum dma_transfer_direction direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct hsu_dma_sg *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) unsigned int nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) size_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) static inline struct hsu_dma_desc *to_hsu_dma_desc(struct virt_dma_desc *vdesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return container_of(vdesc, struct hsu_dma_desc, vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct hsu_dma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct virt_dma_chan vchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) /* hardware configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum dma_transfer_direction direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct dma_slave_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct hsu_dma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static inline struct hsu_dma_chan *to_hsu_dma_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return container_of(chan, struct hsu_dma_chan, vchan.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static inline u32 hsu_chan_readl(struct hsu_dma_chan *hsuc, int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return readl(hsuc->reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) static inline void hsu_chan_writel(struct hsu_dma_chan *hsuc, int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) writel(value, hsuc->reg + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct hsu_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct dma_device dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct hsu_dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned short nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) static inline struct hsu_dma *to_hsu_dma(struct dma_device *ddev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) return container_of(ddev, struct hsu_dma, dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #endif /* __DMA_HSU_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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