Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /* Copyright(c) 2019 HiSilicon Limited. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) #include <linux/bitfield.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #include "virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define HISI_DMA_SQ_BASE_L		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define HISI_DMA_SQ_BASE_H		0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define HISI_DMA_SQ_DEPTH		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define HISI_DMA_SQ_TAIL_PTR		0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define HISI_DMA_CQ_BASE_L		0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define HISI_DMA_CQ_BASE_H		0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define HISI_DMA_CQ_DEPTH		0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define HISI_DMA_CQ_HEAD_PTR		0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define HISI_DMA_CTRL0			0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define HISI_DMA_CTRL0_QUEUE_EN_S	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define HISI_DMA_CTRL0_QUEUE_PAUSE_S	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define HISI_DMA_CTRL1			0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define HISI_DMA_CTRL1_QUEUE_RESET_S	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define HISI_DMA_Q_FSM_STS		0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define HISI_DMA_FSM_STS_MASK		GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define HISI_DMA_INT_STS		0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define HISI_DMA_INT_STS_MASK		GENMASK(12, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define HISI_DMA_INT_MSK		0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define HISI_DMA_MODE			0x217c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define HISI_DMA_OFFSET			0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define HISI_DMA_MSI_NUM		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define HISI_DMA_CHAN_NUM		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define HISI_DMA_Q_DEPTH_VAL		1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define PCI_BAR_2			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) enum hisi_dma_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	EP = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 	RC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) enum hisi_dma_chan_status {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	DISABLE = -1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) 	IDLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 	RUN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) 	CPL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	PAUSE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	HALT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	ABORT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 	WAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	BUFFCLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) struct hisi_dma_sqe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) 	__le32 dw0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define OPCODE_MASK			GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define OPCODE_SMALL_PACKAGE		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define OPCODE_M2M			0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define LOCAL_IRQ_EN			BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define ATTR_SRC_MASK			GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	__le32 dw1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) 	__le32 dw2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define ATTR_DST_MASK			GENMASK(26, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 	__le32 length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) 	__le64 src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	__le64 dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) struct hisi_dma_cqe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	__le32 rsv0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	__le32 rsv1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	__le16 sq_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	__le16 rsv2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	__le16 rsv3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	__le16 w0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define STATUS_MASK			GENMASK(15, 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define STATUS_SUCC			0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define VALID_BIT			BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) struct hisi_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct virt_dma_desc vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 	struct hisi_dma_sqe sqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) struct hisi_dma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) 	struct virt_dma_chan vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 	struct hisi_dma_dev *hdma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 	struct hisi_dma_sqe *sq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) 	struct hisi_dma_cqe *cq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	dma_addr_t sq_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 	dma_addr_t cq_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 	u32 sq_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) 	u32 cq_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) 	u32 qp_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	enum hisi_dma_chan_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) 	struct hisi_dma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct hisi_dma_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 	void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 	struct dma_device dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) 	u32 chan_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) 	u32 chan_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	struct hisi_dma_chan chan[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static inline struct hisi_dma_chan *to_hisi_dma_chan(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return container_of(c, struct hisi_dma_chan, vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static inline struct hisi_dma_desc *to_hisi_dma_desc(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	return container_of(vd, struct hisi_dma_desc, vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) static inline void hisi_dma_chan_write(void __iomem *base, u32 reg, u32 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 				       u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	writel_relaxed(val, base + reg + index * HISI_DMA_OFFSET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static inline void hisi_dma_update_bit(void __iomem *addr, u32 pos, bool val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) 	tmp = readl_relaxed(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 	tmp = val ? tmp | BIT(pos) : tmp & ~BIT(pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 	writel_relaxed(tmp, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static void hisi_dma_free_irq_vectors(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	pci_free_irq_vectors(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) static void hisi_dma_pause_dma(struct hisi_dma_dev *hdma_dev, u32 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 			       bool pause)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL0 + index *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 			     HISI_DMA_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	hisi_dma_update_bit(addr, HISI_DMA_CTRL0_QUEUE_PAUSE_S, pause);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void hisi_dma_enable_dma(struct hisi_dma_dev *hdma_dev, u32 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 				bool enable)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL0 + index *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 			     HISI_DMA_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	hisi_dma_update_bit(addr, HISI_DMA_CTRL0_QUEUE_EN_S, enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) static void hisi_dma_mask_irq(struct hisi_dma_dev *hdma_dev, u32 qp_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	hisi_dma_chan_write(hdma_dev->base, HISI_DMA_INT_MSK, qp_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 			    HISI_DMA_INT_STS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) static void hisi_dma_unmask_irq(struct hisi_dma_dev *hdma_dev, u32 qp_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 	void __iomem *base = hdma_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) 	hisi_dma_chan_write(base, HISI_DMA_INT_STS, qp_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 			    HISI_DMA_INT_STS_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 	hisi_dma_chan_write(base, HISI_DMA_INT_MSK, qp_index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) static void hisi_dma_do_reset(struct hisi_dma_dev *hdma_dev, u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 	void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL1 + index *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 			     HISI_DMA_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 	hisi_dma_update_bit(addr, HISI_DMA_CTRL1_QUEUE_RESET_S, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static void hisi_dma_reset_qp_point(struct hisi_dma_dev *hdma_dev, u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	hisi_dma_chan_write(hdma_dev->base, HISI_DMA_SQ_TAIL_PTR, index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	hisi_dma_chan_write(hdma_dev->base, HISI_DMA_CQ_HEAD_PTR, index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static void hisi_dma_reset_hw_chan(struct hisi_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	u32 index = chan->qp_num, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) 	hisi_dma_pause_dma(hdma_dev, index, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) 	hisi_dma_enable_dma(hdma_dev, index, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 	hisi_dma_mask_irq(hdma_dev, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	ret = readl_relaxed_poll_timeout(hdma_dev->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 		HISI_DMA_Q_FSM_STS + index * HISI_DMA_OFFSET, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 		FIELD_GET(HISI_DMA_FSM_STS_MASK, tmp) != RUN, 10, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 		dev_err(&hdma_dev->pdev->dev, "disable channel timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 		WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	hisi_dma_do_reset(hdma_dev, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	hisi_dma_reset_qp_point(hdma_dev, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	hisi_dma_pause_dma(hdma_dev, index, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	hisi_dma_enable_dma(hdma_dev, index, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	hisi_dma_unmask_irq(hdma_dev, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	ret = readl_relaxed_poll_timeout(hdma_dev->base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 		HISI_DMA_Q_FSM_STS + index * HISI_DMA_OFFSET, tmp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 		FIELD_GET(HISI_DMA_FSM_STS_MASK, tmp) == IDLE, 10, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 		dev_err(&hdma_dev->pdev->dev, "reset channel timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 		WARN_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void hisi_dma_free_chan_resources(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 	struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 	hisi_dma_reset_hw_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) 	vchan_free_chan_resources(&chan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) 	memset(chan->sq, 0, sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 	memset(chan->cq, 0, sizeof(struct hisi_dma_cqe) * hdma_dev->chan_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 	chan->sq_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	chan->cq_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	chan->status = DISABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) static void hisi_dma_desc_free(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) 	kfree(to_hisi_dma_desc(vd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) hisi_dma_prep_dma_memcpy(struct dma_chan *c, dma_addr_t dst, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 			 size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	struct hisi_dma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 	desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 		return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	desc->sqe.length = cpu_to_le32(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) 	desc->sqe.src_addr = cpu_to_le64(src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	desc->sqe.dst_addr = cpu_to_le64(dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	return vchan_tx_prep(&chan->vc, &desc->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) static enum dma_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) hisi_dma_tx_status(struct dma_chan *c, dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 		   struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) 	return dma_cookie_status(c, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) static void hisi_dma_start_transfer(struct hisi_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	struct hisi_dma_sqe *sqe = chan->sq + chan->sq_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct hisi_dma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct virt_dma_desc *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	vd = vchan_next_desc(&chan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	if (!vd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 		dev_err(&hdma_dev->pdev->dev, "no issued task!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 		chan->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 		return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	list_del(&vd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 	desc = to_hisi_dma_desc(vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	chan->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	memcpy(sqe, &desc->sqe, sizeof(struct hisi_dma_sqe));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 	/* update other field in sqe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	sqe->dw0 = cpu_to_le32(FIELD_PREP(OPCODE_MASK, OPCODE_M2M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	sqe->dw0 |= cpu_to_le32(LOCAL_IRQ_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	/* make sure data has been updated in sqe */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) 	wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) 	/* update sq tail, point to new sqe position */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	chan->sq_tail = (chan->sq_tail + 1) % hdma_dev->chan_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	/* update sq_tail to trigger a new task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	hisi_dma_chan_write(hdma_dev->base, HISI_DMA_SQ_TAIL_PTR, chan->qp_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 			    chan->sq_tail);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static void hisi_dma_issue_pending(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	spin_lock_irqsave(&chan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	if (vchan_issue_pending(&chan->vc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 		hisi_dma_start_transfer(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	spin_unlock_irqrestore(&chan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) static int hisi_dma_terminate_all(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	spin_lock_irqsave(&chan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 	hisi_dma_pause_dma(chan->hdma_dev, chan->qp_num, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 	if (chan->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 		vchan_terminate_vdesc(&chan->desc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 		chan->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	vchan_get_all_descriptors(&chan->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	spin_unlock_irqrestore(&chan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	vchan_dma_desc_free_list(&chan->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) 	hisi_dma_pause_dma(chan->hdma_dev, chan->qp_num, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) static void hisi_dma_synchronize(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 	struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) 	vchan_synchronize(&chan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) static int hisi_dma_alloc_qps_mem(struct hisi_dma_dev *hdma_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) 	size_t sq_size = sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) 	size_t cq_size = sizeof(struct hisi_dma_cqe) * hdma_dev->chan_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 	struct device *dev = &hdma_dev->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) 	struct hisi_dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 	for (i = 0; i < hdma_dev->chan_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) 		chan = &hdma_dev->chan[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) 		chan->sq = dmam_alloc_coherent(dev, sq_size, &chan->sq_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) 					       GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) 		if (!chan->sq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) 		chan->cq = dmam_alloc_coherent(dev, cq_size, &chan->cq_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) 					       GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 		if (!chan->cq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) 			return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void hisi_dma_init_hw_qp(struct hisi_dma_dev *hdma_dev, u32 index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) 	struct hisi_dma_chan *chan = &hdma_dev->chan[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) 	u32 hw_depth = hdma_dev->chan_depth - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 	void __iomem *base = hdma_dev->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) 	/* set sq, cq base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) 	hisi_dma_chan_write(base, HISI_DMA_SQ_BASE_L, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) 			    lower_32_bits(chan->sq_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) 	hisi_dma_chan_write(base, HISI_DMA_SQ_BASE_H, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) 			    upper_32_bits(chan->sq_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) 	hisi_dma_chan_write(base, HISI_DMA_CQ_BASE_L, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) 			    lower_32_bits(chan->cq_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) 	hisi_dma_chan_write(base, HISI_DMA_CQ_BASE_H, index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) 			    upper_32_bits(chan->cq_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 	/* set sq, cq depth */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 	hisi_dma_chan_write(base, HISI_DMA_SQ_DEPTH, index, hw_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) 	hisi_dma_chan_write(base, HISI_DMA_CQ_DEPTH, index, hw_depth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) 	/* init sq tail and cq head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) 	hisi_dma_chan_write(base, HISI_DMA_SQ_TAIL_PTR, index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) 	hisi_dma_chan_write(base, HISI_DMA_CQ_HEAD_PTR, index, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static void hisi_dma_enable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) 	hisi_dma_init_hw_qp(hdma_dev, qp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) 	hisi_dma_unmask_irq(hdma_dev, qp_index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) 	hisi_dma_enable_dma(hdma_dev, qp_index, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) static void hisi_dma_disable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 	hisi_dma_reset_hw_chan(&hdma_dev->chan[qp_index]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static void hisi_dma_enable_qps(struct hisi_dma_dev *hdma_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) 	for (i = 0; i < hdma_dev->chan_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) 		hdma_dev->chan[i].qp_num = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 		hdma_dev->chan[i].hdma_dev = hdma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) 		hdma_dev->chan[i].vc.desc_free = hisi_dma_desc_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 		vchan_init(&hdma_dev->chan[i].vc, &hdma_dev->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) 		hisi_dma_enable_qp(hdma_dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) static void hisi_dma_disable_qps(struct hisi_dma_dev *hdma_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) 	int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 	for (i = 0; i < hdma_dev->chan_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) 		hisi_dma_disable_qp(hdma_dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) 		tasklet_kill(&hdma_dev->chan[i].vc.task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) static irqreturn_t hisi_dma_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) 	struct hisi_dma_chan *chan = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) 	struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) 	struct hisi_dma_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) 	struct hisi_dma_cqe *cqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) 	unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) 	spin_lock_irqsave(&chan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) 	desc = chan->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) 	cqe = chan->cq + chan->cq_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) 	if (desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) 		if (FIELD_GET(STATUS_MASK, cqe->w0) == STATUS_SUCC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) 			chan->cq_head = (chan->cq_head + 1) %
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) 					hdma_dev->chan_depth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) 			hisi_dma_chan_write(hdma_dev->base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) 					    HISI_DMA_CQ_HEAD_PTR, chan->qp_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) 					    chan->cq_head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) 			vchan_cookie_complete(&desc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) 		} else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) 			dev_err(&hdma_dev->pdev->dev, "task error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) 		}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) 		chan->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) 	spin_unlock_irqrestore(&chan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) 	return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) static int hisi_dma_request_qps_irq(struct hisi_dma_dev *hdma_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) 	struct pci_dev *pdev = hdma_dev->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) 	int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) 	for (i = 0; i < hdma_dev->chan_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) 		ret = devm_request_irq(&pdev->dev, pci_irq_vector(pdev, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) 				       hisi_dma_irq, IRQF_SHARED, "hisi_dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) 				       &hdma_dev->chan[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) 		if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) 			return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) /* This function enables all hw channels in a device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) static int hisi_dma_enable_hw_channels(struct hisi_dma_dev *hdma_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) 	ret = hisi_dma_alloc_qps_mem(hdma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) 		dev_err(&hdma_dev->pdev->dev, "fail to allocate qp memory!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) 	ret = hisi_dma_request_qps_irq(hdma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) 		dev_err(&hdma_dev->pdev->dev, "fail to request qp irq!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) 	hisi_dma_enable_qps(hdma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) 	return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static void hisi_dma_disable_hw_channels(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) 	hisi_dma_disable_qps(data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) static void hisi_dma_set_mode(struct hisi_dma_dev *hdma_dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) 			      enum hisi_dma_mode mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) 	writel_relaxed(mode == RC ? 1 : 0, hdma_dev->base + HISI_DMA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) static int hisi_dma_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) 	struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) 	struct hisi_dma_dev *hdma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) 	struct dma_device *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) 	int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) 	ret = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) 		dev_err(dev, "failed to enable device mem!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) 	ret = pcim_iomap_regions(pdev, 1 << PCI_BAR_2, pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) 	if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) 		dev_err(dev, "failed to remap I/O region!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) 	ret = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) 	ret = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) 	hdma_dev = devm_kzalloc(dev, struct_size(hdma_dev, chan, HISI_DMA_CHAN_NUM), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) 	if (!hdma_dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) 		return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) 	hdma_dev->base = pcim_iomap_table(pdev)[PCI_BAR_2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) 	hdma_dev->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) 	hdma_dev->chan_num = HISI_DMA_CHAN_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) 	hdma_dev->chan_depth = HISI_DMA_Q_DEPTH_VAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) 	pci_set_drvdata(pdev, hdma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) 	pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) 	ret = pci_alloc_irq_vectors(pdev, HISI_DMA_MSI_NUM, HISI_DMA_MSI_NUM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) 				    PCI_IRQ_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) 		dev_err(dev, "Failed to allocate MSI vectors!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) 	ret = devm_add_action_or_reset(dev, hisi_dma_free_irq_vectors, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) 	dma_dev = &hdma_dev->dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) 	dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) 	dma_dev->device_free_chan_resources = hisi_dma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) 	dma_dev->device_prep_dma_memcpy = hisi_dma_prep_dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) 	dma_dev->device_tx_status = hisi_dma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) 	dma_dev->device_issue_pending = hisi_dma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) 	dma_dev->device_terminate_all = hisi_dma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) 	dma_dev->device_synchronize = hisi_dma_synchronize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) 	dma_dev->directions = BIT(DMA_MEM_TO_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) 	dma_dev->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) 	INIT_LIST_HEAD(&dma_dev->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) 	hisi_dma_set_mode(hdma_dev, RC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) 	ret = hisi_dma_enable_hw_channels(hdma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) 	if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) 		dev_err(dev, "failed to enable hw channel!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) 	}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) 	ret = devm_add_action_or_reset(dev, hisi_dma_disable_hw_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) 				       hdma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) 	if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) 		return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) 	ret = dmaenginem_async_device_register(dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) 	if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) 		dev_err(dev, "failed to register device!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) 	return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) static const struct pci_device_id hisi_dma_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) 	{ PCI_DEVICE(PCI_VENDOR_ID_HUAWEI, 0xa122) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) 	{ 0, }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) static struct pci_driver hisi_dma_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) 	.name		= "hisi_dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) 	.id_table	= hisi_dma_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) 	.probe		= hisi_dma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) module_pci_driver(hisi_dma_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) MODULE_AUTHOR("Zhenfa Qiu <qiuzhenfa@hisilicon.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) MODULE_DESCRIPTION("HiSilicon Kunpeng DMA controller driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) MODULE_DEVICE_TABLE(pci, hisi_dma_pci_tbl);