Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * drivers/dma/fsl_raid.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Freescale RAID Engine device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  *	Harninder Rai <harninder.rai@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *	Naveen Burmi <naveenburmi@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * Rewrite:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *	Xuelin Shi <xuelin.shi@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * Copyright (c) 2010-2012 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  * modification, are permitted provided that the following conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *     * Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *       notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  *     * Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *       notice, this list of conditions and the following disclaimer in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *       documentation and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *     * Neither the name of Freescale Semiconductor nor the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *       names of its contributors may be used to endorse or promote products
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *       derived from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  * ALTERNATIVELY, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  * GNU General Public License ("GPL") as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  * Foundation, either version 2 of that License or (at your option) any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  * later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define FSL_RE_MAX_CHANS		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define FSL_RE_DPAA_MODE		BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define FSL_RE_NON_DPAA_MODE		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define FSL_RE_GFM_POLY			0x1d000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define FSL_RE_ADD_JOB(x)		((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define FSL_RE_RMVD_JOB(x)		((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define FSL_RE_CFG1_CBSI		0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define FSL_RE_CFG1_CBS0		0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define FSL_RE_SLOT_FULL_SHIFT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define FSL_RE_SLOT_FULL(x)		((x) >> FSL_RE_SLOT_FULL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define FSL_RE_SLOT_AVAIL_SHIFT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define FSL_RE_SLOT_AVAIL(x)		((x) >> FSL_RE_SLOT_AVAIL_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define FSL_RE_PQ_OPCODE		0x1B
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define FSL_RE_XOR_OPCODE		0x1A
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define FSL_RE_MOVE_OPCODE		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define FSL_RE_FRAME_ALIGN		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define FSL_RE_BLOCK_SIZE		0x3 /* 4096 bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define FSL_RE_CACHEABLE_IO		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define FSL_RE_BUFFER_OUTPUT		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define FSL_RE_INTR_ON_ERROR		0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define FSL_RE_DATA_DEP			0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define FSL_RE_ENABLE_DPI		0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define FSL_RE_RING_SIZE		0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define FSL_RE_RING_SIZE_MASK		(FSL_RE_RING_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define FSL_RE_RING_SIZE_SHIFT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define FSL_RE_ADDR_BIT_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define FSL_RE_ADDR_BIT_MASK		(BIT(FSL_RE_ADDR_BIT_SHIFT) - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define FSL_RE_ERROR			0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define FSL_RE_INTR			0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define FSL_RE_CLR_INTR			0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define FSL_RE_PAUSE			0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define FSL_RE_ENABLE			0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define FSL_RE_REG_LIODN_MASK		0x00000FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define FSL_RE_CDB_OPCODE_MASK		0xF8000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define FSL_RE_CDB_OPCODE_SHIFT		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define FSL_RE_CDB_EXCLEN_MASK		0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define FSL_RE_CDB_EXCLEN_SHIFT		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define FSL_RE_CDB_EXCLQ1_MASK		0x00F00000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define FSL_RE_CDB_EXCLQ1_SHIFT		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define FSL_RE_CDB_EXCLQ2_MASK		0x000F0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define FSL_RE_CDB_EXCLQ2_SHIFT		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define FSL_RE_CDB_BLKSIZE_MASK		0x0000C000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define FSL_RE_CDB_BLKSIZE_SHIFT	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define FSL_RE_CDB_CACHE_MASK		0x00003000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define FSL_RE_CDB_CACHE_SHIFT		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define FSL_RE_CDB_BUFFER_MASK		0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define FSL_RE_CDB_BUFFER_SHIFT		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define FSL_RE_CDB_ERROR_MASK		0x00000400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define FSL_RE_CDB_ERROR_SHIFT		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define FSL_RE_CDB_NRCS_MASK		0x0000003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define FSL_RE_CDB_NRCS_SHIFT		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define FSL_RE_CDB_DEPEND_MASK		0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define FSL_RE_CDB_DEPEND_SHIFT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define FSL_RE_CDB_DPI_MASK		0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define FSL_RE_CDB_DPI_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)  * the largest cf block is 19*sizeof(struct cmpnd_frame), which is 304 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)  * here 19 = 1(cdb)+2(dest)+16(src), align to 64bytes, that is 320 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)  * the largest cdb block: struct pq_cdb which is 180 bytes, adding to cf block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)  * 320+180=500, align to 64bytes, that is 512 bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define FSL_RE_CF_DESC_SIZE		320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define FSL_RE_CF_CDB_SIZE		512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define FSL_RE_CF_CDB_ALIGN		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct fsl_re_ctrl {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 	/* General Configuration Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	__be32 global_config;	/* Global Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) 	u8     rsvd1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 	__be32 galois_field_config; /* Galois Field Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 	u8     rsvd2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 	__be32 jq_wrr_config;   /* WRR Configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 	u8     rsvd3[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 	__be32 crc_config;	/* CRC Configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) 	u8     rsvd4[228];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 	__be32 system_reset;	/* System Reset Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) 	u8     rsvd5[252];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) 	__be32 global_status;	/* Global Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) 	u8     rsvd6[832];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) 	__be32 re_liodn_base;	/* LIODN Base Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) 	u8     rsvd7[1712];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 	__be32 re_version_id;	/* Version ID register of RE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) 	__be32 re_version_id_2; /* Version ID 2 register of RE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) 	u8     rsvd8[512];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 	__be32 host_config;	/* Host I/F Configuration Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct fsl_re_chan_cfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) 	/* Registers for JR interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) 	__be32 jr_config_0;	/* Job Queue Configuration 0 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) 	__be32 jr_config_1;	/* Job Queue Configuration 1 Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 	__be32 jr_interrupt_status; /* Job Queue Interrupt Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 	u8     rsvd1[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) 	__be32 jr_command;	/* Job Queue Command Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) 	u8     rsvd2[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) 	__be32 jr_status;	/* Job Queue Status Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 	u8     rsvd3[228];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) 	/* Input Ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) 	__be32 inbring_base_h;	/* Inbound Ring Base Address Register - High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 	__be32 inbring_base_l;	/* Inbound Ring Base Address Register - Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 	__be32 inbring_size;	/* Inbound Ring Size Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) 	u8     rsvd4[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) 	__be32 inbring_slot_avail; /* Inbound Ring Slot Available Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) 	u8     rsvd5[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 	__be32 inbring_add_job;	/* Inbound Ring Add Job Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) 	u8     rsvd6[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) 	__be32 inbring_cnsmr_indx; /* Inbound Ring Consumer Index Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) 	u8     rsvd7[220];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) 	/* Output Ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) 	__be32 oubring_base_h;	/* Outbound Ring Base Address Register - High */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 	__be32 oubring_base_l;	/* Outbound Ring Base Address Register - Low */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 	__be32 oubring_size;	/* Outbound Ring Size Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 	u8     rsvd8[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) 	__be32 oubring_job_rmvd; /* Outbound Ring Job Removed Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 	u8     rsvd9[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 	__be32 oubring_slot_full; /* Outbound Ring Slot Full Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 	u8     rsvd10[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 	__be32 oubring_prdcr_indx; /* Outbound Ring Producer Index */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)  * Command Descriptor Block (CDB) for unicast move command.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)  * In RAID Engine terms, memcpy is done through move command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) struct fsl_re_move_cdb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 	__be32 cdb32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Data protection/integrity related fields */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define FSL_RE_DPI_APPS_MASK		0xC0000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define FSL_RE_DPI_APPS_SHIFT		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define FSL_RE_DPI_REF_MASK		0x30000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define FSL_RE_DPI_REF_SHIFT		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define FSL_RE_DPI_GUARD_MASK		0x0C000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define FSL_RE_DPI_GUARD_SHIFT		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define FSL_RE_DPI_ATTR_MASK		0x03000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define FSL_RE_DPI_ATTR_SHIFT		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define FSL_RE_DPI_META_MASK		0x0000FFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) struct fsl_re_dpi {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	__be32 dpi32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	__be32 ref;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)  * CDB for GenQ command. In RAID Engine terminology, XOR is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)  * done through this command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct fsl_re_xor_cdb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) 	__be32 cdb32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 	u8 gfm[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 	struct fsl_re_dpi dpi_dest_spec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) 	struct fsl_re_dpi dpi_src_spec[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* CDB for no-op command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) struct fsl_re_noop_cdb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	__be32 cdb32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)  * CDB for GenQQ command. In RAID Engine terminology, P/Q is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)  * done through this command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct fsl_re_pq_cdb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	__be32 cdb32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 	u8 gfm_q1[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 	u8 gfm_q2[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) 	struct fsl_re_dpi dpi_dest_spec[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) 	struct fsl_re_dpi dpi_src_spec[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* Compound frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define FSL_RE_CF_ADDR_HIGH_MASK	0x000000FF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define FSL_RE_CF_EXT_MASK		0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define FSL_RE_CF_EXT_SHIFT		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define FSL_RE_CF_FINAL_MASK		0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define FSL_RE_CF_FINAL_SHIFT		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define FSL_RE_CF_LENGTH_MASK		0x000FFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define FSL_RE_CF_BPID_MASK		0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define FSL_RE_CF_BPID_SHIFT		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define FSL_RE_CF_OFFSET_MASK		0x00001FFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct fsl_re_cmpnd_frame {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) 	__be32 addr_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) 	__be32 addr_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	__be32 efrl32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	__be32 rbro32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /* Frame descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define FSL_RE_HWDESC_LIODN_MASK	0x3F000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define FSL_RE_HWDESC_LIODN_SHIFT	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define FSL_RE_HWDESC_BPID_MASK		0x00FF0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define FSL_RE_HWDESC_BPID_SHIFT	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define FSL_RE_HWDESC_ELIODN_MASK	0x0000F000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define FSL_RE_HWDESC_ELIODN_SHIFT	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define FSL_RE_HWDESC_FMT_SHIFT		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define FSL_RE_HWDESC_FMT_MASK		(0x3 << FSL_RE_HWDESC_FMT_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct fsl_re_hw_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 	__be32 lbea32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 	__be32 addr_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 	__be32 fmt32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 	__be32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Raid Engine device private data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct fsl_re_drv_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	u8 total_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 	struct dma_device dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 	struct fsl_re_ctrl *re_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) 	struct fsl_re_chan *re_jrs[FSL_RE_MAX_CHANS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 	struct dma_pool *cf_desc_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 	struct dma_pool *hw_desc_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* Per job ring data structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct fsl_re_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) 	char name[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) 	spinlock_t desc_lock; /* queue lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 	struct list_head ack_q;  /* wait to acked queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 	struct list_head active_q; /* already issued on hw, not completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) 	struct list_head submit_q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) 	struct list_head free_q; /* alloc available queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) 	struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 	struct fsl_re_drv_private *re_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 	struct dma_chan chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 	struct fsl_re_chan_cfg *jrregs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) 	int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) 	struct tasklet_struct irqtask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 	u32 alloc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) 	/* hw descriptor ring for inbound queue*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) 	dma_addr_t inb_phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) 	struct fsl_re_hw_desc *inb_ring_virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 	u32 inb_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 	/* hw descriptor ring for outbound queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 	dma_addr_t oub_phys_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) 	struct fsl_re_hw_desc *oub_ring_virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) 	u32 oub_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Async transaction descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) struct fsl_re_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	struct dma_async_tx_descriptor async_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	struct fsl_re_hw_desc hwdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	struct fsl_re_chan *re_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	/* hwdesc will point to cf_addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	void *cf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	dma_addr_t cf_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	void *cdb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	dma_addr_t cdb_paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	int status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) };