^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * drivers/dma/fsl_raid.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Freescale RAID Engine device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Harninder Rai <harninder.rai@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Naveen Burmi <naveenburmi@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Rewrite:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Xuelin Shi <xuelin.shi@freescale.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * Copyright (c) 2010-2014 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Redistribution and use in source and binary forms, with or without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * modification, are permitted provided that the following conditions are met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * * Redistributions of source code must retain the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * notice, this list of conditions and the following disclaimer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * * Redistributions in binary form must reproduce the above copyright
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * notice, this list of conditions and the following disclaimer in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * documentation and/or other materials provided with the distribution.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * * Neither the name of Freescale Semiconductor nor the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * names of its contributors may be used to endorse or promote products
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * derived from this software without specific prior written permission.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * ALTERNATIVELY, this software may be distributed under the terms of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * GNU General Public License ("GPL") as published by the Free Software
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * Foundation, either version 2 of that License or (at your option) any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * THIS SOFTWARE IS PROVIDED BY Freescale Semiconductor ``AS IS'' AND ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * DISCLAIMED. IN NO EVENT SHALL Freescale Semiconductor BE LIABLE FOR ANY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Theory of operation:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * General capabilities:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * RAID Engine (RE) block is capable of offloading XOR, memcpy and P/Q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * calculations required in RAID5 and RAID6 operations. RE driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * registers with Linux's ASYNC layer as dma driver. RE hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * maintains strict ordering of the requests through chained
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * command queueing.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * Data flow:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * Software RAID layer of Linux (MD layer) maintains RAID partitions,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * strips, stripes etc. It sends requests to the underlying ASYNC layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * which further passes it to RE driver. ASYNC layer decides which request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * goes to which job ring of RE hardware. For every request processed by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * RAID Engine, driver gets an interrupt unless coalescing is set. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * per job ring interrupt handler checks the status register for errors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * clears the interrupt and leave the post interrupt processing to the irq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * thread.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include "dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include "fsl_raid.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FSL_RE_MAX_XOR_SRCS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FSL_RE_MAX_PQ_SRCS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FSL_RE_MIN_DESCS 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define FSL_RE_MAX_DESCS (4 * FSL_RE_MIN_DESCS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define FSL_RE_FRAME_FORMAT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define FSL_RE_MAX_DATA_LEN (1024*1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define to_fsl_re_dma_desc(tx) container_of(tx, struct fsl_re_desc, async_tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Add descriptors into per chan software queue - submit_q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) static dma_cookie_t fsl_re_tx_submit(struct dma_async_tx_descriptor *tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct fsl_re_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct fsl_re_chan *re_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) desc = to_fsl_re_dma_desc(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) re_chan = container_of(tx->chan, struct fsl_re_chan, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) spin_lock_irqsave(&re_chan->desc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) cookie = dma_cookie_assign(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) list_add_tail(&desc->node, &re_chan->submit_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) spin_unlock_irqrestore(&re_chan->desc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) return cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Copy descriptor from per chan software queue into hardware job ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) static void fsl_re_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct fsl_re_chan *re_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) int avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct fsl_re_desc *desc, *_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) re_chan = container_of(chan, struct fsl_re_chan, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) spin_lock_irqsave(&re_chan->desc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) avail = FSL_RE_SLOT_AVAIL(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) in_be32(&re_chan->jrregs->inbring_slot_avail));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) list_for_each_entry_safe(desc, _desc, &re_chan->submit_q, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if (!avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) list_move_tail(&desc->node, &re_chan->active_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) memcpy(&re_chan->inb_ring_virt_addr[re_chan->inb_count],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) &desc->hwdesc, sizeof(struct fsl_re_hw_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) re_chan->inb_count = (re_chan->inb_count + 1) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) FSL_RE_RING_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) out_be32(&re_chan->jrregs->inbring_add_job, FSL_RE_ADD_JOB(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) avail--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) spin_unlock_irqrestore(&re_chan->desc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) static void fsl_re_desc_done(struct fsl_re_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dma_cookie_complete(&desc->async_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dma_descriptor_unmap(&desc->async_tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dmaengine_desc_get_callback_invoke(&desc->async_tx, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) static void fsl_re_cleanup_descs(struct fsl_re_chan *re_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct fsl_re_desc *desc, *_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) spin_lock_irqsave(&re_chan->desc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) list_for_each_entry_safe(desc, _desc, &re_chan->ack_q, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (async_tx_test_ack(&desc->async_tx))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) list_move_tail(&desc->node, &re_chan->free_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) spin_unlock_irqrestore(&re_chan->desc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) fsl_re_issue_pending(&re_chan->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) static void fsl_re_dequeue(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct fsl_re_chan *re_chan = from_tasklet(re_chan, t, irqtask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct fsl_re_desc *desc, *_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct fsl_re_hw_desc *hwdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) unsigned int count, oub_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int found;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) fsl_re_cleanup_descs(re_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) spin_lock_irqsave(&re_chan->desc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) count = FSL_RE_SLOT_FULL(in_be32(&re_chan->jrregs->oubring_slot_full));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) while (count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) found = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) hwdesc = &re_chan->oub_ring_virt_addr[re_chan->oub_count];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) list_for_each_entry_safe(desc, _desc, &re_chan->active_q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* compare the hw dma addr to find the completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) if (desc->hwdesc.lbea32 == hwdesc->lbea32 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) desc->hwdesc.addr_low == hwdesc->addr_low) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) found = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) if (found) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) fsl_re_desc_done(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) list_move_tail(&desc->node, &re_chan->ack_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_err(re_chan->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "found hwdesc not in sw queue, discard it\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) oub_count = (re_chan->oub_count + 1) & FSL_RE_RING_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) re_chan->oub_count = oub_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) out_be32(&re_chan->jrregs->oubring_job_rmvd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) FSL_RE_RMVD_JOB(1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) spin_unlock_irqrestore(&re_chan->desc_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* Per Job Ring interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) static irqreturn_t fsl_re_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct fsl_re_chan *re_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 irqstate, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) re_chan = dev_get_drvdata((struct device *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) irqstate = in_be32(&re_chan->jrregs->jr_interrupt_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) if (!irqstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * There's no way in upper layer (read MD layer) to recover from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * error conditions except restart everything. In long term we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * need to do something more than just crashing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (irqstate & FSL_RE_ERROR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) status = in_be32(&re_chan->jrregs->jr_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dev_err(re_chan->dev, "chan error irqstate: %x, status: %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) irqstate, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* Clear interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) out_be32(&re_chan->jrregs->jr_interrupt_status, FSL_RE_CLR_INTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tasklet_schedule(&re_chan->irqtask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) static enum dma_status fsl_re_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) return dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) static void fill_cfd_frame(struct fsl_re_cmpnd_frame *cf, u8 index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) size_t length, dma_addr_t addr, bool final)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 efrl = length & FSL_RE_CF_LENGTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) efrl |= final << FSL_RE_CF_FINAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) cf[index].efrl32 = efrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) cf[index].addr_high = upper_32_bits(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) cf[index].addr_low = lower_32_bits(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static struct fsl_re_desc *fsl_re_init_desc(struct fsl_re_chan *re_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) struct fsl_re_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) void *cf, dma_addr_t paddr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) desc->re_chan = re_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) desc->async_tx.tx_submit = fsl_re_tx_submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) dma_async_tx_descriptor_init(&desc->async_tx, &re_chan->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) INIT_LIST_HEAD(&desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) desc->hwdesc.fmt32 = FSL_RE_FRAME_FORMAT << FSL_RE_HWDESC_FMT_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) desc->hwdesc.lbea32 = upper_32_bits(paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) desc->hwdesc.addr_low = lower_32_bits(paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) desc->cf_addr = cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) desc->cf_paddr = paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) desc->cdb_addr = (void *)(cf + FSL_RE_CF_DESC_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) desc->cdb_paddr = paddr + FSL_RE_CF_DESC_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) static struct fsl_re_desc *fsl_re_chan_alloc_desc(struct fsl_re_chan *re_chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct fsl_re_desc *desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) void *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dma_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned long lock_flag;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) fsl_re_cleanup_descs(re_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) spin_lock_irqsave(&re_chan->desc_lock, lock_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) if (!list_empty(&re_chan->free_q)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* take one desc from free_q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) desc = list_first_entry(&re_chan->free_q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) struct fsl_re_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) list_del(&desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) desc->async_tx.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) spin_unlock_irqrestore(&re_chan->desc_lock, lock_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) if (!desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) desc = kzalloc(sizeof(*desc), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) cf = dma_pool_alloc(re_chan->re_dev->cf_desc_pool, GFP_NOWAIT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) &paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) if (!cf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) desc = fsl_re_init_desc(re_chan, desc, cf, paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) desc->async_tx.flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) spin_lock_irqsave(&re_chan->desc_lock, lock_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) re_chan->alloc_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) spin_unlock_irqrestore(&re_chan->desc_lock, lock_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) static struct dma_async_tx_descriptor *fsl_re_prep_dma_genq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) unsigned int src_cnt, const unsigned char *scf, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct fsl_re_chan *re_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct fsl_re_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) struct fsl_re_xor_cdb *xor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) struct fsl_re_cmpnd_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u32 cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) unsigned int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) unsigned int save_src_cnt = src_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) int cont_q = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) re_chan = container_of(chan, struct fsl_re_chan, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (len > FSL_RE_MAX_DATA_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_err(re_chan->dev, "genq tx length %zu, max length %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) len, FSL_RE_MAX_DATA_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) desc = fsl_re_chan_alloc_desc(re_chan, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) if (desc <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) if (scf && (flags & DMA_PREP_CONTINUE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) cont_q = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) src_cnt += 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* Filling xor CDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) cdb = FSL_RE_XOR_OPCODE << FSL_RE_CDB_OPCODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) cdb |= (src_cnt - 1) << FSL_RE_CDB_NRCS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) cdb |= FSL_RE_BLOCK_SIZE << FSL_RE_CDB_BLKSIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) cdb |= FSL_RE_INTR_ON_ERROR << FSL_RE_CDB_ERROR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cdb |= FSL_RE_DATA_DEP << FSL_RE_CDB_DEPEND_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) xor = desc->cdb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) xor->cdb32 = cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (scf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) /* compute q = src0*coef0^src1*coef1^..., * is GF(8) mult */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) for (i = 0; i < save_src_cnt; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) xor->gfm[i] = scf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (cont_q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) xor->gfm[i++] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* compute P, that is XOR all srcs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) for (i = 0; i < src_cnt; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) xor->gfm[i] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Filling frame 0 of compound frame descriptor with CDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) cf = desc->cf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) fill_cfd_frame(cf, 0, sizeof(*xor), desc->cdb_paddr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* Fill CFD's 1st frame with dest buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) fill_cfd_frame(cf, 1, len, dest, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* Fill CFD's rest of the frames with source buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) for (i = 2, j = 0; j < save_src_cnt; i++, j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) fill_cfd_frame(cf, i, len, src[j], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (cont_q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) fill_cfd_frame(cf, i++, len, dest, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* Setting the final bit in the last source buffer frame in CFD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) cf[i - 1].efrl32 |= 1 << FSL_RE_CF_FINAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) return &desc->async_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * Prep function for P parity calculation.In RAID Engine terminology,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * XOR calculation is called GenQ calculation done through GenQ command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) static struct dma_async_tx_descriptor *fsl_re_prep_dma_xor(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct dma_chan *chan, dma_addr_t dest, dma_addr_t *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int src_cnt, size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* NULL let genq take all coef as 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return fsl_re_prep_dma_genq(chan, dest, src, src_cnt, NULL, len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) * Prep function for P/Q parity calculation.In RAID Engine terminology,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) * P/Q calculation is called GenQQ done through GenQQ command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) static struct dma_async_tx_descriptor *fsl_re_prep_dma_pq(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct dma_chan *chan, dma_addr_t *dest, dma_addr_t *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned int src_cnt, const unsigned char *scf, size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) struct fsl_re_chan *re_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct fsl_re_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct fsl_re_pq_cdb *pq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct fsl_re_cmpnd_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) u32 cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u8 *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) int gfmq_len, i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned int save_src_cnt = src_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) re_chan = container_of(chan, struct fsl_re_chan, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (len > FSL_RE_MAX_DATA_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_err(re_chan->dev, "pq tx length is %zu, max length is %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) len, FSL_RE_MAX_DATA_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) * RE requires at least 2 sources, if given only one source, we pass the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) * second source same as the first one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) * With only one source, generating P is meaningless, only generate Q.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (src_cnt == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dma_addr_t dma_src[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned char coef[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dma_src[0] = *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) coef[0] = *scf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dma_src[1] = *src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) coef[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) tx = fsl_re_prep_dma_genq(chan, dest[1], dma_src, 2, coef, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) desc = to_fsl_re_dma_desc(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) * During RAID6 array creation, Linux's MD layer gets P and Q
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * calculated separately in two steps. But our RAID Engine has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) * the capability to calculate both P and Q with a single command
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) * Hence to merge well with MD layer, we need to provide a hook
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) * here and call re_jq_prep_dma_genq() function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (flags & DMA_PREP_PQ_DISABLE_P)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) return fsl_re_prep_dma_genq(chan, dest[1], src, src_cnt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) scf, len, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (flags & DMA_PREP_CONTINUE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) src_cnt += 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) desc = fsl_re_chan_alloc_desc(re_chan, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) if (desc <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /* Filling GenQQ CDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) cdb = FSL_RE_PQ_OPCODE << FSL_RE_CDB_OPCODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) cdb |= (src_cnt - 1) << FSL_RE_CDB_NRCS_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) cdb |= FSL_RE_BLOCK_SIZE << FSL_RE_CDB_BLKSIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) cdb |= FSL_RE_BUFFER_OUTPUT << FSL_RE_CDB_BUFFER_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) cdb |= FSL_RE_DATA_DEP << FSL_RE_CDB_DEPEND_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) pq = desc->cdb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) pq->cdb32 = cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) p = pq->gfm_q1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* Init gfm_q1[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) for (i = 0; i < src_cnt; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) p[i] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Align gfm[] to 32bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) gfmq_len = ALIGN(src_cnt, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* Init gfm_q2[] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) p += gfmq_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) for (i = 0; i < src_cnt; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) p[i] = scf[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) /* Filling frame 0 of compound frame descriptor with CDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) cf = desc->cf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) fill_cfd_frame(cf, 0, sizeof(struct fsl_re_pq_cdb), desc->cdb_paddr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) /* Fill CFD's 1st & 2nd frame with dest buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) for (i = 1, j = 0; i < 3; i++, j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) fill_cfd_frame(cf, i, len, dest[j], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Fill CFD's rest of the frames with source buffers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) for (i = 3, j = 0; j < save_src_cnt; i++, j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) fill_cfd_frame(cf, i, len, src[j], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /* PQ computation continuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) if (flags & DMA_PREP_CONTINUE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (src_cnt - save_src_cnt == 3) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) p[save_src_cnt] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) p[save_src_cnt + 1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) p[save_src_cnt + 2] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) fill_cfd_frame(cf, i++, len, dest[0], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) fill_cfd_frame(cf, i++, len, dest[1], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) fill_cfd_frame(cf, i++, len, dest[1], 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) dev_err(re_chan->dev, "PQ tx continuation error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Setting the final bit in the last source buffer frame in CFD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) cf[i - 1].efrl32 |= 1 << FSL_RE_CF_FINAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) return &desc->async_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) * Prep function for memcpy. In RAID Engine, memcpy is done through MOVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) * command. Logic of this function will need to be modified once multipage
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * support is added in Linux's MD/ASYNC Layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) static struct dma_async_tx_descriptor *fsl_re_prep_dma_memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) struct fsl_re_chan *re_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct fsl_re_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) size_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct fsl_re_cmpnd_frame *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct fsl_re_move_cdb *move;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) re_chan = container_of(chan, struct fsl_re_chan, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (len > FSL_RE_MAX_DATA_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) dev_err(re_chan->dev, "cp tx length is %zu, max length is %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) len, FSL_RE_MAX_DATA_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) desc = fsl_re_chan_alloc_desc(re_chan, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) if (desc <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /* Filling move CDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) cdb = FSL_RE_MOVE_OPCODE << FSL_RE_CDB_OPCODE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) cdb |= FSL_RE_BLOCK_SIZE << FSL_RE_CDB_BLKSIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) cdb |= FSL_RE_INTR_ON_ERROR << FSL_RE_CDB_ERROR_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) cdb |= FSL_RE_DATA_DEP << FSL_RE_CDB_DEPEND_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) move = desc->cdb_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) move->cdb32 = cdb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) /* Filling frame 0 of CFD with move CDB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) cf = desc->cf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) fill_cfd_frame(cf, 0, sizeof(*move), desc->cdb_paddr, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) length = min_t(size_t, len, FSL_RE_MAX_DATA_LEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) /* Fill CFD's 1st frame with dest buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) fill_cfd_frame(cf, 1, length, dest, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /* Fill CFD's 2nd frame with src buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) fill_cfd_frame(cf, 2, length, src, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) return &desc->async_tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) static int fsl_re_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) struct fsl_re_chan *re_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) struct fsl_re_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) void *cf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) dma_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) re_chan = container_of(chan, struct fsl_re_chan, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) for (i = 0; i < FSL_RE_MIN_DESCS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) desc = kzalloc(sizeof(*desc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (!desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) cf = dma_pool_alloc(re_chan->re_dev->cf_desc_pool, GFP_KERNEL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) &paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (!cf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) INIT_LIST_HEAD(&desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) fsl_re_init_desc(re_chan, desc, cf, paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) list_add_tail(&desc->node, &re_chan->free_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) re_chan->alloc_count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return re_chan->alloc_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static void fsl_re_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) struct fsl_re_chan *re_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct fsl_re_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) re_chan = container_of(chan, struct fsl_re_chan, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) while (re_chan->alloc_count--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) desc = list_first_entry(&re_chan->free_q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct fsl_re_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) list_del(&desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) dma_pool_free(re_chan->re_dev->cf_desc_pool, desc->cf_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) desc->cf_paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (!list_empty(&re_chan->free_q))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_err(re_chan->dev, "chan resource cannot be cleaned!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int fsl_re_chan_probe(struct platform_device *ofdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) struct device_node *np, u8 q, u32 off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) struct device *dev, *chandev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) struct fsl_re_drv_private *re_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct fsl_re_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct dma_device *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) u32 ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int ret = 0, rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) struct platform_device *chan_ofdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev = &ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) re_priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dma_dev = &re_priv->dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) chan = devm_kzalloc(dev, sizeof(*chan), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) /* create platform device for chan node */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) chan_ofdev = of_platform_device_create(np, NULL, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (!chan_ofdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) dev_err(dev, "Not able to create ofdev for jr %d\n", q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) /* read reg property from dts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) rc = of_property_read_u32(np, "reg", &ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) dev_err(dev, "Reg property not found in jr %d\n", q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) chan->jrregs = (struct fsl_re_chan_cfg *)((u8 *)re_priv->re_regs +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) off + ptr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /* read irq property from dts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) chan->irq = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (!chan->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) dev_err(dev, "No IRQ defined for JR %d\n", q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) snprintf(chan->name, sizeof(chan->name), "re_jr%02d", q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) chandev = &chan_ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) tasklet_setup(&chan->irqtask, fsl_re_dequeue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) ret = request_irq(chan->irq, fsl_re_isr, 0, chan->name, chandev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) dev_err(dev, "Unable to register interrupt for JR %d\n", q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) re_priv->re_jrs[q] = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) chan->chan.device = dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) chan->chan.private = chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) chan->dev = chandev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) chan->re_dev = re_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) spin_lock_init(&chan->desc_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) INIT_LIST_HEAD(&chan->ack_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) INIT_LIST_HEAD(&chan->active_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) INIT_LIST_HEAD(&chan->submit_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) INIT_LIST_HEAD(&chan->free_q);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) chan->inb_ring_virt_addr = dma_pool_alloc(chan->re_dev->hw_desc_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) GFP_KERNEL, &chan->inb_phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (!chan->inb_ring_virt_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) dev_err(dev, "No dma memory for inb_ring_virt_addr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) goto err_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) chan->oub_ring_virt_addr = dma_pool_alloc(chan->re_dev->hw_desc_pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) GFP_KERNEL, &chan->oub_phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (!chan->oub_ring_virt_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) dev_err(dev, "No dma memory for oub_ring_virt_addr\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) goto err_free_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /* Program the Inbound/Outbound ring base addresses and size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) out_be32(&chan->jrregs->inbring_base_h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) chan->inb_phys_addr & FSL_RE_ADDR_BIT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) out_be32(&chan->jrregs->oubring_base_h,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) chan->oub_phys_addr & FSL_RE_ADDR_BIT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) out_be32(&chan->jrregs->inbring_base_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) chan->inb_phys_addr >> FSL_RE_ADDR_BIT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) out_be32(&chan->jrregs->oubring_base_l,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) chan->oub_phys_addr >> FSL_RE_ADDR_BIT_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) out_be32(&chan->jrregs->inbring_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) FSL_RE_RING_SIZE << FSL_RE_RING_SIZE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) out_be32(&chan->jrregs->oubring_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) FSL_RE_RING_SIZE << FSL_RE_RING_SIZE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /* Read LIODN value from u-boot */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) status = in_be32(&chan->jrregs->jr_config_1) & FSL_RE_REG_LIODN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* Program the CFG reg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) out_be32(&chan->jrregs->jr_config_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) FSL_RE_CFG1_CBSI | FSL_RE_CFG1_CBS0 | status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) dev_set_drvdata(chandev, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* Enable RE/CHAN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) out_be32(&chan->jrregs->jr_command, FSL_RE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) err_free_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) dma_pool_free(chan->re_dev->hw_desc_pool, chan->inb_ring_virt_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) chan->inb_phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) err_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* Probe function for RAID Engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) static int fsl_re_probe(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) struct fsl_re_drv_private *re_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct device_node *np;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) u32 off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) u8 ridx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct dma_device *dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct device *dev = &ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) re_priv = devm_kzalloc(dev, sizeof(*re_priv), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (!re_priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /* IOMAP the entire RAID Engine region */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) re_priv->re_regs = devm_ioremap(dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (!re_priv->re_regs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /* Program the RE mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) out_be32(&re_priv->re_regs->global_config, FSL_RE_NON_DPAA_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /* Program Galois Field polynomial */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) out_be32(&re_priv->re_regs->galois_field_config, FSL_RE_GFM_POLY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) dev_info(dev, "version %x, mode %x, gfp %x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) in_be32(&re_priv->re_regs->re_version_id),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) in_be32(&re_priv->re_regs->global_config),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) in_be32(&re_priv->re_regs->galois_field_config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) dma_dev = &re_priv->dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dma_dev->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) INIT_LIST_HEAD(&dma_dev->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dma_set_mask(dev, DMA_BIT_MASK(40));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) dma_dev->device_alloc_chan_resources = fsl_re_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) dma_dev->device_tx_status = fsl_re_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) dma_dev->device_issue_pending = fsl_re_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) dma_dev->max_xor = FSL_RE_MAX_XOR_SRCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dma_dev->device_prep_dma_xor = fsl_re_prep_dma_xor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) dma_cap_set(DMA_XOR, dma_dev->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dma_dev->max_pq = FSL_RE_MAX_PQ_SRCS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) dma_dev->device_prep_dma_pq = fsl_re_prep_dma_pq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) dma_cap_set(DMA_PQ, dma_dev->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dma_dev->device_prep_dma_memcpy = fsl_re_prep_dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dma_cap_set(DMA_MEMCPY, dma_dev->cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) dma_dev->device_free_chan_resources = fsl_re_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) re_priv->total_chans = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) re_priv->cf_desc_pool = dmam_pool_create("fsl_re_cf_desc_pool", dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) FSL_RE_CF_CDB_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) FSL_RE_CF_CDB_ALIGN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (!re_priv->cf_desc_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) dev_err(dev, "No memory for fsl re_cf desc pool\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) re_priv->hw_desc_pool = dmam_pool_create("fsl_re_hw_desc_pool", dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) sizeof(struct fsl_re_hw_desc) * FSL_RE_RING_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) FSL_RE_FRAME_ALIGN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) if (!re_priv->hw_desc_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) dev_err(dev, "No memory for fsl re_hw desc pool\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) dev_set_drvdata(dev, re_priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* Parse Device tree to find out the total number of JQs present */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) for_each_compatible_node(np, NULL, "fsl,raideng-v1.0-job-queue") {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) rc = of_property_read_u32(np, "reg", &off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) dev_err(dev, "Reg property not found in JQ node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) of_node_put(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) /* Find out the Job Rings present under each JQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) for_each_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) rc = of_device_is_compatible(child,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) "fsl,raideng-v1.0-job-ring");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) fsl_re_chan_probe(ofdev, child, ridx++, off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) re_priv->total_chans++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dma_async_device_register(dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static void fsl_re_remove_chan(struct fsl_re_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) tasklet_kill(&chan->irqtask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dma_pool_free(chan->re_dev->hw_desc_pool, chan->inb_ring_virt_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) chan->inb_phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) dma_pool_free(chan->re_dev->hw_desc_pool, chan->oub_ring_virt_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) chan->oub_phys_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int fsl_re_remove(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct fsl_re_drv_private *re_priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dev = &ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) re_priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /* Cleanup chan related memory areas */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) for (i = 0; i < re_priv->total_chans; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) fsl_re_remove_chan(re_priv->re_jrs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* Unregister the driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) dma_async_device_unregister(&re_priv->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static const struct of_device_id fsl_re_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) { .compatible = "fsl,raideng-v1.0", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) MODULE_DEVICE_TABLE(of, fsl_re_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static struct platform_driver fsl_re_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) .name = "fsl-raideng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) .of_match_table = fsl_re_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) .probe = fsl_re_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) .remove = fsl_re_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) module_platform_driver(fsl_re_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) MODULE_AUTHOR("Harninder Rai <harninder.rai@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) MODULE_DESCRIPTION("Freescale RAID Engine Device Driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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