^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * drivers/dma/fsl-edma.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright 2013-2014 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Driver for the Freescale eDMA engine with flexible channel multiplexing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * capability for DMA request sources. The eDMA block can be found on some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Vybrid and Layerscape SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include "fsl-edma-common.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) static void fsl_edma_synchronize(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) struct fsl_edma_chan *fsl_chan = to_fsl_edma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) vchan_synchronize(&fsl_chan->vchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) static irqreturn_t fsl_edma_tx_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) struct fsl_edma_engine *fsl_edma = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned int intr, ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct edma_regs *regs = &fsl_edma->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct fsl_edma_chan *fsl_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) intr = edma_readl(fsl_edma, regs->intl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) if (!intr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) for (ch = 0; ch < fsl_edma->n_chans; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) if (intr & (0x1 << ch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) fsl_chan = &fsl_edma->chans[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) spin_lock(&fsl_chan->vchan.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (!fsl_chan->edesc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* terminate_all called before */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) spin_unlock(&fsl_chan->vchan.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) if (!fsl_chan->edesc->iscyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) list_del(&fsl_chan->edesc->vdesc.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) vchan_cookie_complete(&fsl_chan->edesc->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) fsl_chan->edesc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) fsl_chan->status = DMA_COMPLETE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) fsl_chan->idle = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) vchan_cyclic_callback(&fsl_chan->edesc->vdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) if (!fsl_chan->edesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) fsl_edma_xfer_desc(fsl_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) spin_unlock(&fsl_chan->vchan.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static irqreturn_t fsl_edma_err_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct fsl_edma_engine *fsl_edma = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) unsigned int err, ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct edma_regs *regs = &fsl_edma->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) err = edma_readl(fsl_edma, regs->errl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) for (ch = 0; ch < fsl_edma->n_chans; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (err & (0x1 << ch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) fsl_edma_disable_request(&fsl_edma->chans[ch]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) fsl_edma->chans[ch].status = DMA_ERROR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) fsl_edma->chans[ch].idle = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) static irqreturn_t fsl_edma_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) if (fsl_edma_tx_handler(irq, dev_id) == IRQ_HANDLED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return fsl_edma_err_handler(irq, dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) static struct dma_chan *fsl_edma_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct dma_chan *chan, *_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct fsl_edma_chan *fsl_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 dmamux_nr = fsl_edma->drvdata->dmamuxs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (dma_spec->args_count != 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) mutex_lock(&fsl_edma->fsl_edma_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) if (chan->client_count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) if ((chan->chan_id / chans_per_mux) == dma_spec->args[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) chan = dma_get_slave_channel(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) if (chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) chan->device->privatecnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) fsl_chan = to_fsl_edma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) fsl_chan->slave_id = dma_spec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) mutex_unlock(&fsl_edma->fsl_edma_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) mutex_unlock(&fsl_edma->fsl_edma_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) if (fsl_edma->txirq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) return fsl_edma->txirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) if (fsl_edma->errirq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return fsl_edma->errirq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) if (fsl_edma->txirq == fsl_edma->errirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) dev_err(&pdev->dev, "Can't register eDMA IRQ.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dev_err(&pdev->dev, "Can't register eDMA tx IRQ.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) dev_err(&pdev->dev, "Can't register eDMA err IRQ.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) fsl_edma2_irq_init(struct platform_device *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct fsl_edma_engine *fsl_edma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) int i, ret, irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) int count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) count = platform_irq_count(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dev_dbg(&pdev->dev, "%s Found %d interrupts\r\n", __func__, count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) if (count <= 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) dev_err(&pdev->dev, "Interrupts in DTS not correct.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * 16 channel independent interrupts + 1 error interrupt on i.mx7ulp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * 2 channel share one interrupt, for example, ch0/ch16, ch1/ch17...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * For now, just simply request irq without IRQF_SHARED flag, since 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * channels are enough on i.mx7ulp whose M4 domain own some peripherals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) for (i = 0; i < count; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) irq = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* The last IRQ is for eDMA err */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) if (i == count - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) ret = devm_request_irq(&pdev->dev, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) fsl_edma_err_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 0, "eDMA2-ERR", fsl_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) ret = devm_request_irq(&pdev->dev, irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) fsl_edma_tx_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) fsl_edma->chans[i].chan_name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) fsl_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static void fsl_edma_irq_exit(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (fsl_edma->txirq == fsl_edma->errirq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) for (i = 0; i < nr_clocks; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) clk_disable_unprepare(fsl_edma->muxclk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static struct fsl_edma_drvdata vf610_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) .version = v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) .dmamuxs = DMAMUX_NR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) .setup_irq = fsl_edma_irq_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static struct fsl_edma_drvdata ls1028a_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) .version = v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .dmamuxs = DMAMUX_NR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .mux_swap = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) .setup_irq = fsl_edma_irq_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static struct fsl_edma_drvdata imx7ulp_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) .version = v3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) .dmamuxs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) .has_dmaclk = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) .setup_irq = fsl_edma2_irq_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static const struct of_device_id fsl_edma_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) { .compatible = "fsl,vf610-edma", .data = &vf610_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) { .compatible = "fsl,ls1028a-edma", .data = &ls1028a_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) { .compatible = "fsl,imx7ulp-edma", .data = &imx7ulp_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) MODULE_DEVICE_TABLE(of, fsl_edma_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) static int fsl_edma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) const struct of_device_id *of_id =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) of_match_device(fsl_edma_dt_ids, &pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct fsl_edma_engine *fsl_edma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) const struct fsl_edma_drvdata *drvdata = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct fsl_edma_chan *fsl_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct edma_regs *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int len, chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (of_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) drvdata = of_id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (!drvdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_err(&pdev->dev, "unable to find driver data\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) ret = of_property_read_u32(np, "dma-channels", &chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dev_err(&pdev->dev, "Can't get dma-channels.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) len = sizeof(*fsl_edma) + sizeof(*fsl_chan) * chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) fsl_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!fsl_edma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) fsl_edma->drvdata = drvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) fsl_edma->n_chans = chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) mutex_init(&fsl_edma->fsl_edma_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) if (IS_ERR(fsl_edma->membase))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return PTR_ERR(fsl_edma->membase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) fsl_edma_setup_regs(fsl_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) regs = &fsl_edma->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) if (drvdata->has_dmaclk) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (IS_ERR(fsl_edma->dmaclk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) dev_err(&pdev->dev, "Missing DMA block clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return PTR_ERR(fsl_edma->dmaclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) ret = clk_prepare_enable(fsl_edma->dmaclk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) dev_err(&pdev->dev, "DMA clk block failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) char clkname[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) res = platform_get_resource(pdev, IORESOURCE_MEM, 1 + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (IS_ERR(fsl_edma->muxbase[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* on error: disable all previously enabled clks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) fsl_disable_clocks(fsl_edma, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return PTR_ERR(fsl_edma->muxbase[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) sprintf(clkname, "dmamux%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (IS_ERR(fsl_edma->muxclk[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_err(&pdev->dev, "Missing DMAMUX block clock.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* on error: disable all previously enabled clks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) fsl_disable_clocks(fsl_edma, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return PTR_ERR(fsl_edma->muxclk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) ret = clk_prepare_enable(fsl_edma->muxclk[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) /* on error: disable all previously enabled clks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) fsl_disable_clocks(fsl_edma, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) for (i = 0; i < fsl_edma->n_chans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) fsl_chan->edma = fsl_edma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) fsl_chan->pm_state = RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) fsl_chan->slave_id = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) fsl_chan->idle = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) fsl_chan->dma_dir = DMA_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) fsl_chan->vchan.desc_free = fsl_edma_free_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) fsl_edma_chan_mux(fsl_chan, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) edma_writel(fsl_edma, ~0, regs->intl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) fsl_edma->dma_dev.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) fsl_edma->dma_dev.device_alloc_chan_resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) = fsl_edma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) fsl_edma->dma_dev.device_free_chan_resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) = fsl_edma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) fsl_edma->dma_dev.device_pause = fsl_edma_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) fsl_edma->dma_dev.device_resume = fsl_edma_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) platform_set_drvdata(pdev, fsl_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) ret = dma_async_device_register(&fsl_edma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) "Can't register Freescale eDMA engine. (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) "Can't register Freescale eDMA of_dma. (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dma_async_device_unregister(&fsl_edma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /* enable round robin arbitration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int fsl_edma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct device_node *np = pdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) fsl_edma_irq_exit(pdev, fsl_edma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) of_dma_controller_free(np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dma_async_device_unregister(&fsl_edma->dma_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) static int fsl_edma_suspend_late(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct fsl_edma_chan *fsl_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) for (i = 0; i < fsl_edma->n_chans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) fsl_chan = &fsl_edma->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) spin_lock_irqsave(&fsl_chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) /* Make sure chan is idle or will force disable. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (unlikely(!fsl_chan->idle)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dev_warn(dev, "WARN: There is non-idle channel.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) fsl_edma_disable_request(fsl_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) fsl_edma_chan_mux(fsl_chan, 0, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) fsl_chan->pm_state = SUSPENDED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) spin_unlock_irqrestore(&fsl_chan->vchan.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int fsl_edma_resume_early(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct fsl_edma_chan *fsl_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct edma_regs *regs = &fsl_edma->regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) for (i = 0; i < fsl_edma->n_chans; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) fsl_chan = &fsl_edma->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) fsl_chan->pm_state = RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (fsl_chan->slave_id != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) fsl_edma_chan_mux(fsl_chan, fsl_chan->slave_id, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) * eDMA provides the service to others, so it should be suspend late
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) * and resume early. When eDMA suspend, all of the clients should stop
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) * the DMA data transmission and let the channel idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) static const struct dev_pm_ops fsl_edma_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) .suspend_late = fsl_edma_suspend_late,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) .resume_early = fsl_edma_resume_early,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static struct platform_driver fsl_edma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .name = "fsl-edma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .of_match_table = fsl_edma_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .pm = &fsl_edma_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) .probe = fsl_edma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) .remove = fsl_edma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) static int __init fsl_edma_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) return platform_driver_register(&fsl_edma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) subsys_initcall(fsl_edma_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static void __exit fsl_edma_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) platform_driver_unregister(&fsl_edma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) module_exit(fsl_edma_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) MODULE_ALIAS("platform:fsl-edma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) MODULE_DESCRIPTION("Freescale eDMA engine driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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