^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright 2019 NXP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef __DPAA2_QDMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define __DPAA2_QDMA_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define DPAA2_QDMA_STORE_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define NUM_CH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) struct dpaa2_qdma_sd_d {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) u32 rsv:32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) u32 ssd:12; /* souce stride distance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u32 sss:12; /* souce stride size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) u32 rsv1:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) } sdf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) u32 dsd:12; /* Destination stride distance */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) u32 dss:12; /* Destination stride size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u32 rsv2:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) } ddf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) } df;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) u32 rbpcmd; /* Route-by-port command */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) u32 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) } __attribute__((__packed__));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Source descriptor command read transaction type for RBP=0: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* coherent copy of cacheable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define QDMA_SD_CMD_RDTTYPE_COHERENT (0xb << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) /* Destination descriptor command write transaction type for RBP=0: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* coherent copy of cacheable memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define QDMA_DD_CMD_WRTTYPE_COHERENT (0x6 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LX2160_QDMA_DD_CMD_WRTTYPE_COHERENT (0xb << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define QMAN_FD_FMT_ENABLE BIT(0) /* frame list table enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define QMAN_FD_BMT_ENABLE BIT(15) /* bypass memory translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define QMAN_FD_BMT_DISABLE (0) /* bypass memory translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define QMAN_FD_SL_DISABLE (0) /* short lengthe disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define QMAN_FD_SL_ENABLE BIT(14) /* short lengthe enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define QDMA_FINAL_BIT_DISABLE (0) /* final bit disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define QDMA_FINAL_BIT_ENABLE BIT(31) /* final bit enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define QDMA_FD_SHORT_FORMAT BIT(11) /* short format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define QDMA_FD_LONG_FORMAT (0) /* long format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define QDMA_SER_DISABLE (8) /* no notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define QDMA_SER_CTX BIT(8) /* notification by FQD_CTX[fqid] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define QDMA_SER_DEST (2 << 8) /* notification by destination desc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define QDMA_SER_BOTH (3 << 8) /* soruce and dest notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define QDMA_FD_SPF_ENALBE BIT(30) /* source prefetch enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define QMAN_FD_VA_ENABLE BIT(14) /* Address used is virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define QMAN_FD_VA_DISABLE (0)/* Address used is a real address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* Flow Context: 49bit physical address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define QMAN_FD_CBMT_ENABLE BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define QMAN_FD_CBMT_DISABLE (0) /* Flow Context: 64bit virtual address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define QMAN_FD_SC_DISABLE (0) /* stashing control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define QDMA_FL_FMT_SBF (0x0) /* Single buffer frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define QDMA_FL_FMT_SGE (0x2) /* Scatter gather frame */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define QDMA_FL_BMT_ENABLE BIT(15) /* enable bypass memory translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define QDMA_FL_BMT_DISABLE (0x0) /* enable bypass memory translation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define QDMA_FL_SL_LONG (0x0)/* long length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define QDMA_FL_SL_SHORT (0x1) /* short length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define QDMA_FL_F (0x1)/* last frame list bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*Description of Frame list table structure*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct dpaa2_qdma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct dpaa2_qdma_engine *qdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct virt_dma_chan vchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct virt_dma_desc vdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) enum dma_status status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) u32 fqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* spinlock used by dpaa2 qdma driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) spinlock_t queue_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct dma_pool *fd_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct dma_pool *fl_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct dma_pool *sdd_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct list_head comp_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct list_head comp_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct dpaa2_qdma_comp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) dma_addr_t fd_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) dma_addr_t fl_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) dma_addr_t desc_bus_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) struct dpaa2_fd *fd_virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) struct dpaa2_fl_entry *fl_virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct dpaa2_qdma_sd_d *desc_virt_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct dpaa2_qdma_chan *qchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct virt_dma_desc vdesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) struct dpaa2_qdma_engine {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) struct dma_device dma_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 n_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct dpaa2_qdma_chan chans[NUM_CH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) int qdma_wrtype_fixup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) int desc_allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) struct dpaa2_qdma_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * dpaa2_qdma_priv - driver private data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) struct dpaa2_qdma_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int dpqdma_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct iommu_domain *iommu_domain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct dpdmai_attr dpdmai_attr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct fsl_mc_io *mc_io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct fsl_mc_device *dpdmai_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u8 num_pairs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct dpaa2_qdma_engine *dpaa2_qdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) struct dpaa2_qdma_priv_per_prio *ppriv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) struct dpdmai_rx_queue_attr rx_queue_attr[DPDMAI_PRIO_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 tx_fqid[DPDMAI_PRIO_NUM];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct dpaa2_qdma_priv_per_prio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) int req_fqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) int rsp_fqid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) int prio;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct dpaa2_io_store *store;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct dpaa2_io_notification_ctx nctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct dpaa2_qdma_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) static struct soc_device_attribute soc_fixup_tuning[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) { .family = "QorIQ LX2160A"},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* FD pool size: one FD + 3 Frame list + 2 source/destination descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define FD_POOL_SIZE (sizeof(struct dpaa2_fd) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) sizeof(struct dpaa2_fl_entry) * 3 + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) sizeof(struct dpaa2_qdma_sd_d) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static void dpaa2_dpdmai_free_channels(struct dpaa2_qdma_engine *dpaa2_qdma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) static void dpaa2_dpdmai_free_comp(struct dpaa2_qdma_chan *qchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct list_head *head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #endif /* __DPAA2_QDMA_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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