^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (C) 2013,2018 Intel Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include "internal.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) static void idma32_initialize_chan(struct dw_dma_chan *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) u32 cfghi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) u32 cfglo = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* Set default burst alignment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) cfglo |= IDMA32C_CFGL_DST_BURST_ALIGN | IDMA32C_CFGL_SRC_BURST_ALIGN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* Low 4 bits of the request lines */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) cfghi |= IDMA32C_CFGH_DST_PER(dwc->dws.dst_id & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) cfghi |= IDMA32C_CFGH_SRC_PER(dwc->dws.src_id & 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* Request line extension (2 bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) cfghi |= IDMA32C_CFGH_DST_PER_EXT(dwc->dws.dst_id >> 4 & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) cfghi |= IDMA32C_CFGH_SRC_PER_EXT(dwc->dws.src_id >> 4 & 0x3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) channel_writel(dwc, CFG_LO, cfglo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) channel_writel(dwc, CFG_HI, cfghi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static void idma32_suspend_chan(struct dw_dma_chan *dwc, bool drain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 cfglo = channel_readl(dwc, CFG_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) if (drain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) cfglo |= IDMA32C_CFGL_CH_DRAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) channel_writel(dwc, CFG_LO, cfglo | DWC_CFGL_CH_SUSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) static void idma32_resume_chan(struct dw_dma_chan *dwc, bool drain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) u32 cfglo = channel_readl(dwc, CFG_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) if (drain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) cfglo &= ~IDMA32C_CFGL_CH_DRAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) channel_writel(dwc, CFG_LO, cfglo & ~DWC_CFGL_CH_SUSP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) static u32 idma32_bytes2block(struct dw_dma_chan *dwc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) size_t bytes, unsigned int width, size_t *len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) if (bytes > dwc->block_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) block = dwc->block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) *len = dwc->block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) block = bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) *len = bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) return block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) static size_t idma32_block2bytes(struct dw_dma_chan *dwc, u32 block, u32 width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) return IDMA32C_CTLH_BLOCK_TS(block);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) static u32 idma32_prepare_ctllo(struct dw_dma_chan *dwc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct dma_slave_config *sconfig = &dwc->dma_sconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 smsize = (dwc->direction == DMA_DEV_TO_MEM) ? sconfig->src_maxburst : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) u8 dmsize = (dwc->direction == DMA_MEM_TO_DEV) ? sconfig->dst_maxburst : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return DWC_CTLL_LLP_D_EN | DWC_CTLL_LLP_S_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) DWC_CTLL_DST_MSIZE(dmsize) | DWC_CTLL_SRC_MSIZE(smsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) static void idma32_encode_maxburst(struct dw_dma_chan *dwc, u32 *maxburst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) *maxburst = *maxburst > 1 ? fls(*maxburst) - 1 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) static void idma32_set_device_name(struct dw_dma *dw, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) snprintf(dw->name, sizeof(dw->name), "idma32:dmac%d", id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * Program FIFO size of channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * By default full FIFO (512 bytes) is assigned to channel 0. Here we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * slice FIFO on equal parts between channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) static void idma32_fifo_partition(struct dw_dma *dw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u64 value = IDMA32C_FP_PSIZE_CH0(64) | IDMA32C_FP_PSIZE_CH1(64) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) IDMA32C_FP_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u64 fifo_partition = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Fill FIFO_PARTITION low bits (Channels 0..1, 4..5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) fifo_partition |= value << 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* Fill FIFO_PARTITION high bits (Channels 2..3, 6..7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) fifo_partition |= value << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Program FIFO Partition registers - 64 bytes per channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) idma32_writeq(dw, FIFO_PARTITION1, fifo_partition);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) idma32_writeq(dw, FIFO_PARTITION0, fifo_partition);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) static void idma32_disable(struct dw_dma *dw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) do_dw_dma_off(dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) idma32_fifo_partition(dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) static void idma32_enable(struct dw_dma *dw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) idma32_fifo_partition(dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) do_dw_dma_on(dw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) int idma32_dma_probe(struct dw_dma_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct dw_dma *dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) dw = devm_kzalloc(chip->dev, sizeof(*dw), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) if (!dw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Channel operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dw->initialize_chan = idma32_initialize_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) dw->suspend_chan = idma32_suspend_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) dw->resume_chan = idma32_resume_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) dw->prepare_ctllo = idma32_prepare_ctllo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) dw->encode_maxburst = idma32_encode_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dw->bytes2block = idma32_bytes2block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dw->block2bytes = idma32_block2bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* Device operations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dw->set_device_name = idma32_set_device_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) dw->disable = idma32_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dw->enable = idma32_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) chip->dw = dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) return do_dma_probe(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) EXPORT_SYMBOL_GPL(idma32_dma_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) int idma32_dma_remove(struct dw_dma_chip *chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) return do_dma_remove(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) EXPORT_SYMBOL_GPL(idma32_dma_remove);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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