^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Synopsys DesignWare eDMA v0 core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _DW_EDMA_V0_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _DW_EDMA_V0_REGS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define EDMA_V0_MAX_NR_CH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define EDMA_V0_VIEWPORT_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define EDMA_V0_DONE_INT_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define EDMA_V0_ABORT_INT_MASK GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define EDMA_V0_WRITE_CH_COUNT_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EDMA_V0_READ_CH_COUNT_MASK GENMASK(19, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EDMA_V0_CH_STATUS_MASK GENMASK(6, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EDMA_V0_DOORBELL_CH_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EDMA_V0_LINKED_LIST_ERR_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EDMA_V0_CH_ODD_MSI_DATA_MASK GENMASK(31, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EDMA_V0_CH_EVEN_MSI_DATA_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) struct dw_edma_v0_ch_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) u32 ch_control1; /* 0x000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) u32 ch_control2; /* 0x004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) u32 transfer_size; /* 0x008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) u32 sar_low; /* 0x00c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) u32 sar_high; /* 0x010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 dar_low; /* 0x014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) u32 dar_high; /* 0x018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 llp_low; /* 0x01c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 llp_high; /* 0x020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct dw_edma_v0_ch {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct dw_edma_v0_ch_regs wr; /* 0x200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) u32 padding_1[55]; /* [0x224..0x2fc] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct dw_edma_v0_ch_regs rd; /* 0x300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) u32 padding_2[55]; /* [0x324..0x3fc] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct dw_edma_v0_unroll {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u32 padding_1; /* 0x0f8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) u32 wr_engine_chgroup; /* 0x100 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) u32 rd_engine_chgroup; /* 0x104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) u32 wr_engine_hshake_cnt_low; /* 0x108 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) u32 wr_engine_hshake_cnt_high; /* 0x10c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) u32 padding_2[2]; /* [0x110..0x114] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 rd_engine_hshake_cnt_low; /* 0x118 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 rd_engine_hshake_cnt_high; /* 0x11c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 padding_3[2]; /* [0x120..0x124] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 wr_ch0_pwr_en; /* 0x128 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 wr_ch1_pwr_en; /* 0x12c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 wr_ch2_pwr_en; /* 0x130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) u32 wr_ch3_pwr_en; /* 0x134 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) u32 wr_ch4_pwr_en; /* 0x138 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) u32 wr_ch5_pwr_en; /* 0x13c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) u32 wr_ch6_pwr_en; /* 0x140 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u32 wr_ch7_pwr_en; /* 0x144 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 padding_4[8]; /* [0x148..0x164] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 rd_ch0_pwr_en; /* 0x168 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) u32 rd_ch1_pwr_en; /* 0x16c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u32 rd_ch2_pwr_en; /* 0x170 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) u32 rd_ch3_pwr_en; /* 0x174 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 rd_ch4_pwr_en; /* 0x178 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) u32 rd_ch5_pwr_en; /* 0x18c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) u32 rd_ch6_pwr_en; /* 0x180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) u32 rd_ch7_pwr_en; /* 0x184 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 padding_5[30]; /* [0x188..0x1fc] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct dw_edma_v0_ch ch[EDMA_V0_MAX_NR_CH]; /* [0x200..0x1120] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) struct dw_edma_v0_legacy {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) u32 viewport_sel; /* 0x0f8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct dw_edma_v0_ch_regs ch; /* [0x100..0x120] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) struct dw_edma_v0_regs {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /* eDMA global registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) u32 ctrl_data_arb_prior; /* 0x000 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) u32 padding_1; /* 0x004 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) u32 ctrl; /* 0x008 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 wr_engine_en; /* 0x00c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 wr_doorbell; /* 0x010 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) u32 padding_2; /* 0x014 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) u32 wr_ch_arb_weight_low; /* 0x018 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 wr_ch_arb_weight_high; /* 0x01c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) u32 padding_3[3]; /* [0x020..0x028] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) u32 rd_engine_en; /* 0x02c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) u32 rd_doorbell; /* 0x030 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) u32 padding_4; /* 0x034 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) u32 rd_ch_arb_weight_low; /* 0x038 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) u32 rd_ch_arb_weight_high; /* 0x03c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) u32 padding_5[3]; /* [0x040..0x048] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* eDMA interrupts registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) u32 wr_int_status; /* 0x04c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) u32 padding_6; /* 0x050 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) u32 wr_int_mask; /* 0x054 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) u32 wr_int_clear; /* 0x058 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 wr_err_status; /* 0x05c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) u32 wr_done_imwr_low; /* 0x060 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) u32 wr_done_imwr_high; /* 0x064 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) u32 wr_abort_imwr_low; /* 0x068 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) u32 wr_abort_imwr_high; /* 0x06c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) u32 wr_ch01_imwr_data; /* 0x070 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) u32 wr_ch23_imwr_data; /* 0x074 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) u32 wr_ch45_imwr_data; /* 0x078 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 wr_ch67_imwr_data; /* 0x07c */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 padding_7[4]; /* [0x080..0x08c] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 wr_linked_list_err_en; /* 0x090 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 padding_8[3]; /* [0x094..0x09c] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 rd_int_status; /* 0x0a0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 padding_9; /* 0x0a4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 rd_int_mask; /* 0x0a8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 rd_int_clear; /* 0x0ac */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 padding_10; /* 0x0b0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) u32 rd_err_status_low; /* 0x0b4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 rd_err_status_high; /* 0x0b8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 padding_11[2]; /* [0x0bc..0x0c0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 rd_linked_list_err_en; /* 0x0c4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) u32 padding_12; /* 0x0c8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 rd_done_imwr_low; /* 0x0cc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 rd_done_imwr_high; /* 0x0d0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 rd_abort_imwr_low; /* 0x0d4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 rd_abort_imwr_high; /* 0x0d8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 rd_ch01_imwr_data; /* 0x0dc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 rd_ch23_imwr_data; /* 0x0e0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 rd_ch45_imwr_data; /* 0x0e4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 rd_ch67_imwr_data; /* 0x0e8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 padding_13[4]; /* [0x0ec..0x0f8] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* eDMA channel context grouping */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) union dw_edma_v0_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct dw_edma_v0_legacy legacy; /* [0x0f8..0x120] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct dw_edma_v0_unroll unroll; /* [0x0f8..0x1120] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) } type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct dw_edma_v0_lli {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) u32 sar_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 sar_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u32 dar_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u32 dar_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct dw_edma_v0_llp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) u32 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 llp_low;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) u32 llp_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #endif /* _DW_EDMA_V0_REGS_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags