^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018-2019 Synopsys, Inc. and/or its affiliates.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Synopsys DesignWare eDMA PCIe driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Gustavo Pimentel <gustavo.pimentel@synopsys.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dma/edma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pci-epf.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/msi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include "dw-edma-core.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct dw_edma_pcie_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* eDMA registers location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) enum pci_barno rg_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) off_t rg_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) size_t rg_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) /* eDMA memory linked list location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) enum pci_barno ll_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) off_t ll_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) size_t ll_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* eDMA memory data location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum pci_barno dt_bar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) off_t dt_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) size_t dt_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Other */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum dw_edma_mode mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u8 irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) static const struct dw_edma_pcie_data snps_edda_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* eDMA registers location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) .rg_bar = BAR_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) .rg_off = 0x00001000, /* 4 Kbytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) .rg_sz = 0x00002000, /* 8 Kbytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* eDMA memory linked list location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) .ll_bar = BAR_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) .ll_off = 0x00000000, /* 0 Kbytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) .ll_sz = 0x00800000, /* 8 Mbytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* eDMA memory data location */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) .dt_bar = BAR_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) .dt_off = 0x00800000, /* 8 Mbytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) .dt_sz = 0x03800000, /* 56 Mbytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Other */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) .version = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) .mode = EDMA_MODE_UNROLL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) .irqs = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static int dw_edma_pcie_irq_vector(struct device *dev, unsigned int nr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return pci_irq_vector(to_pci_dev(dev), nr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) static const struct dw_edma_core_ops dw_edma_pcie_core_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) .irq_vector = dw_edma_pcie_irq_vector,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) static int dw_edma_pcie_probe(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) const struct pci_device_id *pid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) const struct dw_edma_pcie_data *pdata = (void *)pid->driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct dw_edma_chip *chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) int err, nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct dw_edma *dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /* Enable PCI device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) err = pcim_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) pci_err(pdev, "enabling device failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* Mapping PCI BAR regions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) err = pcim_iomap_regions(pdev, BIT(pdata->rg_bar) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) BIT(pdata->ll_bar) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) BIT(pdata->dt_bar),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) pci_name(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) pci_err(pdev, "eDMA BAR I/O remapping failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* DMA configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) err = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) pci_err(pdev, "consistent DMA mask 64 set failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) pci_err(pdev, "DMA mask 64 set failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) err = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) pci_err(pdev, "DMA mask 32 set failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) pci_err(pdev, "consistent DMA mask 32 set failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Data structure allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) chip = devm_kzalloc(dev, sizeof(*chip), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) if (!chip)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) dw = devm_kzalloc(dev, sizeof(*dw), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) if (!dw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* IRQs allocation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) nr_irqs = pci_alloc_irq_vectors(pdev, 1, pdata->irqs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PCI_IRQ_MSI | PCI_IRQ_MSIX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (nr_irqs < 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) pci_err(pdev, "fail to alloc IRQ vector (number of IRQs=%u)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Data structure initialization */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) chip->dw = dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) chip->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) chip->id = pdev->devfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) chip->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) dw->rg_region.vaddr = pcim_iomap_table(pdev)[pdata->rg_bar];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) dw->rg_region.vaddr += pdata->rg_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dw->rg_region.paddr = pdev->resource[pdata->rg_bar].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dw->rg_region.paddr += pdata->rg_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) dw->rg_region.sz = pdata->rg_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) dw->ll_region.vaddr = pcim_iomap_table(pdev)[pdata->ll_bar];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dw->ll_region.vaddr += pdata->ll_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dw->ll_region.paddr = pdev->resource[pdata->ll_bar].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) dw->ll_region.paddr += pdata->ll_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) dw->ll_region.sz = pdata->ll_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) dw->dt_region.vaddr = pcim_iomap_table(pdev)[pdata->dt_bar];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) dw->dt_region.vaddr += pdata->dt_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) dw->dt_region.paddr = pdev->resource[pdata->dt_bar].start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dw->dt_region.paddr += pdata->dt_off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) dw->dt_region.sz = pdata->dt_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) dw->version = pdata->version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dw->mode = pdata->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) dw->nr_irqs = nr_irqs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dw->ops = &dw_edma_pcie_core_ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* Debug info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) pci_dbg(pdev, "Version:\t%u\n", dw->version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) pci_dbg(pdev, "Mode:\t%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dw->mode == EDMA_MODE_LEGACY ? "Legacy" : "Unroll");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) pci_dbg(pdev, "Registers:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) pdata->rg_bar, pdata->rg_off, pdata->rg_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) dw->rg_region.vaddr, &dw->rg_region.paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) pci_dbg(pdev, "L. List:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) pdata->ll_bar, pdata->ll_off, pdata->ll_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dw->ll_region.vaddr, &dw->ll_region.paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pci_dbg(pdev, "Data:\tBAR=%u, off=0x%.8lx, sz=0x%zx bytes, addr(v=%p, p=%pa)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) pdata->dt_bar, pdata->dt_off, pdata->dt_sz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dw->dt_region.vaddr, &dw->dt_region.paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) pci_dbg(pdev, "Nr. IRQs:\t%u\n", dw->nr_irqs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Validating if PCI interrupts were enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (!pci_dev_msi_enabled(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) pci_err(pdev, "enable interrupt failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) dw->irq = devm_kcalloc(dev, nr_irqs, sizeof(*dw->irq), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) if (!dw->irq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* Starting eDMA driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) err = dw_edma_probe(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) pci_err(pdev, "eDMA probe failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* Saving data structure reference */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) pci_set_drvdata(pdev, chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void dw_edma_pcie_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct dw_edma_chip *chip = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* Stopping eDMA driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) err = dw_edma_remove(chip);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) pci_warn(pdev, "can't remove device properly: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* Freeing IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static const struct pci_device_id dw_edma_pcie_id_table[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) { PCI_DEVICE_DATA(SYNOPSYS, EDDA, &snps_edda_data) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) { }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) MODULE_DEVICE_TABLE(pci, dw_edma_pcie_id_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) static struct pci_driver dw_edma_pcie_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) .name = "dw-edma-pcie",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) .id_table = dw_edma_pcie_id_table,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) .probe = dw_edma_pcie_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) .remove = dw_edma_pcie_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) module_pci_driver(dw_edma_pcie_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) MODULE_DESCRIPTION("Synopsys DesignWare eDMA PCIe driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) MODULE_AUTHOR("Gustavo Pimentel <gustavo.pimentel@synopsys.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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