^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) config DW_EDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) tristate "Synopsys DesignWare eDMA controller driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) depends on PCI && PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) Support the Synopsys DesignWare eDMA controller, normally
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) implemented on endpoints SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) config DW_EDMA_PCIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) tristate "Synopsys DesignWare eDMA PCIe driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) depends on PCI && PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) select DW_EDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) Provides a glue-logic between the Synopsys DesignWare
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) eDMA controller and an endpoint PCIe device. This also serves
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) as a reference design to whom desires to use this IP.