Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier:  GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) // (C) 2017-2018 Synopsys, Inc. (www.synopsys.com)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Synopsys DesignWare AXI DMA Controller driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * Author: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #ifndef _AXI_DMA_PLATFORM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define _AXI_DMA_PLATFORM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #include "../virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define DMAC_MAX_CHANNELS	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define DMAC_MAX_MASTERS	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define DMAC_MAX_BLK_SIZE	0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) struct dw_axi_dma_hcfg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 	u32	nr_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) 	u32	nr_masters;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 	u32	m_data_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 	u32	block_size[DMAC_MAX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) 	u32	priority[DMAC_MAX_CHANNELS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) 	/* maximum supported axi burst length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) 	u32	axi_rw_burst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 	bool	restrict_axi_burst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) struct axi_dma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) 	struct axi_dma_chip		*chip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) 	void __iomem			*chan_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) 	u8				id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) 	atomic_t			descs_allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 	struct virt_dma_chan		vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) 	/* these other elements are all protected by vc.lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 	bool				is_paused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) struct dw_axi_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 	struct dma_device	dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) 	struct dw_axi_dma_hcfg	*hdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 	struct dma_pool		*desc_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 	/* channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) 	struct axi_dma_chan	*chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) struct axi_dma_chip {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) 	struct device		*dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 	int			irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 	void __iomem		*regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) 	struct clk		*core_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) 	struct clk		*cfgr_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) 	struct dw_axi_dma	*dw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* LLI == Linked List Item */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) struct __packed axi_dma_lli {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) 	__le64		sar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) 	__le64		dar;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) 	__le32		block_ts_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 	__le32		block_ts_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 	__le64		llp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) 	__le32		ctl_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 	__le32		ctl_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) 	__le32		sstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) 	__le32		dstat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) 	__le32		status_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 	__le32		status_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) 	__le32		reserved_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 	__le32		reserved_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) struct axi_dma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 	struct axi_dma_lli		lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 	struct virt_dma_desc		vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) 	struct axi_dma_chan		*chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) 	struct list_head		xfer_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) static inline struct device *dchan2dev(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) 	return &dchan->dev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) static inline struct device *chan2dev(struct axi_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 	return &chan->vc.chan.dev->device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) static inline struct axi_dma_desc *vd_to_axi_desc(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) 	return container_of(vd, struct axi_dma_desc, vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) static inline struct axi_dma_chan *vc_to_axi_dma_chan(struct virt_dma_chan *vc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) 	return container_of(vc, struct axi_dma_chan, vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) static inline struct axi_dma_chan *dchan_to_axi_dma_chan(struct dma_chan *dchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) 	return vc_to_axi_dma_chan(to_virt_chan(dchan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define COMMON_REG_LEN		0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CHAN_REG_LEN		0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Common registers offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define DMAC_ID			0x000 /* R DMAC ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define DMAC_COMPVER		0x008 /* R DMAC Component Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DMAC_CFG		0x010 /* R/W DMAC Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DMAC_CHEN		0x018 /* R/W DMAC Channel Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define DMAC_CHEN_L		0x018 /* R/W DMAC Channel Enable 00-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define DMAC_CHEN_H		0x01C /* R/W DMAC Channel Enable 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DMAC_INTSTATUS		0x030 /* R DMAC Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define DMAC_COMMON_INTCLEAR	0x038 /* W DMAC Interrupt Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define DMAC_COMMON_INTSTATUS_ENA 0x040 /* R DMAC Interrupt Status Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DMAC_COMMON_INTSIGNAL_ENA 0x048 /* R/W DMAC Interrupt Signal Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DMAC_COMMON_INTSTATUS	0x050 /* R DMAC Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define DMAC_RESET		0x058 /* R DMAC Reset Register1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* DMA channel registers offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CH_SAR			0x000 /* R/W Chan Source Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CH_DAR			0x008 /* R/W Chan Destination Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CH_BLOCK_TS		0x010 /* R/W Chan Block Transfer Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CH_CTL			0x018 /* R/W Chan Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CH_CTL_L		0x018 /* R/W Chan Control 00-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CH_CTL_H		0x01C /* R/W Chan Control 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CH_CFG			0x020 /* R/W Chan Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CH_CFG_L		0x020 /* R/W Chan Configuration 00-31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CH_CFG_H		0x024 /* R/W Chan Configuration 32-63 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CH_LLP			0x028 /* R/W Chan Linked List Pointer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CH_STATUS		0x030 /* R Chan Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CH_SWHSSRC		0x038 /* R/W Chan SW Handshake Source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CH_SWHSDST		0x040 /* R/W Chan SW Handshake Destination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CH_BLK_TFR_RESUMEREQ	0x048 /* W Chan Block Transfer Resume Req */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CH_AXI_ID		0x050 /* R/W Chan AXI ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CH_AXI_QOS		0x058 /* R/W Chan AXI QOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CH_SSTAT		0x060 /* R Chan Source Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CH_DSTAT		0x068 /* R Chan Destination Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CH_SSTATAR		0x070 /* R/W Chan Source Status Fetch Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CH_DSTATAR		0x078 /* R/W Chan Destination Status Fetch Addr */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CH_INTSTATUS_ENA	0x080 /* R/W Chan Interrupt Status Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CH_INTSTATUS		0x088 /* R/W Chan Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CH_INTSIGNAL_ENA	0x090 /* R/W Chan Interrupt Signal Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CH_INTCLEAR		0x098 /* W Chan Interrupt Clear */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* DMAC_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DMAC_EN_POS			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DMAC_EN_MASK			BIT(DMAC_EN_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define INT_EN_POS			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define INT_EN_MASK			BIT(INT_EN_POS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DMAC_CHAN_EN_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DMAC_CHAN_EN_WE_SHIFT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define DMAC_CHAN_SUSP_SHIFT		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define DMAC_CHAN_SUSP_WE_SHIFT		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* CH_CTL_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CH_CTL_H_ARLEN_EN		BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CH_CTL_H_ARLEN_POS		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CH_CTL_H_AWLEN_EN		BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CH_CTL_H_AWLEN_POS		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 	DWAXIDMAC_ARWLEN_1		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 	DWAXIDMAC_ARWLEN_2		= 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) 	DWAXIDMAC_ARWLEN_4		= 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 	DWAXIDMAC_ARWLEN_8		= 7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 	DWAXIDMAC_ARWLEN_16		= 15,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 	DWAXIDMAC_ARWLEN_32		= 31,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 	DWAXIDMAC_ARWLEN_64		= 63,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 	DWAXIDMAC_ARWLEN_128		= 127,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) 	DWAXIDMAC_ARWLEN_256		= 255,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 	DWAXIDMAC_ARWLEN_MIN		= DWAXIDMAC_ARWLEN_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) 	DWAXIDMAC_ARWLEN_MAX		= DWAXIDMAC_ARWLEN_256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CH_CTL_H_LLI_LAST		BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CH_CTL_H_LLI_VALID		BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* CH_CTL_L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CH_CTL_L_LAST_WRITE_EN		BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CH_CTL_L_DST_MSIZE_POS		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CH_CTL_L_SRC_MSIZE_POS		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 	DWAXIDMAC_BURST_TRANS_LEN_1	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) 	DWAXIDMAC_BURST_TRANS_LEN_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 	DWAXIDMAC_BURST_TRANS_LEN_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) 	DWAXIDMAC_BURST_TRANS_LEN_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) 	DWAXIDMAC_BURST_TRANS_LEN_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) 	DWAXIDMAC_BURST_TRANS_LEN_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 	DWAXIDMAC_BURST_TRANS_LEN_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) 	DWAXIDMAC_BURST_TRANS_LEN_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) 	DWAXIDMAC_BURST_TRANS_LEN_512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) 	DWAXIDMAC_BURST_TRANS_LEN_1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CH_CTL_L_DST_WIDTH_POS		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CH_CTL_L_SRC_WIDTH_POS		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CH_CTL_L_DST_INC_POS		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CH_CTL_L_SRC_INC_POS		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) 	DWAXIDMAC_CH_CTL_L_INC		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 	DWAXIDMAC_CH_CTL_L_NOINC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CH_CTL_L_DST_MAST		BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CH_CTL_L_SRC_MAST		BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* CH_CFG_H */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CH_CFG_H_PRIORITY_POS		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CH_CFG_H_HS_SEL_DST_POS		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CH_CFG_H_HS_SEL_SRC_POS		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 	DWAXIDMAC_HS_SEL_HW		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) 	DWAXIDMAC_HS_SEL_SW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CH_CFG_H_TT_FC_POS		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) 	DWAXIDMAC_TT_FC_MEM_TO_MEM_DMAC	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 	DWAXIDMAC_TT_FC_MEM_TO_PER_DMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) 	DWAXIDMAC_TT_FC_PER_TO_MEM_DMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) 	DWAXIDMAC_TT_FC_PER_TO_PER_DMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 	DWAXIDMAC_TT_FC_PER_TO_MEM_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 	DWAXIDMAC_TT_FC_PER_TO_PER_SRC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) 	DWAXIDMAC_TT_FC_MEM_TO_PER_DST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) 	DWAXIDMAC_TT_FC_PER_TO_PER_DST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* CH_CFG_L */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CH_CFG_L_DST_MULTBLK_TYPE_POS	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CH_CFG_L_SRC_MULTBLK_TYPE_POS	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 	DWAXIDMAC_MBLK_TYPE_CONTIGUOUS	= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) 	DWAXIDMAC_MBLK_TYPE_RELOAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 	DWAXIDMAC_MBLK_TYPE_SHADOW_REG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) 	DWAXIDMAC_MBLK_TYPE_LL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)  * DW AXI DMA channel interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)  * @DWAXIDMAC_IRQ_NONE: Bitmask of no one interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)  * @DWAXIDMAC_IRQ_BLOCK_TRF: Block transfer complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)  * @DWAXIDMAC_IRQ_DMA_TRF: Dma transfer complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)  * @DWAXIDMAC_IRQ_SRC_TRAN: Source transaction complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)  * @DWAXIDMAC_IRQ_DST_TRAN: Destination transaction complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)  * @DWAXIDMAC_IRQ_SRC_DEC_ERR: Source decode error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)  * @DWAXIDMAC_IRQ_DST_DEC_ERR: Destination decode error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)  * @DWAXIDMAC_IRQ_SRC_SLV_ERR: Source slave error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271)  * @DWAXIDMAC_IRQ_DST_SLV_ERR: Destination slave error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)  * @DWAXIDMAC_IRQ_LLI_RD_DEC_ERR: LLI read decode error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)  * @DWAXIDMAC_IRQ_LLI_WR_DEC_ERR: LLI write decode error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)  * @DWAXIDMAC_IRQ_LLI_RD_SLV_ERR: LLI read slave error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)  * @DWAXIDMAC_IRQ_LLI_WR_SLV_ERR: LLI write slave error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)  * @DWAXIDMAC_IRQ_INVALID_ERR: LLI invalid error or Shadow register error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)  * @DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR: Slave Interface Multiblock type error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)  * @DWAXIDMAC_IRQ_DEC_ERR: Slave Interface decode error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)  * @DWAXIDMAC_IRQ_WR2RO_ERR: Slave Interface write to read only error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)  * @DWAXIDMAC_IRQ_RD2RWO_ERR: Slave Interface read to write only error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)  * @DWAXIDMAC_IRQ_WRONCHEN_ERR: Slave Interface write to channel error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)  * @DWAXIDMAC_IRQ_SHADOWREG_ERR: Slave Interface shadow reg error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)  * @DWAXIDMAC_IRQ_WRONHOLD_ERR: Slave Interface hold error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)  * @DWAXIDMAC_IRQ_LOCK_CLEARED: Lock Cleared Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)  * @DWAXIDMAC_IRQ_SRC_SUSPENDED: Source Suspended Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)  * @DWAXIDMAC_IRQ_SUSPENDED: Channel Suspended Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)  * @DWAXIDMAC_IRQ_DISABLED: Channel Disabled Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)  * @DWAXIDMAC_IRQ_ABORTED: Channel Aborted Status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)  * @DWAXIDMAC_IRQ_ALL_ERR: Bitmask of all error interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)  * @DWAXIDMAC_IRQ_ALL: Bitmask of all interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 	DWAXIDMAC_IRQ_NONE		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) 	DWAXIDMAC_IRQ_BLOCK_TRF		= BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) 	DWAXIDMAC_IRQ_DMA_TRF		= BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 	DWAXIDMAC_IRQ_SRC_TRAN		= BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) 	DWAXIDMAC_IRQ_DST_TRAN		= BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) 	DWAXIDMAC_IRQ_SRC_DEC_ERR	= BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 	DWAXIDMAC_IRQ_DST_DEC_ERR	= BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 	DWAXIDMAC_IRQ_SRC_SLV_ERR	= BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) 	DWAXIDMAC_IRQ_DST_SLV_ERR	= BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) 	DWAXIDMAC_IRQ_LLI_RD_DEC_ERR	= BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 	DWAXIDMAC_IRQ_LLI_WR_DEC_ERR	= BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) 	DWAXIDMAC_IRQ_LLI_RD_SLV_ERR	= BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 	DWAXIDMAC_IRQ_LLI_WR_SLV_ERR	= BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) 	DWAXIDMAC_IRQ_INVALID_ERR	= BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 	DWAXIDMAC_IRQ_MULTIBLKTYPE_ERR	= BIT(14),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 	DWAXIDMAC_IRQ_DEC_ERR		= BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) 	DWAXIDMAC_IRQ_WR2RO_ERR		= BIT(17),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 	DWAXIDMAC_IRQ_RD2RWO_ERR	= BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) 	DWAXIDMAC_IRQ_WRONCHEN_ERR	= BIT(19),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) 	DWAXIDMAC_IRQ_SHADOWREG_ERR	= BIT(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) 	DWAXIDMAC_IRQ_WRONHOLD_ERR	= BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) 	DWAXIDMAC_IRQ_LOCK_CLEARED	= BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 	DWAXIDMAC_IRQ_SRC_SUSPENDED	= BIT(28),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) 	DWAXIDMAC_IRQ_SUSPENDED		= BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) 	DWAXIDMAC_IRQ_DISABLED		= BIT(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 	DWAXIDMAC_IRQ_ABORTED		= BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) 	DWAXIDMAC_IRQ_ALL_ERR		= (GENMASK(21, 16) | GENMASK(14, 5)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) 	DWAXIDMAC_IRQ_ALL		= GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) enum {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) 	DWAXIDMAC_TRANS_WIDTH_8		= 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 	DWAXIDMAC_TRANS_WIDTH_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) 	DWAXIDMAC_TRANS_WIDTH_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) 	DWAXIDMAC_TRANS_WIDTH_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) 	DWAXIDMAC_TRANS_WIDTH_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) 	DWAXIDMAC_TRANS_WIDTH_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) 	DWAXIDMAC_TRANS_WIDTH_512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) 	DWAXIDMAC_TRANS_WIDTH_MAX	= DWAXIDMAC_TRANS_WIDTH_512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #endif /* _AXI_DMA_PLATFORM_H */