^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * driver/dma/coh901318_lli.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2009 ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Support functions for handling lli for dma
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Per Friden <per.friden@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/memory.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/gfp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include "coh901318.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #if (defined(CONFIG_DEBUG_FS) && defined(CONFIG_U300_DEBUG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DEBUGFS_POOL_COUNTER_RESET(pool) (pool->debugfs_pool_counter = 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DEBUGFS_POOL_COUNTER_ADD(pool, add) (pool->debugfs_pool_counter += add)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DEBUGFS_POOL_COUNTER_RESET(pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DEBUGFS_POOL_COUNTER_ADD(pool, add)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) static struct coh901318_lli *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) coh901318_lli_next(struct coh901318_lli *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) if (data == NULL || data->link_addr == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) return (struct coh901318_lli *) data->virt_link_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) int coh901318_pool_create(struct coh901318_pool *pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) size_t size, size_t align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) spin_lock_init(&pool->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) pool->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) pool->dmapool = dma_pool_create("lli_pool", dev, size, align, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) DEBUGFS_POOL_COUNTER_RESET(pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int coh901318_pool_destroy(struct coh901318_pool *pool)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) dma_pool_destroy(pool->dmapool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct coh901318_lli *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) coh901318_lli_alloc(struct coh901318_pool *pool, unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct coh901318_lli *head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) struct coh901318_lli *lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct coh901318_lli *lli_prev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) dma_addr_t phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) if (len == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) spin_lock(&pool->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) head = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) if (head == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) DEBUGFS_POOL_COUNTER_ADD(pool, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) lli = head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) lli->phy_this = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) lli->link_addr = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) lli->virt_link_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) for (i = 1; i < len; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) lli_prev = lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) lli = dma_pool_alloc(pool->dmapool, GFP_NOWAIT, &phy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) if (lli == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) goto err_clean_up;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) DEBUGFS_POOL_COUNTER_ADD(pool, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) lli->phy_this = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) lli->link_addr = 0x00000000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) lli->virt_link_addr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) lli_prev->link_addr = phy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) lli_prev->virt_link_addr = lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) spin_unlock(&pool->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) spin_unlock(&pool->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) err_clean_up:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) lli_prev->link_addr = 0x00000000U;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) spin_unlock(&pool->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) coh901318_lli_free(pool, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void coh901318_lli_free(struct coh901318_pool *pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) struct coh901318_lli **lli)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct coh901318_lli *l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct coh901318_lli *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) if (lli == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) l = *lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (l == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) spin_lock(&pool->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) while (l->link_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) next = l->virt_link_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dma_pool_free(pool->dmapool, l, l->phy_this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) DEBUGFS_POOL_COUNTER_ADD(pool, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) l = next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dma_pool_free(pool->dmapool, l, l->phy_this);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) DEBUGFS_POOL_COUNTER_ADD(pool, -1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) spin_unlock(&pool->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) *lli = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) coh901318_lli_fill_memcpy(struct coh901318_pool *pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct coh901318_lli *lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dma_addr_t source, unsigned int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) dma_addr_t destination, u32 ctrl_chained,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) u32 ctrl_eom)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) int s = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) dma_addr_t src = source;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) dma_addr_t dst = destination;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) lli->src_addr = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) lli->dst_addr = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) while (lli->link_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) lli->src_addr = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) lli->dst_addr = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) s -= MAX_DMA_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) lli = coh901318_lli_next(lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) src += MAX_DMA_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) dst += MAX_DMA_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) lli->control = ctrl_eom | s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) lli->src_addr = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) lli->dst_addr = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) coh901318_lli_fill_single(struct coh901318_pool *pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) struct coh901318_lli *lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) dma_addr_t buf, unsigned int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_eom,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) enum dma_transfer_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) int s = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) dma_addr_t src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dma_addr_t dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (dir == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) src = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) dst = dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) } else if (dir == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) src = dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) dst = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) while (lli->link_addr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) size_t block_size = MAX_DMA_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) lli->control = ctrl_chained | MAX_DMA_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* If we are on the next-to-final block and there will
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * be less than half a DMA packet left for the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * block, then we want to make this block a little
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * smaller to balance the sizes. This is meant to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * avoid too small transfers if the buffer size is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * (MAX_DMA_PACKET_SIZE*N + 1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) if (s < (MAX_DMA_PACKET_SIZE + MAX_DMA_PACKET_SIZE/2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) block_size = MAX_DMA_PACKET_SIZE/2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) s -= block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) lli->src_addr = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) lli->dst_addr = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) lli = coh901318_lli_next(lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) if (dir == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) src += block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) else if (dir == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) dst += block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) lli->control = ctrl_eom | s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) lli->src_addr = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) lli->dst_addr = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) coh901318_lli_fill_sg(struct coh901318_pool *pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct coh901318_lli *lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct scatterlist *sgl, unsigned int nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) u32 ctrl_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) enum dma_transfer_direction dir, u32 ctrl_irq_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) u32 ctrl_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dma_addr_t src = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) dma_addr_t dst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 bytes_to_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 elem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) if (lli == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) spin_lock(&pool->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) if (dir == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) dst = dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) else if (dir == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) src = dev_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) for_each_sg(sgl, sg, nents, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (sg_is_chain(sg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* sg continues to the next sg-element don't
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * send ctrl_finish until the last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * sg-element in the chain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ctrl_sg = ctrl_chained;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } else if (i == nents - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) ctrl_sg = ctrl_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) ctrl_sg = ctrl ? ctrl : ctrl_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) if (dir == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) /* increment source address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) src = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* increment destination address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) dst = sg_dma_address(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) bytes_to_transfer = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) while (bytes_to_transfer) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) if (bytes_to_transfer > MAX_DMA_PACKET_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) elem_size = MAX_DMA_PACKET_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) val = ctrl_chained;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) elem_size = bytes_to_transfer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) val = ctrl_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) lli->control = val | elem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) lli->src_addr = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) lli->dst_addr = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) if (dir == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dst += elem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) src += elem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) BUG_ON(lli->link_addr & 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) bytes_to_transfer -= elem_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) lli = coh901318_lli_next(lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) spin_unlock(&pool->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) spin_unlock(&pool->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags