^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2007-2013 ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * DMA driver for COH 901 318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Per Friden <per.friden@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef COH901318_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define COH901318_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define MAX_DMA_PACKET_SIZE_SHIFT 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define MAX_DMA_PACKET_SIZE (1 << MAX_DMA_PACKET_SIZE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) struct device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) struct coh901318_pool {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct dma_pool *dmapool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) int debugfs_pool_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * struct coh901318_lli - linked list item for DMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @control: control settings for DMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @src_addr: transfer source address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @dst_addr: transfer destination address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @link_addr: physical address to next lli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @virt_link_addr: virtual address of next lli (only used by pool_free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * @phy_this: physical address of current lli (only used by pool_free)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) struct coh901318_lli {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) dma_addr_t src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) dma_addr_t dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) dma_addr_t link_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) void *virt_link_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) dma_addr_t phy_this;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * coh901318_pool_create() - Creates an dma pool for lli:s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @pool: pool handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @dev: dma device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @lli_nbr: number of lli:s in the pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @algin: address alignemtn of lli:s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * returns 0 on success otherwise none zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) int coh901318_pool_create(struct coh901318_pool *pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) size_t lli_nbr, size_t align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * coh901318_pool_destroy() - Destroys the dma pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @pool: pool handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * returns 0 on success otherwise none zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int coh901318_pool_destroy(struct coh901318_pool *pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * coh901318_lli_alloc() - Allocates a linked list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @pool: pool handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) * @len: length to list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * return: none NULL if success otherwise NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct coh901318_lli *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) coh901318_lli_alloc(struct coh901318_pool *pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) unsigned int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * coh901318_lli_free() - Returns the linked list items to the pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @pool: pool handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @lli: reference to lli pointer to be freed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) void coh901318_lli_free(struct coh901318_pool *pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct coh901318_lli **lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * coh901318_lli_fill_memcpy() - Prepares the lli:s for dma memcpy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @pool: pool handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @lli: allocated lli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @src: src address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @size: transfer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @dst: destination address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @ctrl_chained: ctrl for chained lli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @ctrl_last: ctrl for the last lli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * returns number of CPU interrupts for the lli, negative on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) coh901318_lli_fill_memcpy(struct coh901318_pool *pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) struct coh901318_lli *lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) dma_addr_t src, unsigned int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) dma_addr_t dst, u32 ctrl_chained, u32 ctrl_last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * coh901318_lli_fill_single() - Prepares the lli:s for dma single transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @pool: pool handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @lli: allocated lli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @buf: transfer buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @size: transfer size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @dev_addr: address of periphal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @ctrl_chained: ctrl for chained lli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @ctrl_last: ctrl for the last lli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @dir: direction of transfer (to or from device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * returns number of CPU interrupts for the lli, negative on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) coh901318_lli_fill_single(struct coh901318_pool *pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct coh901318_lli *lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) dma_addr_t buf, unsigned int size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) dma_addr_t dev_addr, u32 ctrl_chained, u32 ctrl_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) enum dma_transfer_direction dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * coh901318_lli_fill_single() - Prepares the lli:s for dma scatter list transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @pool: pool handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @lli: allocated lli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @sg: scatter gather list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @nents: number of entries in sg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @dev_addr: address of periphal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @ctrl_chained: ctrl for chained lli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @ctrl: ctrl of middle lli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @ctrl_last: ctrl for the last lli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @dir: direction of transfer (to or from device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @ctrl_irq_mask: ctrl mask for CPU interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * returns number of CPU interrupts for the lli, negative on error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) coh901318_lli_fill_sg(struct coh901318_pool *pool,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) struct coh901318_lli *lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct scatterlist *sg, unsigned int nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) dma_addr_t dev_addr, u32 ctrl_chained,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 ctrl, u32 ctrl_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) enum dma_transfer_direction dir, u32 ctrl_irq_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #endif /* COH901318_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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