^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * driver/dma/coh901318.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007-2009 ST-Ericsson
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * DMA driver for COH 901 318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Per Friden <per.friden@stericsson.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h> /* printk() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/fs.h> /* everything... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/slab.h> /* kmalloc() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_data/dma-coh901318.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include "coh901318.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include "dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define COH901318_MOD32_MASK (0x1F)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define COH901318_WORD_MASK (0xFFFFFFFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* INT_STATUS - Interrupt Status Registers 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define COH901318_INT_STATUS1 (0x0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define COH901318_INT_STATUS2 (0x0004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* TC_INT_STATUS - Terminal Count Interrupt Status Registers 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define COH901318_TC_INT_STATUS1 (0x0008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define COH901318_TC_INT_STATUS2 (0x000C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* TC_INT_CLEAR - Terminal Count Interrupt Clear Registers 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define COH901318_TC_INT_CLEAR1 (0x0010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define COH901318_TC_INT_CLEAR2 (0x0014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* RAW_TC_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define COH901318_RAW_TC_INT_STATUS1 (0x0018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define COH901318_RAW_TC_INT_STATUS2 (0x001C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) /* BE_INT_STATUS - Bus Error Interrupt Status Registers 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define COH901318_BE_INT_STATUS1 (0x0020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define COH901318_BE_INT_STATUS2 (0x0024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) /* BE_INT_CLEAR - Bus Error Interrupt Clear Registers 32bit (-/W) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define COH901318_BE_INT_CLEAR1 (0x0028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define COH901318_BE_INT_CLEAR2 (0x002C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* RAW_BE_INT_STATUS - Raw Term Count Interrupt Status Registers 32bit (R/-) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define COH901318_RAW_BE_INT_STATUS1 (0x0030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define COH901318_RAW_BE_INT_STATUS2 (0x0034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * CX_CFG - Channel Configuration Registers 32bit (R/W)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define COH901318_CX_CFG (0x0100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define COH901318_CX_CFG_SPACING (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) /* Channel enable activates tha dma job */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define COH901318_CX_CFG_CH_ENABLE (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define COH901318_CX_CFG_CH_DISABLE (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* Request Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define COH901318_CX_CFG_RM_MASK (0x00000006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define COH901318_CX_CFG_RM_MEMORY_TO_MEMORY (0x0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY (0x1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define COH901318_CX_CFG_RM_PRIMARY_TO_SECONDARY (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define COH901318_CX_CFG_RM_SECONDARY_TO_PRIMARY (0x3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) /* Linked channel request field. RM must == 11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define COH901318_CX_CFG_LCRF_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define COH901318_CX_CFG_LCRF_MASK (0x000001F8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define COH901318_CX_CFG_LCR_DISABLE (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* Terminal Counter Interrupt Request Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define COH901318_CX_CFG_TC_IRQ_ENABLE (0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define COH901318_CX_CFG_TC_IRQ_DISABLE (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) /* Bus Error interrupt Mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define COH901318_CX_CFG_BE_IRQ_ENABLE (0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define COH901318_CX_CFG_BE_IRQ_DISABLE (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * CX_STAT - Channel Status Registers 32bit (R/-)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define COH901318_CX_STAT (0x0200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define COH901318_CX_STAT_SPACING (0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define COH901318_CX_STAT_RBE_IRQ_IND (0x00000008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define COH901318_CX_STAT_RTC_IRQ_IND (0x00000004)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define COH901318_CX_STAT_ACTIVE (0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define COH901318_CX_STAT_ENABLED (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * CX_CTRL - Channel Control Registers 32bit (R/W)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define COH901318_CX_CTRL (0x0400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define COH901318_CX_CTRL_SPACING (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* Transfer Count Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define COH901318_CX_CTRL_TC_ENABLE (0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define COH901318_CX_CTRL_TC_DISABLE (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* Transfer Count Value 0 - 4095 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define COH901318_CX_CTRL_TC_VALUE_MASK (0x00000FFF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* Burst count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define COH901318_CX_CTRL_BURST_COUNT_MASK (0x0000E000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define COH901318_CX_CTRL_BURST_COUNT_64_BYTES (0x7 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define COH901318_CX_CTRL_BURST_COUNT_48_BYTES (0x6 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define COH901318_CX_CTRL_BURST_COUNT_32_BYTES (0x5 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define COH901318_CX_CTRL_BURST_COUNT_16_BYTES (0x4 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define COH901318_CX_CTRL_BURST_COUNT_8_BYTES (0x3 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define COH901318_CX_CTRL_BURST_COUNT_4_BYTES (0x2 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define COH901318_CX_CTRL_BURST_COUNT_2_BYTES (0x1 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define COH901318_CX_CTRL_BURST_COUNT_1_BYTE (0x0 << 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* Source bus size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define COH901318_CX_CTRL_SRC_BUS_SIZE_MASK (0x00030000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS (0x2 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS (0x1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS (0x0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* Source address increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE (0x00040000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Destination Bus Size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define COH901318_CX_CTRL_DST_BUS_SIZE_MASK (0x00180000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS (0x2 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS (0x1 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS (0x0 << 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Destination address increment */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define COH901318_CX_CTRL_DST_ADDR_INC_ENABLE (0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define COH901318_CX_CTRL_DST_ADDR_INC_DISABLE (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Master Mode (Master2 is only connected to MSL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define COH901318_CX_CTRL_MASTER_MODE_MASK (0x00C00000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define COH901318_CX_CTRL_MASTER_MODE_M2R_M1W (0x3 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define COH901318_CX_CTRL_MASTER_MODE_M1R_M2W (0x2 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define COH901318_CX_CTRL_MASTER_MODE_M2RW (0x1 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define COH901318_CX_CTRL_MASTER_MODE_M1RW (0x0 << 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Terminal Count flag to PER enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define COH901318_CX_CTRL_TCP_ENABLE (0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define COH901318_CX_CTRL_TCP_DISABLE (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* Terminal Count flags to CPU enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define COH901318_CX_CTRL_TC_IRQ_ENABLE (0x02000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define COH901318_CX_CTRL_TC_IRQ_DISABLE (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* Hand shake to peripheral */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define COH901318_CX_CTRL_HSP_ENABLE (0x04000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define COH901318_CX_CTRL_HSP_DISABLE (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define COH901318_CX_CTRL_HSS_ENABLE (0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define COH901318_CX_CTRL_HSS_DISABLE (0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define COH901318_CX_CTRL_DDMA_MASK (0x30000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define COH901318_CX_CTRL_DDMA_LEGACY (0x0 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define COH901318_CX_CTRL_DDMA_DEMAND_DMA1 (0x1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define COH901318_CX_CTRL_DDMA_DEMAND_DMA2 (0x2 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) /* Primary Request Data Destination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define COH901318_CX_CTRL_PRDD_MASK (0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define COH901318_CX_CTRL_PRDD_DEST (0x1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define COH901318_CX_CTRL_PRDD_SOURCE (0x0 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * CX_SRC_ADDR - Channel Source Address Registers 32bit (R/W)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define COH901318_CX_SRC_ADDR (0x0404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define COH901318_CX_SRC_ADDR_SPACING (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * CX_DST_ADDR - Channel Destination Address Registers 32bit R/W
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define COH901318_CX_DST_ADDR (0x0408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define COH901318_CX_DST_ADDR_SPACING (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * CX_LNK_ADDR - Channel Link Address Registers 32bit (R/W)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define COH901318_CX_LNK_ADDR (0x040C)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define COH901318_CX_LNK_ADDR_SPACING (0x10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define COH901318_CX_LNK_LINK_IMMEDIATE (0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * struct coh901318_params - parameters for DMAC configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @config: DMA config register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @ctrl_lli_last: DMA control register for the last lli in the list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @ctrl_lli: DMA control register for an lli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @ctrl_lli_chained: DMA control register for a chained lli
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct coh901318_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) u32 ctrl_lli_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) u32 ctrl_lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) u32 ctrl_lli_chained;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * struct coh_dma_channel - dma channel base
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @name: ascii name of dma channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @number: channel id number
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @desc_nbr_max: number of preallocated descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @priority_high: prio of channel, 0 low otherwise high.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @param: configuration parameters
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) struct coh_dma_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) const char name[32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) const int number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) const int desc_nbr_max;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) const int priority_high;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) const struct coh901318_params param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * struct powersave - DMA power save structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @lock: lock protecting data in this struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @started_channels: bit mask indicating active dma channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) struct powersave {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u64 started_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* points out all dma slave channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * Syntax is [A1, B1, A2, B2, .... ,-1,-1]
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * Select all channels from A to B, end of list is marked with -1,-1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static int dma_slave_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) U300_DMA_MSL_TX_0, U300_DMA_SPI_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) U300_DMA_UART1_TX, U300_DMA_UART1_RX, -1, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) /* points out all dma memcpy channels. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static int dma_memcpy_channels[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) U300_DMA_GENERAL_PURPOSE_0, U300_DMA_GENERAL_PURPOSE_8, -1, -1};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define flags_memcpy_config (COH901318_CX_CFG_CH_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) COH901318_CX_CFG_RM_MEMORY_TO_MEMORY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) COH901318_CX_CFG_LCR_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) COH901318_CX_CFG_TC_IRQ_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) COH901318_CX_CFG_BE_IRQ_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define flags_memcpy_lli_chained (COH901318_CX_CTRL_TC_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) COH901318_CX_CTRL_MASTER_MODE_M1RW | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) COH901318_CX_CTRL_TCP_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) COH901318_CX_CTRL_TC_IRQ_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) COH901318_CX_CTRL_HSP_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) COH901318_CX_CTRL_HSS_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) COH901318_CX_CTRL_DDMA_LEGACY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) COH901318_CX_CTRL_PRDD_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define flags_memcpy_lli (COH901318_CX_CTRL_TC_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) COH901318_CX_CTRL_MASTER_MODE_M1RW | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) COH901318_CX_CTRL_TCP_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) COH901318_CX_CTRL_TC_IRQ_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) COH901318_CX_CTRL_HSP_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) COH901318_CX_CTRL_HSS_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) COH901318_CX_CTRL_DDMA_LEGACY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) COH901318_CX_CTRL_PRDD_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define flags_memcpy_lli_last (COH901318_CX_CTRL_TC_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) COH901318_CX_CTRL_BURST_COUNT_32_BYTES | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) COH901318_CX_CTRL_MASTER_MODE_M1RW | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) COH901318_CX_CTRL_TCP_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) COH901318_CX_CTRL_TC_IRQ_ENABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) COH901318_CX_CTRL_HSP_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) COH901318_CX_CTRL_HSS_DISABLE | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) COH901318_CX_CTRL_DDMA_LEGACY | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) COH901318_CX_CTRL_PRDD_SOURCE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static const struct coh_dma_channel chan_config[U300_DMA_CHANNELS] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .number = U300_DMA_MSL_TX_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .name = "MSL TX 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .number = U300_DMA_MSL_TX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .name = "MSL TX 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) .number = U300_DMA_MSL_TX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) .name = "MSL TX 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) .desc_nbr_max = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) .number = U300_DMA_MSL_TX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) .name = "MSL TX 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) .number = U300_DMA_MSL_TX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) .name = "MSL TX 4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) COH901318_CX_CTRL_MASTER_MODE_M1R_M2W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) .number = U300_DMA_MSL_TX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) .name = "MSL TX 5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) .number = U300_DMA_MSL_TX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) .name = "MSL TX 6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .number = U300_DMA_MSL_RX_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .name = "MSL RX 0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) .number = U300_DMA_MSL_RX_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) .name = "MSL RX 1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) .param.ctrl_lli = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) .number = U300_DMA_MSL_RX_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) .name = "MSL RX 2",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) .number = U300_DMA_MSL_RX_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) .name = "MSL RX 3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) .number = U300_DMA_MSL_RX_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) .name = "MSL RX 4",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .number = U300_DMA_MSL_RX_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .name = "MSL RX 5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) COH901318_CX_CTRL_BURST_COUNT_32_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) COH901318_CX_CTRL_MASTER_MODE_M2R_M1W |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) COH901318_CX_CTRL_DDMA_DEMAND_DMA1 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .number = U300_DMA_MSL_RX_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .name = "MSL RX 6",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * Don't set up device address, burst count or size of src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) * or dst bus for this peripheral - handled by PrimeCell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) * DMA extension.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .number = U300_DMA_MMCSD_RX_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .name = "MMCSD RX TX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .number = U300_DMA_MSPRO_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .name = "MSPRO TX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .number = U300_DMA_MSPRO_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .name = "MSPRO RX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) * Don't set up device address, burst count or size of src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) * or dst bus for this peripheral - handled by PrimeCell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) * DMA extension.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .number = U300_DMA_UART0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .name = "UART0 TX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .number = U300_DMA_UART0_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .name = "UART0 RX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) .number = U300_DMA_APEX_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) .name = "APEX TX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) .number = U300_DMA_APEX_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) .name = "APEX RX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) .number = U300_DMA_PCM_I2S0_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) .name = "PCM I2S0 TX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) .priority_high = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) .number = U300_DMA_PCM_I2S0_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) .name = "PCM I2S0 RX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) .priority_high = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) .number = U300_DMA_PCM_I2S1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) .name = "PCM I2S1 TX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) .priority_high = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) COH901318_CX_CTRL_DST_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) COH901318_CX_CTRL_PRDD_SOURCE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) .number = U300_DMA_PCM_I2S1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) .name = "PCM I2S1 RX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) .priority_high = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) COH901318_CX_CTRL_BURST_COUNT_16_BYTES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) COH901318_CX_CTRL_SRC_ADDR_INC_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) COH901318_CX_CTRL_TCP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) COH901318_CX_CTRL_DDMA_LEGACY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) COH901318_CX_CTRL_PRDD_DEST,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) .number = U300_DMA_XGAM_CDI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) .name = "XGAM CDI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) .number = U300_DMA_XGAM_PDI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) .name = "XGAM PDI",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) * Don't set up device address, burst count or size of src
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) * or dst bus for this peripheral - handled by PrimeCell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) * DMA extension.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) .number = U300_DMA_SPI_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) .name = "SPI TX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) .number = U300_DMA_SPI_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) .name = "SPI RX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) .param.config = COH901318_CX_CFG_CH_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) COH901318_CX_CFG_LCR_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) COH901318_CX_CFG_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) COH901318_CX_CFG_BE_IRQ_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) .param.ctrl_lli_chained = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) COH901318_CX_CTRL_TC_IRQ_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .param.ctrl_lli = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) .param.ctrl_lli_last = 0 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) COH901318_CX_CTRL_TC_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) COH901318_CX_CTRL_MASTER_MODE_M1RW |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) COH901318_CX_CTRL_TCP_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) COH901318_CX_CTRL_TC_IRQ_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) COH901318_CX_CTRL_HSP_ENABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) COH901318_CX_CTRL_HSS_DISABLE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) COH901318_CX_CTRL_DDMA_LEGACY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) .number = U300_DMA_GENERAL_PURPOSE_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) .name = "GENERAL 00",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) .param.config = flags_memcpy_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) .param.ctrl_lli_chained = flags_memcpy_lli_chained,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) .param.ctrl_lli = flags_memcpy_lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) .param.ctrl_lli_last = flags_memcpy_lli_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) .number = U300_DMA_GENERAL_PURPOSE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) .name = "GENERAL 01",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) .param.config = flags_memcpy_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) .param.ctrl_lli_chained = flags_memcpy_lli_chained,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) .param.ctrl_lli = flags_memcpy_lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) .param.ctrl_lli_last = flags_memcpy_lli_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) .number = U300_DMA_GENERAL_PURPOSE_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) .name = "GENERAL 02",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .param.config = flags_memcpy_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .param.ctrl_lli_chained = flags_memcpy_lli_chained,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .param.ctrl_lli = flags_memcpy_lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .param.ctrl_lli_last = flags_memcpy_lli_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) .number = U300_DMA_GENERAL_PURPOSE_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .name = "GENERAL 03",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .param.config = flags_memcpy_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .param.ctrl_lli_chained = flags_memcpy_lli_chained,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .param.ctrl_lli = flags_memcpy_lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .param.ctrl_lli_last = flags_memcpy_lli_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .number = U300_DMA_GENERAL_PURPOSE_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .name = "GENERAL 04",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .param.config = flags_memcpy_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .param.ctrl_lli_chained = flags_memcpy_lli_chained,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .param.ctrl_lli = flags_memcpy_lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) .param.ctrl_lli_last = flags_memcpy_lli_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .number = U300_DMA_GENERAL_PURPOSE_5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .name = "GENERAL 05",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .param.config = flags_memcpy_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .param.ctrl_lli_chained = flags_memcpy_lli_chained,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) .param.ctrl_lli = flags_memcpy_lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) .param.ctrl_lli_last = flags_memcpy_lli_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) .number = U300_DMA_GENERAL_PURPOSE_6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .name = "GENERAL 06",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .param.config = flags_memcpy_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .param.ctrl_lli_chained = flags_memcpy_lli_chained,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .param.ctrl_lli = flags_memcpy_lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .param.ctrl_lli_last = flags_memcpy_lli_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .number = U300_DMA_GENERAL_PURPOSE_7,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .name = "GENERAL 07",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .param.config = flags_memcpy_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) .param.ctrl_lli_chained = flags_memcpy_lli_chained,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .param.ctrl_lli = flags_memcpy_lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .param.ctrl_lli_last = flags_memcpy_lli_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .number = U300_DMA_GENERAL_PURPOSE_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) .name = "GENERAL 08",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) .param.config = flags_memcpy_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) .param.ctrl_lli_chained = flags_memcpy_lli_chained,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) .param.ctrl_lli = flags_memcpy_lli,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .param.ctrl_lli_last = flags_memcpy_lli_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .number = U300_DMA_UART1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .name = "UART1 TX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .number = U300_DMA_UART1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .name = "UART1 RX",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .priority_high = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) #define COHC_2_DEV(cohc) (&cohc->chan.dev->device)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) #ifdef VERBOSE_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) #define COH_DBG(x) ({ if (1) x; 0; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) #define COH_DBG(x) ({ if (0) x; 0; })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) struct coh901318_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) struct dma_async_tx_descriptor desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) unsigned int sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) struct coh901318_lli *lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) enum dma_transfer_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) u32 head_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) u32 head_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) struct coh901318_base {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) void __iomem *virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) struct coh901318_pool pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) struct powersave pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) struct dma_device dma_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) struct dma_device dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) struct coh901318_chan *chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) struct coh901318_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) int allocated;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) int stopped;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) struct work_struct free_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) struct dma_chan chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) struct tasklet_struct tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct list_head active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct list_head queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct list_head free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) unsigned long nbr_active_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) unsigned long busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) struct dma_slave_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) u32 addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) u32 ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) struct coh901318_base *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) static void coh901318_list_print(struct coh901318_chan *cohc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) struct coh901318_lli *lli)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct coh901318_lli *l = lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) while (l) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) dev_vdbg(COHC_2_DEV(cohc), "i %d, lli %p, ctrl 0x%x, src %pad"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) ", dst %pad, link %pad virt_link_addr 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) i, l, l->control, &l->src_addr, &l->dst_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) &l->link_addr, l->virt_link_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) l = l->virt_link_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) #define COH901318_DEBUGFS_ASSIGN(x, y) (x = y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static struct coh901318_base *debugfs_dma_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static struct dentry *dma_dentry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) static ssize_t coh901318_debugfs_read(struct file *file, char __user *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) size_t count, loff_t *f_pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) u64 started_channels = debugfs_dma_base->pm.started_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) int pool_count = debugfs_dma_base->pool.debugfs_pool_counter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) char *dev_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) char *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) dev_buf = kmalloc(4*1024, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) if (dev_buf == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) tmp = dev_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) tmp += sprintf(tmp, "DMA -- enabled dma channels\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) for (i = 0; i < U300_DMA_CHANNELS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (started_channels & (1ULL << i))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) tmp += sprintf(tmp, "channel %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) tmp += sprintf(tmp, "Pool alloc nbr %d\n", pool_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) ret = simple_read_from_buffer(buf, count, f_pos, dev_buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) tmp - dev_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) kfree(dev_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) static const struct file_operations coh901318_debugfs_status_operations = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) .open = simple_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) .read = coh901318_debugfs_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) .llseek = default_llseek,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) static int __init init_coh901318_debugfs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) dma_dentry = debugfs_create_dir("dma", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) debugfs_create_file("status", S_IFREG | S_IRUGO, dma_dentry, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) &coh901318_debugfs_status_operations);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) static void __exit exit_coh901318_debugfs(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) debugfs_remove_recursive(dma_dentry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) module_init(init_coh901318_debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) module_exit(exit_coh901318_debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) #define COH901318_DEBUGFS_ASSIGN(x, y)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) #endif /* CONFIG_DEBUG_FS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static inline struct coh901318_chan *to_coh901318_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return container_of(chan, struct coh901318_chan, chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) struct dma_slave_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) enum dma_transfer_direction direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) static inline const struct coh901318_params *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) cohc_chan_param(struct coh901318_chan *cohc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) return &chan_config[cohc->id].param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) static inline const struct coh_dma_channel *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) cohc_chan_conf(struct coh901318_chan *cohc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) return &chan_config[cohc->id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) static void enable_powersave(struct coh901318_chan *cohc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) struct powersave *pm = &cohc->base->pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) spin_lock_irqsave(&pm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) pm->started_channels &= ~(1ULL << cohc->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) spin_unlock_irqrestore(&pm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static void disable_powersave(struct coh901318_chan *cohc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct powersave *pm = &cohc->base->pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) spin_lock_irqsave(&pm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) pm->started_channels |= (1ULL << cohc->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) spin_unlock_irqrestore(&pm->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) static inline int coh901318_set_ctrl(struct coh901318_chan *cohc, u32 control)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) int channel = cohc->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) void __iomem *virtbase = cohc->base->virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) writel(control,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) virtbase + COH901318_CX_CTRL +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) COH901318_CX_CTRL_SPACING * channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) static inline int coh901318_set_conf(struct coh901318_chan *cohc, u32 conf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) int channel = cohc->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) void __iomem *virtbase = cohc->base->virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) writel(conf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) virtbase + COH901318_CX_CFG +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) COH901318_CX_CFG_SPACING*channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) static int coh901318_start(struct coh901318_chan *cohc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) int channel = cohc->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) void __iomem *virtbase = cohc->base->virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) disable_powersave(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) val = readl(virtbase + COH901318_CX_CFG +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) COH901318_CX_CFG_SPACING * channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) /* Enable channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) val |= COH901318_CX_CFG_CH_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) writel(val, virtbase + COH901318_CX_CFG +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) COH901318_CX_CFG_SPACING * channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) static int coh901318_prep_linked_list(struct coh901318_chan *cohc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) struct coh901318_lli *lli)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) int channel = cohc->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) void __iomem *virtbase = cohc->base->virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) BUG_ON(readl(virtbase + COH901318_CX_STAT +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) COH901318_CX_STAT_SPACING*channel) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) COH901318_CX_STAT_ACTIVE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) writel(lli->src_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) virtbase + COH901318_CX_SRC_ADDR +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) COH901318_CX_SRC_ADDR_SPACING * channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) writel(lli->dst_addr, virtbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) COH901318_CX_DST_ADDR +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) COH901318_CX_DST_ADDR_SPACING * channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) COH901318_CX_LNK_ADDR_SPACING * channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) writel(lli->control, virtbase + COH901318_CX_CTRL +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) COH901318_CX_CTRL_SPACING * channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) static struct coh901318_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) coh901318_desc_get(struct coh901318_chan *cohc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) struct coh901318_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) if (list_empty(&cohc->free)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) /* alloc new desc because we're out of used ones
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) * TODO: alloc a pile of descs instead of just one,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) * avoid many small allocations.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) desc = kzalloc(sizeof(struct coh901318_desc), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) if (desc == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) INIT_LIST_HEAD(&desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) dma_async_tx_descriptor_init(&desc->desc, &cohc->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) /* Reuse an old desc. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) desc = list_first_entry(&cohc->free,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) struct coh901318_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) list_del(&desc->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) /* Initialize it a bit so it's not insane */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) desc->sg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) desc->sg_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) desc->desc.callback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) desc->desc.callback_param = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) return desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) coh901318_desc_free(struct coh901318_chan *cohc, struct coh901318_desc *cohd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) list_add_tail(&cohd->node, &cohc->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) /* call with irq lock held */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) coh901318_desc_submit(struct coh901318_chan *cohc, struct coh901318_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) list_add_tail(&desc->node, &cohc->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) static struct coh901318_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) coh901318_first_active_get(struct coh901318_chan *cohc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) return list_first_entry_or_null(&cohc->active, struct coh901318_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) coh901318_desc_remove(struct coh901318_desc *cohd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) list_del(&cohd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) coh901318_desc_queue(struct coh901318_chan *cohc, struct coh901318_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) list_add_tail(&desc->node, &cohc->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) static struct coh901318_desc *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) coh901318_first_queued(struct coh901318_chan *cohc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) return list_first_entry_or_null(&cohc->queue, struct coh901318_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) static inline u32 coh901318_get_bytes_in_lli(struct coh901318_lli *in_lli)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) struct coh901318_lli *lli = in_lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) u32 bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) while (lli) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) bytes += lli->control & COH901318_CX_CTRL_TC_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) lli = lli->virt_link_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) return bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) * Get the number of bytes left to transfer on this channel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) * it is unwise to call this before stopping the channel for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) * absolute measures, but for a rough guess you can still call
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) * it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) static u32 coh901318_get_bytes_left(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) struct coh901318_chan *cohc = to_coh901318_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) struct coh901318_desc *cohd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) struct list_head *pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) u32 left = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) spin_lock_irqsave(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) * If there are many queued jobs, we iterate and add the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) * size of them all. We take a special look on the first
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) * job though, since it is probably active.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) list_for_each(pos, &cohc->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) * The first job in the list will be working on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) * hardware. The job can be stopped but still active,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) * so that the transfer counter is somewhere inside
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) * the buffer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) cohd = list_entry(pos, struct coh901318_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (i == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) struct coh901318_lli *lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) dma_addr_t ladd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) /* Read current transfer count value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) left = readl(cohc->base->virtbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) COH901318_CX_CTRL +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) COH901318_CX_CTRL_SPACING * cohc->id) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) COH901318_CX_CTRL_TC_VALUE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) /* See if the transfer is linked... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) ladd = readl(cohc->base->virtbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) COH901318_CX_LNK_ADDR +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) COH901318_CX_LNK_ADDR_SPACING *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) cohc->id) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) ~COH901318_CX_LNK_LINK_IMMEDIATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) /* Single transaction */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) if (!ladd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * Linked transaction, follow the lli, find the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * currently processing lli, and proceed to the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) lli = cohd->lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) while (lli && lli->link_addr != ladd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) lli = lli->virt_link_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) if (lli)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) lli = lli->virt_link_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) * Follow remaining lli links around to count the total
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) * number of bytes left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) left += coh901318_get_bytes_in_lli(lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) left += coh901318_get_bytes_in_lli(cohd->lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) /* Also count bytes in the queued jobs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) list_for_each(pos, &cohc->queue) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) cohd = list_entry(pos, struct coh901318_desc, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) left += coh901318_get_bytes_in_lli(cohd->lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) spin_unlock_irqrestore(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) return left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) * Pauses a transfer without losing data. Enables power save.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) * Use this function in conjunction with coh901318_resume.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static int coh901318_pause(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) struct coh901318_chan *cohc = to_coh901318_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) int channel = cohc->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) void __iomem *virtbase = cohc->base->virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) spin_lock_irqsave(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) /* Disable channel in HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) val = readl(virtbase + COH901318_CX_CFG +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) COH901318_CX_CFG_SPACING * channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) /* Stopping infinite transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) if ((val & COH901318_CX_CTRL_TC_ENABLE) == 0 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) (val & COH901318_CX_CFG_CH_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) cohc->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) val &= ~COH901318_CX_CFG_CH_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) /* Enable twice, HW bug work around */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) writel(val, virtbase + COH901318_CX_CFG +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) COH901318_CX_CFG_SPACING * channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) writel(val, virtbase + COH901318_CX_CFG +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) COH901318_CX_CFG_SPACING * channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) /* Spin-wait for it to actually go inactive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) channel) & COH901318_CX_STAT_ACTIVE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) /* Check if we stopped an active job */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) channel) & COH901318_CX_CTRL_TC_VALUE_MASK) > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) cohc->stopped = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) enable_powersave(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) spin_unlock_irqrestore(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) /* Resumes a transfer that has been stopped via 300_dma_stop(..).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) Power save is handled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) static int coh901318_resume(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) struct coh901318_chan *cohc = to_coh901318_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) int channel = cohc->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) spin_lock_irqsave(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) disable_powersave(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (cohc->stopped) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) /* Enable channel in HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) val = readl(cohc->base->virtbase + COH901318_CX_CFG +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) COH901318_CX_CFG_SPACING * channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) val |= COH901318_CX_CFG_CH_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) writel(val, cohc->base->virtbase + COH901318_CX_CFG +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) COH901318_CX_CFG_SPACING*channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) cohc->stopped = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) spin_unlock_irqrestore(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) bool coh901318_filter_id(struct dma_chan *chan, void *chan_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) unsigned long ch_nr = (unsigned long) chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) if (ch_nr == to_coh901318_chan(chan)->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) EXPORT_SYMBOL(coh901318_filter_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) struct coh901318_filter_args {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) struct coh901318_base *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) unsigned int ch_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) static bool coh901318_filter_base_and_id(struct dma_chan *chan, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) struct coh901318_filter_args *args = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (&args->base->dma_slave == chan->device &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) args->ch_nr == to_coh901318_chan(chan)->id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) static struct dma_chan *coh901318_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) struct coh901318_filter_args args = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) .base = ofdma->of_dma_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) .ch_nr = dma_spec->args[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) dma_cap_mask_t cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) dma_cap_zero(cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) dma_cap_set(DMA_SLAVE, cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) return dma_request_channel(cap, coh901318_filter_base_and_id, &args);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) * DMA channel allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) static int coh901318_config(struct coh901318_chan *cohc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) struct coh901318_params *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) const struct coh901318_params *p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) int channel = cohc->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) void __iomem *virtbase = cohc->base->virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) if (param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) p = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) p = cohc_chan_param(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) /* Clear any pending BE or TC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) if (channel < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) writel(1 << (channel - 32), virtbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) COH901318_BE_INT_CLEAR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) writel(1 << (channel - 32), virtbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) COH901318_TC_INT_CLEAR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) coh901318_set_conf(cohc, p->config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) coh901318_set_ctrl(cohc, p->ctrl_lli_last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /* must lock when calling this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) * start queued jobs, if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) * TODO: start all queued jobs in one go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) * Returns descriptor if queued job is started otherwise NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) * If the queue is empty NULL is returned.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) static struct coh901318_desc *coh901318_queue_start(struct coh901318_chan *cohc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) struct coh901318_desc *cohd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) * start queued jobs, if any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) * TODO: transmit all queued jobs in one go
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) cohd = coh901318_first_queued(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (cohd != NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) /* Remove from queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) coh901318_desc_remove(cohd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) /* initiate DMA job */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) cohc->busy = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) coh901318_desc_submit(cohc, cohd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) /* Program the transaction head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) coh901318_set_conf(cohc, cohd->head_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) coh901318_set_ctrl(cohc, cohd->head_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) coh901318_prep_linked_list(cohc, cohd->lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) /* start dma job on this channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) coh901318_start(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) return cohd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) * This tasklet is called from the interrupt handler to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) * handle each descriptor (DMA job) that is sent to a channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) static void dma_tasklet(struct tasklet_struct *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) struct coh901318_chan *cohc = from_tasklet(cohc, t, tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) struct coh901318_desc *cohd_fin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) struct dmaengine_desc_callback cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) dev_vdbg(COHC_2_DEV(cohc), "[%s] chan_id %d"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) " nbr_active_done %ld\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) cohc->id, cohc->nbr_active_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) spin_lock_irqsave(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) /* get first active descriptor entry from list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) cohd_fin = coh901318_first_active_get(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) if (cohd_fin == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) /* locate callback to client */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) dmaengine_desc_get_callback(&cohd_fin->desc, &cb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) /* sign this job as completed on the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) dma_cookie_complete(&cohd_fin->desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) /* release the lli allocation and remove the descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) coh901318_lli_free(&cohc->base->pool, &cohd_fin->lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) /* return desc to free-list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) coh901318_desc_remove(cohd_fin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) coh901318_desc_free(cohc, cohd_fin);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) spin_unlock_irqrestore(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) /* Call the callback when we're done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) dmaengine_desc_callback_invoke(&cb, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) spin_lock_irqsave(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) * If another interrupt fired while the tasklet was scheduling,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) * we don't get called twice, so we have this number of active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) * counter that keep track of the number of IRQs expected to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) * be handled for this channel. If there happen to be more than
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) * one IRQ to be ack:ed, we simply schedule this tasklet again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) cohc->nbr_active_done--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (cohc->nbr_active_done) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) dev_dbg(COHC_2_DEV(cohc), "scheduling tasklet again, new IRQs "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) "came in while we were scheduling this tasklet\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) if (cohc_chan_conf(cohc)->priority_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) tasklet_hi_schedule(&cohc->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) tasklet_schedule(&cohc->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) spin_unlock_irqrestore(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) spin_unlock_irqrestore(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) dev_err(COHC_2_DEV(cohc), "[%s] No active dma desc\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) /* called from interrupt context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) static void dma_tc_handle(struct coh901318_chan *cohc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) * If the channel is not allocated, then we shouldn't have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) * any TC interrupts on it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) if (!cohc->allocated) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) dev_err(COHC_2_DEV(cohc), "spurious interrupt from "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) "unallocated channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) * When we reach this point, at least one queue item
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) * should have been moved over from cohc->queue to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) * cohc->active and run to completion, that is why we're
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) * getting a terminal count interrupt is it not?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) * If you get this BUG() the most probable cause is that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) * the individual nodes in the lli chain have IRQ enabled,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) * so check your platform config for lli chain ctrl.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) BUG_ON(list_empty(&cohc->active));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) cohc->nbr_active_done++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) * This attempt to take a job from cohc->queue, put it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) * into cohc->active and start it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) if (coh901318_queue_start(cohc) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) cohc->busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) * This tasklet will remove items from cohc->active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) * and thus terminates them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) if (cohc_chan_conf(cohc)->priority_high)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) tasklet_hi_schedule(&cohc->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) tasklet_schedule(&cohc->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) static irqreturn_t dma_irq_handler(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) u32 status1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) u32 status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) struct coh901318_base *base = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) struct coh901318_chan *cohc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) void __iomem *virtbase = base->virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) status1 = readl(virtbase + COH901318_INT_STATUS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) status2 = readl(virtbase + COH901318_INT_STATUS2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) if (unlikely(status1 == 0 && status2 == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) dev_warn(base->dev, "spurious DMA IRQ from no channel!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) /* TODO: consider handle IRQ in tasklet here to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) * minimize interrupt latency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) /* Check the first 32 DMA channels for IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) while (status1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) /* Find first bit set, return as a number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) i = ffs(status1) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) ch = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) cohc = &base->chans[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) spin_lock(&cohc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) /* Mask off this bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) status1 &= ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) /* Check the individual channel bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) dev_crit(COHC_2_DEV(cohc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) "DMA bus error on channel %d!\n", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) BUG_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) /* Clear BE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) /* Caused by TC, really? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) if (unlikely(!test_bit(i, virtbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) COH901318_TC_INT_STATUS1))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) dev_warn(COHC_2_DEV(cohc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) "ignoring interrupt not caused by terminal count on channel %d\n", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) /* Clear TC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) BUG_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) /* Enable powersave if transfer has finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) if (!(readl(virtbase + COH901318_CX_STAT +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) COH901318_CX_STAT_SPACING*ch) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) COH901318_CX_STAT_ENABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) enable_powersave(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) /* Must clear TC interrupt before calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) * dma_tc_handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) * in case tc_handle initiate a new dma job
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) dma_tc_handle(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) spin_unlock(&cohc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) /* Check the remaining 32 DMA channels for IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) while (status2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) /* Find first bit set, return as a number. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) i = ffs(status2) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) ch = i + 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) cohc = &base->chans[ch];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) spin_lock(&cohc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) /* Mask off this bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) status2 &= ~(1 << i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) /* Check the individual channel bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) dev_crit(COHC_2_DEV(cohc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) "DMA bus error on channel %d!\n", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) /* Clear BE interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) BUG_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) /* Caused by TC, really? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) if (unlikely(!test_bit(i, virtbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) COH901318_TC_INT_STATUS2))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) dev_warn(COHC_2_DEV(cohc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) "ignoring interrupt not caused by terminal count on channel %d\n", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) /* Clear TC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) BUG_ON(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) /* Enable powersave if transfer has finished */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) if (!(readl(virtbase + COH901318_CX_STAT +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) COH901318_CX_STAT_SPACING*ch) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) COH901318_CX_STAT_ENABLED)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) enable_powersave(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) /* Must clear TC interrupt before calling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) * dma_tc_handle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) * in case tc_handle initiate a new dma job
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) dma_tc_handle(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) spin_unlock(&cohc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) static int coh901318_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) struct coh901318_chan *cohc = to_coh901318_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) struct coh901318_desc *cohd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) void __iomem *virtbase = cohc->base->virtbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) /* The remainder of this function terminates the transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) coh901318_pause(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) spin_lock_irqsave(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) /* Clear any pending BE or TC interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) if (cohc->id < 32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) writel(1 << (cohc->id - 32), virtbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) COH901318_BE_INT_CLEAR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) writel(1 << (cohc->id - 32), virtbase +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) COH901318_TC_INT_CLEAR2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) enable_powersave(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) while ((cohd = coh901318_first_active_get(cohc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) /* release the lli allocation*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) coh901318_lli_free(&cohc->base->pool, &cohd->lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) /* return desc to free-list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) coh901318_desc_remove(cohd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) coh901318_desc_free(cohc, cohd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) while ((cohd = coh901318_first_queued(cohc))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) /* release the lli allocation*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) coh901318_lli_free(&cohc->base->pool, &cohd->lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) /* return desc to free-list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) coh901318_desc_remove(cohd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) coh901318_desc_free(cohc, cohd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) cohc->nbr_active_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) cohc->busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) spin_unlock_irqrestore(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) static int coh901318_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) struct coh901318_chan *cohc = to_coh901318_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) dev_vdbg(COHC_2_DEV(cohc), "[%s] DMA channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) __func__, cohc->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) if (chan->client_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) spin_lock_irqsave(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) coh901318_config(cohc, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) cohc->allocated = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) dma_cookie_init(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) spin_unlock_irqrestore(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) coh901318_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) struct coh901318_chan *cohc = to_coh901318_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) int channel = cohc->id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) spin_lock_irqsave(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) /* Disable HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) COH901318_CX_CFG_SPACING*channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) COH901318_CX_CTRL_SPACING*channel);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) cohc->allocated = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) spin_unlock_irqrestore(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) coh901318_terminate_all(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) static dma_cookie_t
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) coh901318_tx_submit(struct dma_async_tx_descriptor *tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) struct coh901318_desc *cohd = container_of(tx, struct coh901318_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) struct coh901318_chan *cohc = to_coh901318_chan(tx->chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) dma_cookie_t cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) spin_lock_irqsave(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) cookie = dma_cookie_assign(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) coh901318_desc_queue(cohc, cohd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) spin_unlock_irqrestore(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) return cookie;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) coh901318_prep_memcpy(struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) size_t size, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) struct coh901318_lli *lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) struct coh901318_desc *cohd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) unsigned long flg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) struct coh901318_chan *cohc = to_coh901318_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) int lli_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) spin_lock_irqsave(&cohc->lock, flg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) dev_vdbg(COHC_2_DEV(cohc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) "[%s] channel %d src %pad dest %pad size %zu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) __func__, cohc->id, &src, &dest, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) if (flags & DMA_PREP_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) /* Trigger interrupt after last lli */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) lli_len = size >> MAX_DMA_PACKET_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) if ((lli_len << MAX_DMA_PACKET_SIZE_SHIFT) < size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) lli_len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) lli = coh901318_lli_alloc(&cohc->base->pool, lli_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) if (lli == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) ret = coh901318_lli_fill_memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) &cohc->base->pool, lli, src, size, dest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) cohc_chan_param(cohc)->ctrl_lli_chained,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) ctrl_last);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) COH_DBG(coh901318_list_print(cohc, lli));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) /* Pick a descriptor to handle this transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) cohd = coh901318_desc_get(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) cohd->lli = lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) cohd->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) cohd->desc.tx_submit = coh901318_tx_submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) spin_unlock_irqrestore(&cohc->lock, flg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) return &cohd->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) spin_unlock_irqrestore(&cohc->lock, flg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) static struct dma_async_tx_descriptor *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) coh901318_prep_slave_sg(struct dma_chan *chan, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) unsigned int sg_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) unsigned long flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) struct coh901318_chan *cohc = to_coh901318_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) struct coh901318_lli *lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) struct coh901318_desc *cohd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) const struct coh901318_params *params;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) int len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) u32 ctrl_chained = cohc_chan_param(cohc)->ctrl_lli_chained;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) u32 ctrl = cohc_chan_param(cohc)->ctrl_lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) u32 ctrl_last = cohc_chan_param(cohc)->ctrl_lli_last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) u32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) unsigned long flg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) if (!sgl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) if (sg_dma_len(sgl) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) spin_lock_irqsave(&cohc->lock, flg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) dev_vdbg(COHC_2_DEV(cohc), "[%s] sg_len %d dir %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) __func__, sg_len, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) if (flags & DMA_PREP_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) /* Trigger interrupt after last lli */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) ctrl_last |= COH901318_CX_CTRL_TC_IRQ_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) params = cohc_chan_param(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) config = params->config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) * Add runtime-specific control on top, make
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) * sure the bits you set per peripheral channel are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) * cleared in the default config from the platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) ctrl_chained |= cohc->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) ctrl_last |= cohc->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) ctrl |= cohc->ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) if (direction == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) u32 tx_flags = COH901318_CX_CTRL_PRDD_SOURCE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) COH901318_CX_CTRL_SRC_ADDR_INC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) config |= COH901318_CX_CFG_RM_MEMORY_TO_PRIMARY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) ctrl_chained |= tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) ctrl_last |= tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) ctrl |= tx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) } else if (direction == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) u32 rx_flags = COH901318_CX_CTRL_PRDD_DEST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) COH901318_CX_CTRL_DST_ADDR_INC_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) config |= COH901318_CX_CFG_RM_PRIMARY_TO_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) ctrl_chained |= rx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) ctrl_last |= rx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) ctrl |= rx_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) goto err_direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) /* The dma only supports transmitting packages up to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) * MAX_DMA_PACKET_SIZE. Calculate to total number of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) * dma elemts required to send the entire sg list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) for_each_sg(sgl, sg, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) unsigned int factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) size = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) if (size <= MAX_DMA_PACKET_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) factor = size >> MAX_DMA_PACKET_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) if ((factor << MAX_DMA_PACKET_SIZE_SHIFT) < size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) factor++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) len += factor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) pr_debug("Allocate %d lli:s for this transfer\n", len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) lli = coh901318_lli_alloc(&cohc->base->pool, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) if (lli == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) goto err_dma_alloc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) coh901318_dma_set_runtimeconfig(chan, &cohc->config, direction);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) /* initiate allocated lli list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) ret = coh901318_lli_fill_sg(&cohc->base->pool, lli, sgl, sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) cohc->addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) ctrl_chained,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) ctrl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) ctrl_last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) direction, COH901318_CX_CTRL_TC_IRQ_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) goto err_lli_fill;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) COH_DBG(coh901318_list_print(cohc, lli));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) /* Pick a descriptor to handle this transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) cohd = coh901318_desc_get(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) cohd->head_config = config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) * Set the default head ctrl for the channel to the one from the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) * lli, things may have changed due to odd buffer alignment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) * etc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) cohd->head_ctrl = lli->control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) cohd->dir = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) cohd->flags = flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) cohd->desc.tx_submit = coh901318_tx_submit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) cohd->lli = lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) spin_unlock_irqrestore(&cohc->lock, flg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) return &cohd->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) err_lli_fill:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) err_dma_alloc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) err_direction:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) spin_unlock_irqrestore(&cohc->lock, flg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) static enum dma_status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) coh901318_tx_status(struct dma_chan *chan, dma_cookie_t cookie,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) struct coh901318_chan *cohc = to_coh901318_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) enum dma_status ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) ret = dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) if (ret == DMA_COMPLETE || !txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) dma_set_residue(txstate, coh901318_get_bytes_left(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) if (ret == DMA_IN_PROGRESS && cohc->stopped)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) ret = DMA_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) static void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) coh901318_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) struct coh901318_chan *cohc = to_coh901318_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) spin_lock_irqsave(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) * Busy means that pending jobs are already being processed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) * and then there is no point in starting the queue: the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) * terminal count interrupt on the channel will take the next
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) * job on the queue and execute it anyway.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) if (!cohc->busy)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) coh901318_queue_start(cohc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) spin_unlock_irqrestore(&cohc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) * Here we wrap in the runtime dma control interface
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) struct burst_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) int burst_8bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) int burst_16bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) int burst_32bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) static const struct burst_table burst_sizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) .burst_8bit = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .burst_16bit = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) .burst_32bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) .reg = COH901318_CX_CTRL_BURST_COUNT_64_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .burst_8bit = 48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .burst_16bit = 24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) .burst_32bit = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) .reg = COH901318_CX_CTRL_BURST_COUNT_48_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) .burst_8bit = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .burst_16bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) .burst_32bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) .reg = COH901318_CX_CTRL_BURST_COUNT_32_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) .burst_8bit = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) .burst_16bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) .burst_32bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) .reg = COH901318_CX_CTRL_BURST_COUNT_16_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .burst_8bit = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .burst_16bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .burst_32bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) .reg = COH901318_CX_CTRL_BURST_COUNT_8_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) .burst_8bit = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) .burst_16bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .burst_32bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .reg = COH901318_CX_CTRL_BURST_COUNT_4_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) .burst_8bit = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) .burst_16bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) .burst_32bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) .reg = COH901318_CX_CTRL_BURST_COUNT_2_BYTES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) .burst_8bit = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) .burst_16bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .burst_32bit = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .reg = COH901318_CX_CTRL_BURST_COUNT_1_BYTE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) static int coh901318_dma_set_runtimeconfig(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) struct dma_slave_config *config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) enum dma_transfer_direction direction)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) struct coh901318_chan *cohc = to_coh901318_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) enum dma_slave_buswidth addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) u32 maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) u32 ctrl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) /* We only support mem to per or per to mem transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) if (direction == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) addr = config->src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) addr_width = config->src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) maxburst = config->src_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) } else if (direction == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) addr = config->dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) addr_width = config->dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) maxburst = config->dst_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) dev_err(COHC_2_DEV(cohc), "illegal channel mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) dev_dbg(COHC_2_DEV(cohc), "configure channel for %d byte transfers\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) switch (addr_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) ctrl |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) COH901318_CX_CTRL_SRC_BUS_SIZE_8_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) COH901318_CX_CTRL_DST_BUS_SIZE_8_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) while (i < ARRAY_SIZE(burst_sizes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) if (burst_sizes[i].burst_8bit <= maxburst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) ctrl |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) COH901318_CX_CTRL_SRC_BUS_SIZE_16_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) COH901318_CX_CTRL_DST_BUS_SIZE_16_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) while (i < ARRAY_SIZE(burst_sizes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) if (burst_sizes[i].burst_16bit <= maxburst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) /* Direction doesn't matter here, it's 32/32 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) ctrl |=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) COH901318_CX_CTRL_SRC_BUS_SIZE_32_BITS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) COH901318_CX_CTRL_DST_BUS_SIZE_32_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) while (i < ARRAY_SIZE(burst_sizes)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) if (burst_sizes[i].burst_32bit <= maxburst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) i++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) dev_err(COHC_2_DEV(cohc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) "bad runtimeconfig: alien address width\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) ctrl |= burst_sizes[i].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) dev_dbg(COHC_2_DEV(cohc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) "selected burst size %d bytes for address width %d bytes, maxburst %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) burst_sizes[i].burst_8bit, addr_width, maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) cohc->addr = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) cohc->ctrl = ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) static int coh901318_dma_slave_config(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) struct dma_slave_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) struct coh901318_chan *cohc = to_coh901318_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) memcpy(&cohc->config, config, sizeof(*config));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) static void coh901318_base_init(struct dma_device *dma, const int *pick_chans,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) struct coh901318_base *base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) int chans_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) struct coh901318_chan *cohc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) INIT_LIST_HEAD(&dma->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) cohc = &base->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) cohc->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) cohc->chan.device = dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) cohc->id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) /* TODO: do we really need this lock if only one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) * client is connected to each channel?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) spin_lock_init(&cohc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) cohc->nbr_active_done = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) cohc->busy = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) INIT_LIST_HEAD(&cohc->free);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) INIT_LIST_HEAD(&cohc->active);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) INIT_LIST_HEAD(&cohc->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) tasklet_setup(&cohc->tasklet, dma_tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) list_add_tail(&cohc->chan.device_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) &dma->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) static int __init coh901318_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) struct coh901318_base *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) struct resource *io;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) io = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) if (!io)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) /* Map DMA controller registers to virtual memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) if (devm_request_mem_region(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) io->start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) resource_size(io),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) pdev->dev.driver->name) == NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) base = devm_kzalloc(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) ALIGN(sizeof(struct coh901318_base), 4) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) U300_DMA_CHANNELS *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) sizeof(struct coh901318_chan),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) if (!base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) base->chans = ((void *)base) + ALIGN(sizeof(struct coh901318_base), 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) if (!base->virtbase)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) base->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) spin_lock_init(&base->pm.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) base->pm.started_channels = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) COH901318_DEBUGFS_ASSIGN(debugfs_dma_base, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) err = devm_request_irq(&pdev->dev, irq, dma_irq_handler, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) "coh901318", base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) base->irq = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) err = coh901318_pool_create(&base->pool, &pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) sizeof(struct coh901318_lli),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) /* init channels for device transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) coh901318_base_init(&base->dma_slave, dma_slave_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) dma_cap_zero(base->dma_slave.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) dma_cap_set(DMA_SLAVE, base->dma_slave.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) base->dma_slave.device_alloc_chan_resources = coh901318_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) base->dma_slave.device_free_chan_resources = coh901318_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) base->dma_slave.device_prep_slave_sg = coh901318_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) base->dma_slave.device_tx_status = coh901318_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) base->dma_slave.device_issue_pending = coh901318_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) base->dma_slave.device_config = coh901318_dma_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) base->dma_slave.device_pause = coh901318_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) base->dma_slave.device_resume = coh901318_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) base->dma_slave.device_terminate_all = coh901318_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) base->dma_slave.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) err = dma_async_device_register(&base->dma_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) goto err_register_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) /* init channels for memcpy */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) coh901318_base_init(&base->dma_memcpy, dma_memcpy_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) dma_cap_zero(base->dma_memcpy.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) dma_cap_set(DMA_MEMCPY, base->dma_memcpy.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) base->dma_memcpy.device_alloc_chan_resources = coh901318_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) base->dma_memcpy.device_free_chan_resources = coh901318_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) base->dma_memcpy.device_prep_dma_memcpy = coh901318_prep_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) base->dma_memcpy.device_tx_status = coh901318_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) base->dma_memcpy.device_issue_pending = coh901318_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) base->dma_memcpy.device_config = coh901318_dma_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) base->dma_memcpy.device_pause = coh901318_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) base->dma_memcpy.device_resume = coh901318_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) base->dma_memcpy.device_terminate_all = coh901318_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) base->dma_memcpy.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) * This controller can only access address at even 32bit boundaries,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) * i.e. 2^2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) base->dma_memcpy.copy_align = DMAENGINE_ALIGN_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) err = dma_async_device_register(&base->dma_memcpy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) goto err_register_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) err = of_dma_controller_register(pdev->dev.of_node, coh901318_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) goto err_register_of_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) platform_set_drvdata(pdev, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) dev_info(&pdev->dev, "Initialized COH901318 DMA on virtual base 0x%p\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) base->virtbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) err_register_of_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) dma_async_device_unregister(&base->dma_memcpy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) err_register_memcpy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) dma_async_device_unregister(&base->dma_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) err_register_slave:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) coh901318_pool_destroy(&base->pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) static void coh901318_base_remove(struct coh901318_base *base, const int *pick_chans)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) int chans_i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) int i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) struct coh901318_chan *cohc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) for (chans_i = 0; pick_chans[chans_i] != -1; chans_i += 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) for (i = pick_chans[chans_i]; i <= pick_chans[chans_i+1]; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) cohc = &base->chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) tasklet_kill(&cohc->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) static int coh901318_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) struct coh901318_base *base = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) devm_free_irq(&pdev->dev, base->irq, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) coh901318_base_remove(base, dma_slave_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) coh901318_base_remove(base, dma_memcpy_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) of_dma_controller_free(pdev->dev.of_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) dma_async_device_unregister(&base->dma_memcpy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) dma_async_device_unregister(&base->dma_slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) coh901318_pool_destroy(&base->pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) static const struct of_device_id coh901318_dt_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) { .compatible = "stericsson,coh901318" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) static struct platform_driver coh901318_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) .remove = coh901318_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) .name = "coh901318",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .of_match_table = coh901318_dt_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) static int __init coh901318_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) return platform_driver_probe(&coh901318_driver, coh901318_probe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) subsys_initcall(coh901318_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) static void __exit coh901318_exit(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) platform_driver_unregister(&coh901318_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) module_exit(coh901318_exit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) MODULE_AUTHOR("Per Friden");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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