^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for MPC52xx processor BestComm General Buffer Descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2007 Sylvain Munaut <tnt@246tNt.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2006 AppSpec Computer Technologies Corp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Jeff Gibbons <jeff.gibbons@appspec.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <asm/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <asm/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <asm/mpc52xx.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <asm/mpc52xx_psc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/fsl/bestcomm/bestcomm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/fsl/bestcomm/bestcomm_priv.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/fsl/bestcomm/gen_bd.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Task image/var/inc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* gen_bd tasks images */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) extern u32 bcom_gen_bd_rx_task[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) extern u32 bcom_gen_bd_tx_task[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* rx task vars that need to be set before enabling the task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) struct bcom_gen_bd_rx_var {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) u32 enable; /* (u16*) address of task's control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) u32 fifo; /* (u32*) address of gen_bd's fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) u32 bd_base; /* (struct bcom_bd*) beginning of ring buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) u32 bd_last; /* (struct bcom_bd*) end of ring buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) u32 bd_start; /* (struct bcom_bd*) current bd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) u32 buffer_size; /* size of receive buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* rx task incs that need to be set before enabling the task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct bcom_gen_bd_rx_inc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) u16 pad0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) s16 incr_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) u16 pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) s16 incr_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* tx task vars that need to be set before enabling the task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) struct bcom_gen_bd_tx_var {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) u32 fifo; /* (u32*) address of gen_bd's fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) u32 enable; /* (u16*) address of task's control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) u32 bd_base; /* (struct bcom_bd*) beginning of ring buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) u32 bd_last; /* (struct bcom_bd*) end of ring buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) u32 bd_start; /* (struct bcom_bd*) current bd */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) u32 buffer_size; /* set by uCode for each packet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* tx task incs that need to be set before enabling the task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) struct bcom_gen_bd_tx_inc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) u16 pad0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) s16 incr_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u16 pad1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) s16 incr_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) u16 pad2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) s16 incr_src_ma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* private structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct bcom_gen_bd_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) phys_addr_t fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int initiator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) int ipr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int maxbufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /* Task support code */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* ======================================================================== */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) struct bcom_task *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) bcom_gen_bd_rx_init(int queue_len, phys_addr_t fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) int initiator, int ipr, int maxbufsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) struct bcom_task *tsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct bcom_gen_bd_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) tsk = bcom_task_alloc(queue_len, sizeof(struct bcom_gen_bd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) sizeof(struct bcom_gen_bd_priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) if (!tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) tsk->flags = BCOM_FLAGS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) priv = tsk->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) priv->fifo = fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) priv->initiator = initiator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) priv->ipr = ipr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) priv->maxbufsize = maxbufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) if (bcom_gen_bd_rx_reset(tsk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) bcom_task_free(tsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return tsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) EXPORT_SYMBOL_GPL(bcom_gen_bd_rx_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) bcom_gen_bd_rx_reset(struct bcom_task *tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct bcom_gen_bd_priv *priv = tsk->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct bcom_gen_bd_rx_var *var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct bcom_gen_bd_rx_inc *inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* Shutdown the task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) bcom_disable_task(tsk->tasknum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* Reset the microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) var = (struct bcom_gen_bd_rx_var *) bcom_task_var(tsk->tasknum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) inc = (struct bcom_gen_bd_rx_inc *) bcom_task_inc(tsk->tasknum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) if (bcom_load_image(tsk->tasknum, bcom_gen_bd_rx_task))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) var->enable = bcom_eng->regs_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) var->fifo = (u32) priv->fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) var->bd_base = tsk->bd_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) var->bd_last = tsk->bd_pa + ((tsk->num_bd-1) * tsk->bd_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) var->bd_start = tsk->bd_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) var->buffer_size = priv->maxbufsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) inc->incr_bytes = -(s16)sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) inc->incr_dst = sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Reset the BDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) tsk->index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) tsk->outdex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) memset(tsk->bd, 0x00, tsk->num_bd * tsk->bd_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Configure some stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) bcom_set_task_pragma(tsk->tasknum, BCOM_GEN_RX_BD_PRAGMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) bcom_set_task_auto_start(tsk->tasknum, tsk->tasknum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) out_8(&bcom_eng->regs->ipr[priv->initiator], priv->ipr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) bcom_set_initiator(tsk->tasknum, priv->initiator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) out_be32(&bcom_eng->regs->IntPend, 1<<tsk->tasknum); /* Clear ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) EXPORT_SYMBOL_GPL(bcom_gen_bd_rx_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bcom_gen_bd_rx_release(struct bcom_task *tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Nothing special for the GenBD tasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) bcom_task_free(tsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) EXPORT_SYMBOL_GPL(bcom_gen_bd_rx_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) extern struct bcom_task *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) bcom_gen_bd_tx_init(int queue_len, phys_addr_t fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) int initiator, int ipr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) struct bcom_task *tsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) struct bcom_gen_bd_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) tsk = bcom_task_alloc(queue_len, sizeof(struct bcom_gen_bd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) sizeof(struct bcom_gen_bd_priv));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) if (!tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) tsk->flags = BCOM_FLAGS_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) priv = tsk->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) priv->fifo = fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) priv->initiator = initiator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) priv->ipr = ipr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) if (bcom_gen_bd_tx_reset(tsk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) bcom_task_free(tsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) return tsk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) EXPORT_SYMBOL_GPL(bcom_gen_bd_tx_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) bcom_gen_bd_tx_reset(struct bcom_task *tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct bcom_gen_bd_priv *priv = tsk->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) struct bcom_gen_bd_tx_var *var;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct bcom_gen_bd_tx_inc *inc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) /* Shutdown the task */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) bcom_disable_task(tsk->tasknum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Reset the microcode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) var = (struct bcom_gen_bd_tx_var *) bcom_task_var(tsk->tasknum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) inc = (struct bcom_gen_bd_tx_inc *) bcom_task_inc(tsk->tasknum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) if (bcom_load_image(tsk->tasknum, bcom_gen_bd_tx_task))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) return -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) var->enable = bcom_eng->regs_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) offsetof(struct mpc52xx_sdma, tcr[tsk->tasknum]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) var->fifo = (u32) priv->fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) var->bd_base = tsk->bd_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) var->bd_last = tsk->bd_pa + ((tsk->num_bd-1) * tsk->bd_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) var->bd_start = tsk->bd_pa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) inc->incr_bytes = -(s16)sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) inc->incr_src = sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) inc->incr_src_ma = sizeof(u8);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* Reset the BDs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) tsk->index = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) tsk->outdex = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) memset(tsk->bd, 0x00, tsk->num_bd * tsk->bd_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* Configure some stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) bcom_set_task_pragma(tsk->tasknum, BCOM_GEN_TX_BD_PRAGMA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) bcom_set_task_auto_start(tsk->tasknum, tsk->tasknum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) out_8(&bcom_eng->regs->ipr[priv->initiator], priv->ipr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) bcom_set_initiator(tsk->tasknum, priv->initiator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) out_be32(&bcom_eng->regs->IntPend, 1<<tsk->tasknum); /* Clear ints */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) EXPORT_SYMBOL_GPL(bcom_gen_bd_tx_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) bcom_gen_bd_tx_release(struct bcom_task *tsk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Nothing special for the GenBD tasks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) bcom_task_free(tsk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) EXPORT_SYMBOL_GPL(bcom_gen_bd_tx_release);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) /* ---------------------------------------------------------------------
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * PSC support code
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * bcom_psc_parameters - Bestcomm initialization value table for PSC devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * This structure is only used internally. It is a lookup table for PSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * specific parameters to bestcomm tasks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) static struct bcom_psc_params {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) int rx_initiator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int rx_ipr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) int tx_initiator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) int tx_ipr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) } bcom_psc_params[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) [0] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) .rx_initiator = BCOM_INITIATOR_PSC1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) .rx_ipr = BCOM_IPR_PSC1_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) .tx_initiator = BCOM_INITIATOR_PSC1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .tx_ipr = BCOM_IPR_PSC1_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) [1] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .rx_initiator = BCOM_INITIATOR_PSC2_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .rx_ipr = BCOM_IPR_PSC2_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .tx_initiator = BCOM_INITIATOR_PSC2_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .tx_ipr = BCOM_IPR_PSC2_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) [2] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .rx_initiator = BCOM_INITIATOR_PSC3_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .rx_ipr = BCOM_IPR_PSC3_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .tx_initiator = BCOM_INITIATOR_PSC3_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .tx_ipr = BCOM_IPR_PSC3_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) [3] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .rx_initiator = BCOM_INITIATOR_PSC4_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .rx_ipr = BCOM_IPR_PSC4_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .tx_initiator = BCOM_INITIATOR_PSC4_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) .tx_ipr = BCOM_IPR_PSC4_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) [4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) .rx_initiator = BCOM_INITIATOR_PSC5_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .rx_ipr = BCOM_IPR_PSC5_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .tx_initiator = BCOM_INITIATOR_PSC5_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .tx_ipr = BCOM_IPR_PSC5_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) [5] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .rx_initiator = BCOM_INITIATOR_PSC6_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .rx_ipr = BCOM_IPR_PSC6_RX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .tx_initiator = BCOM_INITIATOR_PSC6_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .tx_ipr = BCOM_IPR_PSC6_TX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * bcom_psc_gen_bd_rx_init - Allocate a receive bcom_task for a PSC port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @psc_num: Number of the PSC to allocate a task for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * @queue_len: number of buffer descriptors to allocate for the task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * @fifo: physical address of FIFO register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * @maxbufsize: Maximum receive data size in bytes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * Allocate a bestcomm task structure for receiving data from a PSC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct bcom_task * bcom_psc_gen_bd_rx_init(unsigned psc_num, int queue_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) phys_addr_t fifo, int maxbufsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (psc_num >= MPC52xx_PSC_MAXNUM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) return bcom_gen_bd_rx_init(queue_len, fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) bcom_psc_params[psc_num].rx_initiator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) bcom_psc_params[psc_num].rx_ipr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) maxbufsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) EXPORT_SYMBOL_GPL(bcom_psc_gen_bd_rx_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * bcom_psc_gen_bd_tx_init - Allocate a transmit bcom_task for a PSC port
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * @psc_num: Number of the PSC to allocate a task for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * @queue_len: number of buffer descriptors to allocate for the task
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * @fifo: physical address of FIFO register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * Allocate a bestcomm task structure for transmitting data to a PSC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) struct bcom_task *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) bcom_psc_gen_bd_tx_init(unsigned psc_num, int queue_len, phys_addr_t fifo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) struct psc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) return bcom_gen_bd_tx_init(queue_len, fifo,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bcom_psc_params[psc_num].tx_initiator,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) bcom_psc_params[psc_num].tx_ipr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) EXPORT_SYMBOL_GPL(bcom_psc_gen_bd_tx_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) MODULE_DESCRIPTION("BestComm General Buffer Descriptor tasks driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) MODULE_AUTHOR("Jeff Gibbons <jeff.gibbons@appspec.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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