^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * BCM2835 DMA engine support
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Florian Meier <florian.meier@koalo.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright 2013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * OMAP DMAengine support by Russell King
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * BCM2708 DMA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Copyright (C) 2010 Broadcom
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * Raspberry Pi PCM I2S ALSA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * Copyright (c) by Phil Poole 2013
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * MARVELL MMP Peripheral DMA Driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * Copyright 2012 Marvell International Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/list.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include "virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define BCM2835_DMA_CHAN_NAME_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * struct bcm2835_dmadev - BCM2835 DMA controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @ddev: DMA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @base: base address of register map
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @zero_page: bus address of zero page (to detect transactions copying from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * zero page and avoid accessing memory if so)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct bcm2835_dmadev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) struct dma_device ddev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) dma_addr_t zero_page;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct bcm2835_dma_cb {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) uint32_t info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) uint32_t src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) uint32_t dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) uint32_t length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) uint32_t stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) uint32_t next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) uint32_t pad[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct bcm2835_cb_entry {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) struct bcm2835_dma_cb *cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dma_addr_t paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct bcm2835_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) struct virt_dma_chan vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) unsigned int dreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) struct bcm2835_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) struct dma_pool *cb_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) void __iomem *chan_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) int irq_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) unsigned int irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) bool is_lite_channel;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct bcm2835_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct bcm2835_chan *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct virt_dma_desc vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) enum dma_transfer_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) unsigned int frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) bool cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct bcm2835_cb_entry cb_list[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define BCM2835_DMA_CS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define BCM2835_DMA_ADDR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define BCM2835_DMA_TI 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define BCM2835_DMA_SOURCE_AD 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define BCM2835_DMA_DEST_AD 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define BCM2835_DMA_LEN 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define BCM2835_DMA_STRIDE 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define BCM2835_DMA_NEXTCB 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define BCM2835_DMA_DEBUG 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* DMA CS Control and Status bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define BCM2835_DMA_ACTIVE BIT(0) /* activate the DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define BCM2835_DMA_END BIT(1) /* current CB has ended */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define BCM2835_DMA_INT BIT(2) /* interrupt status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BCM2835_DMA_DREQ BIT(3) /* DREQ state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define BCM2835_DMA_ISPAUSED BIT(4) /* Pause requested or not active */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define BCM2835_DMA_ISHELD BIT(5) /* Is held by DREQ flow control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define BCM2835_DMA_WAITING_FOR_WRITES BIT(6) /* waiting for last
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * AXI-write to ack
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define BCM2835_DMA_ERR BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define BCM2835_DMA_PRIORITY(x) ((x & 15) << 16) /* AXI priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define BCM2835_DMA_PANIC_PRIORITY(x) ((x & 15) << 20) /* panic priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* current value of TI.BCM2835_DMA_WAIT_RESP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define BCM2835_DMA_WAIT_FOR_WRITES BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define BCM2835_DMA_DIS_DEBUG BIT(29) /* disable debug pause signal */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define BCM2835_DMA_ABORT BIT(30) /* Stop current CB, go to next, WO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define BCM2835_DMA_RESET BIT(31) /* WO, self clearing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* Transfer information bits - also bcm2835_cb.info field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define BCM2835_DMA_INT_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define BCM2835_DMA_TDMODE BIT(1) /* 2D-Mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define BCM2835_DMA_WAIT_RESP BIT(3) /* wait for AXI-write to be acked */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define BCM2835_DMA_D_INC BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define BCM2835_DMA_D_WIDTH BIT(5) /* 128bit writes if set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define BCM2835_DMA_D_DREQ BIT(6) /* enable DREQ for destination */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define BCM2835_DMA_D_IGNORE BIT(7) /* ignore destination writes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define BCM2835_DMA_S_INC BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define BCM2835_DMA_S_WIDTH BIT(9) /* 128bit writes if set */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BCM2835_DMA_S_DREQ BIT(10) /* enable SREQ for source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define BCM2835_DMA_S_IGNORE BIT(11) /* ignore source reads - read 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define BCM2835_DMA_BURST_LENGTH(x) ((x & 15) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define BCM2835_DMA_PER_MAP(x) ((x & 31) << 16) /* REQ source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define BCM2835_DMA_WAIT(x) ((x & 31) << 21) /* add DMA-wait cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define BCM2835_DMA_NO_WIDE_BURSTS BIT(26) /* no 2 beat write bursts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* debug register bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define BCM2835_DMA_DEBUG_LAST_NOT_SET_ERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define BCM2835_DMA_DEBUG_FIFO_ERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define BCM2835_DMA_DEBUG_READ_ERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define BCM2835_DMA_DEBUG_OUTSTANDING_WRITES_BITS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define BCM2835_DMA_DEBUG_ID_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define BCM2835_DMA_DEBUG_ID_BITS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define BCM2835_DMA_DEBUG_STATE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define BCM2835_DMA_DEBUG_STATE_BITS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define BCM2835_DMA_DEBUG_VERSION_SHIFT 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define BCM2835_DMA_DEBUG_VERSION_BITS 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define BCM2835_DMA_DEBUG_LITE BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* shared registers for all dma channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define BCM2835_DMA_INT_STATUS 0xfe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define BCM2835_DMA_ENABLE 0xff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define BCM2835_DMA_DATA_TYPE_S8 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define BCM2835_DMA_DATA_TYPE_S16 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define BCM2835_DMA_DATA_TYPE_S32 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define BCM2835_DMA_DATA_TYPE_S128 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Valid only for channels 0 - 14, 15 has its own base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define BCM2835_DMA_CHAN(n) ((n) << 8) /* Base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define BCM2835_DMA_CHANIO(base, n) ((base) + BCM2835_DMA_CHAN(n))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* the max dma length for different channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define MAX_DMA_LEN SZ_1G
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define MAX_LITE_DMA_LEN (SZ_64K - 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) static inline size_t bcm2835_dma_max_frame_length(struct bcm2835_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* lite and normal channels have different max frame length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return c->is_lite_channel ? MAX_LITE_DMA_LEN : MAX_DMA_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* how many frames of max_len size do we need to transfer len bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static inline size_t bcm2835_dma_frames_for_length(size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) size_t max_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) return DIV_ROUND_UP(len, max_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) static inline struct bcm2835_dmadev *to_bcm2835_dma_dev(struct dma_device *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) return container_of(d, struct bcm2835_dmadev, ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static inline struct bcm2835_chan *to_bcm2835_dma_chan(struct dma_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return container_of(c, struct bcm2835_chan, vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static inline struct bcm2835_desc *to_bcm2835_dma_desc(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct dma_async_tx_descriptor *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return container_of(t, struct bcm2835_desc, vd.tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void bcm2835_dma_free_cb_chain(struct bcm2835_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) size_t i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) for (i = 0; i < desc->frames; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) dma_pool_free(desc->c->cb_pool, desc->cb_list[i].cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) desc->cb_list[i].paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) kfree(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) static void bcm2835_dma_desc_free(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) bcm2835_dma_free_cb_chain(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) container_of(vd, struct bcm2835_desc, vd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) static void bcm2835_dma_create_cb_set_length(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct bcm2835_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) struct bcm2835_dma_cb *control_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) size_t len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) size_t period_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) size_t *total_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 finalextrainfo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) size_t max_len = bcm2835_dma_max_frame_length(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* set the length taking lite-channel limitations into account */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) control_block->length = min_t(u32, len, max_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* finished if we have no period_length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (!period_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * period_len means: that we need to generate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * transfers that are terminating at every
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * multiple of period_len - this is typically
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * used to set the interrupt flag in info
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * which is required during cyclic transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* have we filled in period_length yet? */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) if (*total_len + control_block->length < period_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* update number of bytes in this period so far */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) *total_len += control_block->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* calculate the length that remains to reach period_length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) control_block->length = period_len - *total_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* reset total_length for next period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) *total_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* add extrainfo bits in info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) control_block->info |= finalextrainfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline size_t bcm2835_dma_count_frames_for_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct bcm2835_chan *c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) unsigned int sg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) size_t frames = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct scatterlist *sgent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) size_t plength = bcm2835_dma_max_frame_length(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) for_each_sg(sgl, sgent, sg_len, i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) frames += bcm2835_dma_frames_for_length(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) sg_dma_len(sgent), plength);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * bcm2835_dma_create_cb_chain - create a control block and fills data in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * @chan: the @dma_chan for which we run this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * @direction: the direction in which we transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * @cyclic: it is a cyclic transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * @info: the default info bits to apply per controlblock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * @frames: number of controlblocks to allocate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * @src: the src address to assign (if the S_INC bit is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * in @info, then it gets incremented)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * @dst: the dst address to assign (if the D_INC bit is set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * in @info, then it gets incremented)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @buf_len: the full buffer length (may also be 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @period_len: the period length when to apply @finalextrainfo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * in addition to the last transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * this will also break some control-blocks early
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * @finalextrainfo: additional bits in last controlblock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * (or when period_len is reached in case of cyclic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @gfp: the GFP flag to use for allocation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) static struct bcm2835_desc *bcm2835_dma_create_cb_chain(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) struct dma_chan *chan, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) bool cyclic, u32 info, u32 finalextrainfo, size_t frames,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) dma_addr_t src, dma_addr_t dst, size_t buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) size_t period_len, gfp_t gfp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) size_t len = buf_len, total_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) size_t frame;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct bcm2835_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct bcm2835_cb_entry *cb_entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) struct bcm2835_dma_cb *control_block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) if (!frames)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* allocate and setup the descriptor. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) d = kzalloc(struct_size(d, cb_list, frames), gfp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) d->c = c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) d->dir = direction;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) d->cyclic = cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Iterate over all frames, create a control block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * for each frame and link them together.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) for (frame = 0, total_len = 0; frame < frames; d->frames++, frame++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) cb_entry = &d->cb_list[frame];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) cb_entry->cb = dma_pool_alloc(c->cb_pool, gfp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) &cb_entry->paddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!cb_entry->cb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) goto error_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* fill in the control block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) control_block = cb_entry->cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) control_block->info = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) control_block->src = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) control_block->dst = dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) control_block->stride = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) control_block->next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* set up length in control_block if requested */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* calculate length honoring period_length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) bcm2835_dma_create_cb_set_length(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) c, control_block,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) len, period_len, &total_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) cyclic ? finalextrainfo : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) /* calculate new remaining length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) len -= control_block->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* link this the last controlblock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) if (frame)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) d->cb_list[frame - 1].cb->next = cb_entry->paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* update src and dst and length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (src && (info & BCM2835_DMA_S_INC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) src += control_block->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (dst && (info & BCM2835_DMA_D_INC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dst += control_block->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Length of total transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) d->size += control_block->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* the last frame requires extra flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) d->cb_list[d->frames - 1].cb->info |= finalextrainfo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* detect a size missmatch */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) if (buf_len && (d->size != buf_len))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) goto error_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) error_cb:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) bcm2835_dma_free_cb_chain(d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) static void bcm2835_dma_fill_cb_chain_with_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) struct bcm2835_cb_entry *cb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int sg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) size_t len, max_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) struct scatterlist *sgent;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) max_len = bcm2835_dma_max_frame_length(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) for_each_sg(sgl, sgent, sg_len, i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) for (addr = sg_dma_address(sgent), len = sg_dma_len(sgent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) len > 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) addr += cb->cb->length, len -= cb->cb->length, cb++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (direction == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) cb->cb->dst = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) cb->cb->src = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) cb->cb->length = min(len, max_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) static void bcm2835_dma_abort(struct bcm2835_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) void __iomem *chan_base = c->chan_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) long int timeout = 10000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * A zero control block address means the channel is idle.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * (The ACTIVE flag in the CS register is not a reliable indicator.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!readl(chan_base + BCM2835_DMA_ADDR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Write 0 to the active bit - Pause the DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) writel(0, chan_base + BCM2835_DMA_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* Wait for any current AXI transfer to complete */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) while ((readl(chan_base + BCM2835_DMA_CS) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) BCM2835_DMA_WAITING_FOR_WRITES) && --timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) /* Peripheral might be stuck and fail to signal AXI write responses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) if (!timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_err(c->vc.chan.device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) "failed to complete outstanding writes\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) writel(BCM2835_DMA_RESET, chan_base + BCM2835_DMA_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) static void bcm2835_dma_start_desc(struct bcm2835_chan *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) struct virt_dma_desc *vd = vchan_next_desc(&c->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) struct bcm2835_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!vd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) c->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) list_del(&vd->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) c->desc = d = to_bcm2835_dma_desc(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) writel(d->cb_list[0].paddr, c->chan_base + BCM2835_DMA_ADDR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) writel(BCM2835_DMA_ACTIVE, c->chan_base + BCM2835_DMA_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) static irqreturn_t bcm2835_dma_callback(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) struct bcm2835_chan *c = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct bcm2835_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* check the shared interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (c->irq_flags & IRQF_SHARED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) /* check if the interrupt is enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) flags = readl(c->chan_base + BCM2835_DMA_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /* if not set then we are not the reason for the irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) if (!(flags & BCM2835_DMA_INT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) spin_lock_irqsave(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * Clear the INT flag to receive further interrupts. Keep the channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * active in case the descriptor is cyclic or in case the client has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) * already terminated the descriptor and issued a new one. (May happen
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) * if this IRQ handler is threaded.) If the channel is finished, it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) * will remain idle despite the ACTIVE flag being set.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) writel(BCM2835_DMA_INT | BCM2835_DMA_ACTIVE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) c->chan_base + BCM2835_DMA_CS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) d = c->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (d) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (d->cyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /* call the cyclic callback */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) vchan_cyclic_callback(&d->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) } else if (!readl(c->chan_base + BCM2835_DMA_ADDR)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) vchan_cookie_complete(&c->desc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) bcm2835_dma_start_desc(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) spin_unlock_irqrestore(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) static int bcm2835_dma_alloc_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) struct device *dev = c->vc.chan.device->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev_dbg(dev, "Allocating DMA channel %d\n", c->ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) * Control blocks are 256 bit in length and must start at a 256 bit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * (32 byte) aligned address (BCM2835 ARM Peripherals, sec. 4.2.1.1).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) c->cb_pool = dma_pool_create(dev_name(dev), dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) sizeof(struct bcm2835_dma_cb), 32, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) if (!c->cb_pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_err(dev, "unable to allocate descriptor pool\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) return request_irq(c->irq_number, bcm2835_dma_callback,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) c->irq_flags, "DMA IRQ", c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) static void bcm2835_dma_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) vchan_free_chan_resources(&c->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) free_irq(c->irq_number, c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) dma_pool_destroy(c->cb_pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_dbg(c->vc.chan.device->dev, "Freeing DMA channel %u\n", c->ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) static size_t bcm2835_dma_desc_size(struct bcm2835_desc *d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) return d->size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) static size_t bcm2835_dma_desc_size_pos(struct bcm2835_desc *d, dma_addr_t addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) for (size = i = 0; i < d->frames; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) struct bcm2835_dma_cb *control_block = d->cb_list[i].cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) size_t this_size = control_block->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) if (d->dir == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) dma = control_block->dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) dma = control_block->src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) if (size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) size += this_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) else if (addr >= dma && addr < dma + this_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) size += dma + this_size - addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) static enum dma_status bcm2835_dma_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) dma_cookie_t cookie, struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct virt_dma_desc *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) enum dma_status ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ret = dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) if (ret == DMA_COMPLETE || !txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) spin_lock_irqsave(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) vd = vchan_find_desc(&c->vc, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) if (vd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) txstate->residue =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) bcm2835_dma_desc_size(to_bcm2835_dma_desc(&vd->tx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) } else if (c->desc && c->desc->vd.tx.cookie == cookie) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct bcm2835_desc *d = c->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) dma_addr_t pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (d->dir == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) pos = readl(c->chan_base + BCM2835_DMA_SOURCE_AD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) else if (d->dir == DMA_DEV_TO_MEM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pos = readl(c->chan_base + BCM2835_DMA_DEST_AD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) pos = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) txstate->residue = bcm2835_dma_desc_size_pos(d, pos);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) txstate->residue = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) spin_unlock_irqrestore(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) static void bcm2835_dma_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) spin_lock_irqsave(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (vchan_issue_pending(&c->vc) && !c->desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) bcm2835_dma_start_desc(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) spin_unlock_irqrestore(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) struct dma_chan *chan, dma_addr_t dst, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct bcm2835_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u32 info = BCM2835_DMA_D_INC | BCM2835_DMA_S_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u32 extra = BCM2835_DMA_INT_EN | BCM2835_DMA_WAIT_RESP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) size_t max_len = bcm2835_dma_max_frame_length(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) size_t frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /* if src, dst or len is not given return with an error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) if (!src || !dst || !len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /* calculate number of frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) frames = bcm2835_dma_frames_for_length(len, max_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) /* allocate the CB chain - this also fills in the pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) d = bcm2835_dma_create_cb_chain(chan, DMA_MEM_TO_MEM, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) info, extra, frames,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) src, dst, len, 0, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return vchan_tx_prep(&c->vc, &d->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) static struct dma_async_tx_descriptor *bcm2835_dma_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) struct scatterlist *sgl, unsigned int sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) unsigned long flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) struct bcm2835_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) dma_addr_t src = 0, dst = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) u32 info = BCM2835_DMA_WAIT_RESP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) u32 extra = BCM2835_DMA_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) size_t frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) if (!is_slave_direction(direction)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) dev_err(chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) "%s: bad direction?\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (c->dreq != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) info |= BCM2835_DMA_PER_MAP(c->dreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (direction == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) src = c->cfg.src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) dst = c->cfg.dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) /* count frames in sg list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) frames = bcm2835_dma_count_frames_for_sg(c, sgl, sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /* allocate the CB chain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) d = bcm2835_dma_create_cb_chain(chan, direction, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) info, extra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) frames, src, dst, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /* fill in frames with scatterlist pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) bcm2835_dma_fill_cb_chain_with_sg(chan, direction, d->cb_list,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) sgl, sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return vchan_tx_prep(&c->vc, &d->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static struct dma_async_tx_descriptor *bcm2835_dma_prep_dma_cyclic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) size_t period_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct bcm2835_dmadev *od = to_bcm2835_dma_dev(chan->device);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) struct bcm2835_desc *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) dma_addr_t src, dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) u32 info = BCM2835_DMA_WAIT_RESP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) u32 extra = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) size_t max_len = bcm2835_dma_max_frame_length(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) size_t frames;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* Grab configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) if (!is_slave_direction(direction)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) dev_err(chan->device->dev, "%s: bad direction?\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) if (!buf_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) dev_err(chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) "%s: bad buffer length (= 0)\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) if (flags & DMA_PREP_INTERRUPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) extra |= BCM2835_DMA_INT_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) period_len = buf_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) * warn if buf_len is not a multiple of period_len - this may leed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) * to unexpected latencies for interrupts and thus audiable clicks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) if (buf_len % period_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) dev_warn_once(chan->device->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) "%s: buffer_length (%zd) is not a multiple of period_len (%zd)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) __func__, buf_len, period_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) /* Setup DREQ channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) if (c->dreq != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) info |= BCM2835_DMA_PER_MAP(c->dreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) if (direction == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) if (c->cfg.src_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) src = c->cfg.src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) dst = buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) info |= BCM2835_DMA_S_DREQ | BCM2835_DMA_D_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (c->cfg.dst_addr_width != DMA_SLAVE_BUSWIDTH_4_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) dst = c->cfg.dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) src = buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) info |= BCM2835_DMA_D_DREQ | BCM2835_DMA_S_INC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /* non-lite channels can write zeroes w/o accessing memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) if (buf_addr == od->zero_page && !c->is_lite_channel)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) info |= BCM2835_DMA_S_IGNORE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /* calculate number of frames */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) frames = /* number of periods */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) DIV_ROUND_UP(buf_len, period_len) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /* number of frames per period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) bcm2835_dma_frames_for_length(period_len, max_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) * allocate the CB chain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * note that we need to use GFP_NOWAIT, as the ALSA i2s dmaengine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * implementation calls prep_dma_cyclic with interrupts disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) d = bcm2835_dma_create_cb_chain(chan, direction, true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) info, extra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) frames, src, dst, buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) period_len, GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) if (!d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) /* wrap around into a loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) d->cb_list[d->frames - 1].cb->next = d->cb_list[0].paddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return vchan_tx_prep(&c->vc, &d->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) static int bcm2835_dma_slave_config(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) struct dma_slave_config *cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) c->cfg = *cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) static int bcm2835_dma_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) spin_lock_irqsave(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) /* stop DMA activity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) if (c->desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) vchan_terminate_vdesc(&c->desc->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) c->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) bcm2835_dma_abort(c);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) vchan_get_all_descriptors(&c->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) spin_unlock_irqrestore(&c->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) vchan_dma_desc_free_list(&c->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) static void bcm2835_dma_synchronize(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct bcm2835_chan *c = to_bcm2835_dma_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) vchan_synchronize(&c->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static int bcm2835_dma_chan_init(struct bcm2835_dmadev *d, int chan_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) int irq, unsigned int irq_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) struct bcm2835_chan *c;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) c = devm_kzalloc(d->ddev.dev, sizeof(*c), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (!c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) c->vc.desc_free = bcm2835_dma_desc_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) vchan_init(&c->vc, &d->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) c->chan_base = BCM2835_DMA_CHANIO(d->base, chan_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) c->ch = chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) c->irq_number = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) c->irq_flags = irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) /* check in DEBUG register if this is a LITE channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) if (readl(c->chan_base + BCM2835_DMA_DEBUG) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) BCM2835_DMA_DEBUG_LITE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) c->is_lite_channel = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) static void bcm2835_dma_free(struct bcm2835_dmadev *od)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) struct bcm2835_chan *c, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) list_for_each_entry_safe(c, next, &od->ddev.channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) vc.chan.device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) list_del(&c->vc.chan.device_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) tasklet_kill(&c->vc.task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dma_unmap_page_attrs(od->ddev.dev, od->zero_page, PAGE_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) DMA_TO_DEVICE, DMA_ATTR_SKIP_CPU_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) static const struct of_device_id bcm2835_dma_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) { .compatible = "brcm,bcm2835-dma", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) MODULE_DEVICE_TABLE(of, bcm2835_dma_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static struct dma_chan *bcm2835_dma_xlate(struct of_phandle_args *spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) struct bcm2835_dmadev *d = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) chan = dma_get_any_slave_channel(&d->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /* Set DREQ from param */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) to_bcm2835_dma_chan(chan)->dreq = spec->args[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) return chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) static int bcm2835_dma_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct bcm2835_dmadev *od;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) int rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) int irq[BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) int irq_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) uint32_t chans_available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) char chan_name[BCM2835_DMA_CHAN_NAME_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (!pdev->dev.dma_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) pdev->dev.dma_mask = &pdev->dev.coherent_dma_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) dev_err(&pdev->dev, "Unable to set DMA mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) od = devm_kzalloc(&pdev->dev, sizeof(*od), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (!od)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dma_set_max_seg_size(&pdev->dev, 0x3FFFFFFF);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) base = devm_ioremap_resource(&pdev->dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) if (IS_ERR(base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return PTR_ERR(base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) od->base = base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) dma_cap_set(DMA_SLAVE, od->ddev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) dma_cap_set(DMA_PRIVATE, od->ddev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) dma_cap_set(DMA_CYCLIC, od->ddev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dma_cap_set(DMA_MEMCPY, od->ddev.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) od->ddev.device_alloc_chan_resources = bcm2835_dma_alloc_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) od->ddev.device_free_chan_resources = bcm2835_dma_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) od->ddev.device_tx_status = bcm2835_dma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) od->ddev.device_issue_pending = bcm2835_dma_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) od->ddev.device_prep_dma_cyclic = bcm2835_dma_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) od->ddev.device_prep_slave_sg = bcm2835_dma_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) od->ddev.device_prep_dma_memcpy = bcm2835_dma_prep_dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) od->ddev.device_config = bcm2835_dma_slave_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) od->ddev.device_terminate_all = bcm2835_dma_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) od->ddev.device_synchronize = bcm2835_dma_synchronize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) od->ddev.src_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) od->ddev.dst_addr_widths = BIT(DMA_SLAVE_BUSWIDTH_4_BYTES);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) od->ddev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) BIT(DMA_MEM_TO_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) od->ddev.residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) od->ddev.descriptor_reuse = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) od->ddev.dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) INIT_LIST_HEAD(&od->ddev.channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) platform_set_drvdata(pdev, od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) od->zero_page = dma_map_page_attrs(od->ddev.dev, ZERO_PAGE(0), 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) PAGE_SIZE, DMA_TO_DEVICE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) DMA_ATTR_SKIP_CPU_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (dma_mapping_error(od->ddev.dev, od->zero_page)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) dev_err(&pdev->dev, "Failed to map zero page\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) /* Request DMA channel mask from device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (of_property_read_u32(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) "brcm,dma-channel-mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) &chans_available)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) dev_err(&pdev->dev, "Failed to get channel mask\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) rc = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) goto err_no_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* get irqs for each channel that we support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* skip masked out channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (!(chans_available & (1 << i))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) irq[i] = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /* get the named irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) snprintf(chan_name, sizeof(chan_name), "dma%i", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) irq[i] = platform_get_irq_byname(pdev, chan_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (irq[i] >= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) /* legacy device tree case handling */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dev_warn_once(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) "missing interrupt-names property in device tree - legacy interpretation is used\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) * in case of channel >= 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) * use the 11th interrupt and that is shared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) irq[i] = platform_get_irq(pdev, i < 11 ? i : 11);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) /* get irqs for each channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) for (i = 0; i <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) /* skip channels without irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (irq[i] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) /* check if there are other channels that also use this irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) irq_flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) for (j = 0; j <= BCM2835_DMA_MAX_DMA_CHAN_SUPPORTED; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if ((i != j) && (irq[j] == irq[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) irq_flags = IRQF_SHARED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) /* initialize the channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) rc = bcm2835_dma_chan_init(od, i, irq[i], irq_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) if (rc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) goto err_no_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) dev_dbg(&pdev->dev, "Initialized %i DMA channels\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) /* Device-tree DMA controller registration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) rc = of_dma_controller_register(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) bcm2835_dma_xlate, od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dev_err(&pdev->dev, "Failed to register DMA controller\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) goto err_no_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) rc = dma_async_device_register(&od->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) if (rc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) "Failed to register slave DMA engine device: %d\n", rc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) goto err_no_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) dev_dbg(&pdev->dev, "Load BCM2835 DMA engine driver\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) err_no_dma:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) bcm2835_dma_free(od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) return rc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) static int bcm2835_dma_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct bcm2835_dmadev *od = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dma_async_device_unregister(&od->ddev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) bcm2835_dma_free(od);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) static struct platform_driver bcm2835_dma_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) .probe = bcm2835_dma_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) .remove = bcm2835_dma_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) .name = "bcm2835-dma",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) .of_match_table = of_match_ptr(bcm2835_dma_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) module_platform_driver(bcm2835_dma_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) MODULE_ALIAS("platform:bcm2835-dma");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) MODULE_DESCRIPTION("BCM2835 DMA engine driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) MODULE_AUTHOR("Florian Meier <florian.meier@koalo.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags