^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2006 ARM Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (c) 2010 ST-Ericsson SA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyirght (c) 2017 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Peter Pearse <peter.pearse@arm.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Linus Walleij <linus.walleij@linaro.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Documentation: ARM DDI 0196G == PL080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Documentation: ARM DDI 0218E == PL081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Documentation: S3C6410 User's Manual == PL080S
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * PL080 & PL081 both have 16 sets of DMA signals that can be routed to any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * The PL080 has 8 channels available for simultaneous use, and the PL081
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * has only two channels. So on these DMA controllers the number of channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * and the number of incoming DMA signals are two totally different things.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * It is usually not possible to theoretically handle all physical signals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * so a multiplexing scheme with possible denial of use is necessary.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * The PL080 has a dual bus master, PL081 has a single master.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * PL080S is a version modified by Samsung and used in S3C64xx SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * It differs in following aspects:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * - CH_CONFIG register at different offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * - separate CH_CONTROL2 register for transfer size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * - bigger maximum transfer size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * - 8-word aligned LLI, instead of 4-word, due to extra CCTL2 word,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * - no support for peripheral flow control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * Memory to peripheral transfer may be visualized as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * Get data from memory to DMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * Until no data left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * On burst request from peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * Destination burst from DMAC to peripheral
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * Clear burst request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * Raise terminal count interrupt
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * For peripherals with a FIFO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * Source burst size == half the depth of the peripheral FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * Destination burst size == the depth of the peripheral FIFO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * (Bursts are irrelevant for mem to mem transfers - there are no burst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * signals, the DMA controller will simply facilitate its AHB master.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * ASSUMES default (little) endianness for DMA transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * The PL08x has two flow control settings:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * - DMAC flow control: the transfer size defines the number of transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * which occur for the current LLI entry, and the DMAC raises TC at the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * end of every LLI entry. Observed behaviour shows the DMAC listening
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * to both the BREQ and SREQ signals (contrary to documented),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * transferring data if either is active. The LBREQ and LSREQ signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * are ignored.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * - Peripheral flow control: the transfer size is ignored (and should be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * zero). The data is transferred from the current LLI entry, until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * after the final transfer signalled by LBREQ or LSREQ. The DMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * will then move to the next LLI entry. Unsupported by PL080S.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #include <linux/amba/bus.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #include <linux/amba/pl08x.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #include <linux/export.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #include <linux/of_dma.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #include <linux/amba/pl080.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #include "dmaengine.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #include "virt-dma.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DRIVER_NAME "pl08xdmac"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PL80X_DMA_BUSWIDTHS \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) BIT(DMA_SLAVE_BUSWIDTH_UNDEFINED) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) BIT(DMA_SLAVE_BUSWIDTH_4_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) static struct amba_driver pl08x_amba_driver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct pl08x_driver_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * struct vendor_data - vendor-specific config parameters for PL08x derivatives
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @config_offset: offset to the configuration register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @channels: the number of channels available in this variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @signals: the number of request signals available from the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @dualmaster: whether this version supports dual AHB masters or not.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @nomadik: whether this variant is a ST Microelectronics Nomadik, where the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * channels have Nomadik security extension bits that need to be checked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * for permission before use and some registers are missing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @pl080s: whether this variant is a Samsung PL080S, which has separate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * register and LLI word for transfer size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @ftdmac020: whether this variant is a Faraday Technology FTDMAC020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @max_transfer_size: the maximum single element transfer size for this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * PL08x variant.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct vendor_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u8 config_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u8 channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u8 signals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) bool dualmaster;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) bool nomadik;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) bool pl080s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) bool ftdmac020;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 max_transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * struct pl08x_bus_data - information of source or destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * busses for a transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * @addr: current address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @maxwidth: the maximum width of a transfer on this bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @buswidth: the width of this bus in bytes: 1, 2 or 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) struct pl08x_bus_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u8 maxwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u8 buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IS_BUS_ALIGNED(bus) IS_ALIGNED((bus)->addr, (bus)->buswidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * struct pl08x_phy_chan - holder for the physical channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @id: physical index to this channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @base: memory base address for this physical channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @reg_config: configuration address for this physical channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @reg_control: control address for this physical channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @reg_src: transfer source address register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * @reg_dst: transfer destination address register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @reg_lli: transfer LLI address register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @reg_busy: if the variant has a special per-channel busy register,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * this contains a pointer to it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @lock: a lock to use when altering an instance of this struct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @serving: the virtual channel currently being served by this physical
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @locked: channel unavailable for the system, e.g. dedicated to secure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) * world
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @ftdmac020: channel is on a FTDMAC020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @pl080s: channel is on a PL08s
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct pl08x_phy_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) unsigned int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) void __iomem *reg_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) void __iomem *reg_control;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void __iomem *reg_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) void __iomem *reg_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) void __iomem *reg_lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) void __iomem *reg_busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct pl08x_dma_chan *serving;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) bool locked;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) bool ftdmac020;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) bool pl080s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * struct pl08x_sg - structure containing data per sg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @src_addr: src address of sg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @dst_addr: dst address of sg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @len: transfer len in bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @node: node for txd's dsg_list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) struct pl08x_sg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) dma_addr_t src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) dma_addr_t dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct list_head node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * struct pl08x_txd - wrapper for struct dma_async_tx_descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @vd: virtual DMA descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @dsg_list: list of children sg's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @llis_bus: DMA memory address (physical) start for the LLIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @llis_va: virtual memory address start for the LLIs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @cctl: control reg values for current txd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @ccfg: config reg values for current txd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @done: this marks completed descriptors, which should not have their
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * mux released.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @cyclic: indicate cyclic transfers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct pl08x_txd {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct virt_dma_desc vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct list_head dsg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) dma_addr_t llis_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 *llis_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) /* Default cctl value for LLIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 cctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * Settings to be put into the physical channel when we
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * trigger this txd. Other registers are in llis_va[0].
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 ccfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) bool done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) bool cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * enum pl08x_dma_chan_state - holds the PL08x specific virtual channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * states
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @PL08X_CHAN_IDLE: the channel is idle
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @PL08X_CHAN_RUNNING: the channel has allocated a physical transport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * channel and is running a transfer on it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @PL08X_CHAN_PAUSED: the channel has allocated a physical transport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * channel, but the transfer is currently paused
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @PL08X_CHAN_WAITING: the channel is waiting for a physical transport
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * channel to become available (only pertains to memcpy channels)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) enum pl08x_dma_chan_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) PL08X_CHAN_IDLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) PL08X_CHAN_RUNNING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) PL08X_CHAN_PAUSED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) PL08X_CHAN_WAITING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * struct pl08x_dma_chan - this structure wraps a DMA ENGINE channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @vc: wrappped virtual channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @phychan: the physical channel utilized by this channel, if there is one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @name: name of channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @cd: channel platform data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @cfg: slave configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * @at: active transaction on this channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @host: a pointer to the host (internal use)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * @state: whether the channel is idle, paused, running etc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @slave: whether this channel is a device (slave) or for memcpy
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @signal: the physical DMA request signal which this channel is using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @mux_use: count of descriptors using this DMA request signal setting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * @waiting_at: time in jiffies when this channel moved to waiting state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct pl08x_dma_chan {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) struct virt_dma_chan vc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct pl08x_phy_chan *phychan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct pl08x_channel_data *cd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct pl08x_txd *at;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) struct pl08x_driver_data *host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) enum pl08x_dma_chan_state state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) bool slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int signal;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) unsigned mux_use;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) unsigned long waiting_at;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * struct pl08x_driver_data - the local state holder for the PL08x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * @slave: optional slave engine for this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * @memcpy: memcpy engine for this instance
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * @has_slave: the PL08x has a slave engine (routed signals)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) * @base: virtual memory base (remapped) for the PL08x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * @adev: the corresponding AMBA (PrimeCell) bus entry
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @vd: vendor data for this PL08x variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * @pd: platform data passed in from the platform/machine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * @phy_chans: array of data for the physical channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * @pool: a pool for the LLI descriptors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @lli_buses: bitmask to or in to LLI pointer selecting AHB port for LLI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * fetches
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * @mem_buses: set to indicate memory transfers on AHB2.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) * @lli_words: how many words are used in each LLI item for this variant
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct pl08x_driver_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) struct dma_device slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) struct dma_device memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) bool has_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) struct amba_device *adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) const struct vendor_data *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) struct pl08x_platform_data *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct pl08x_phy_chan *phy_chans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) struct dma_pool *pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) u8 lli_buses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) u8 mem_buses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u8 lli_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * PL08X specific defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /* The order of words in an LLI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define PL080_LLI_SRC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define PL080_LLI_DST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define PL080_LLI_LLI 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define PL080_LLI_CCTL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define PL080S_LLI_CCTL2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* Total words in an LLI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define PL080_LLI_WORDS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define PL080S_LLI_WORDS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * Number of LLIs in each LLI buffer allocated for one transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * (maximum times we call dma_pool_alloc on this pool without freeing)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define MAX_NUM_TSFR_LLIS 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define PL08X_ALIGN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) static inline struct pl08x_dma_chan *to_pl08x_chan(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) return container_of(chan, struct pl08x_dma_chan, vc.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) static inline struct pl08x_txd *to_pl08x_txd(struct dma_async_tx_descriptor *tx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) return container_of(tx, struct pl08x_txd, vd.tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * Mux handling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * This gives us the DMA request input to the PL08x primecell which the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * peripheral described by the channel data will be routed to, possibly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * via a board/SoC specific external MUX. One important point to note
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * here is that this does not depend on the physical channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) static int pl08x_request_mux(struct pl08x_dma_chan *plchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) const struct pl08x_platform_data *pd = plchan->host->pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (plchan->mux_use++ == 0 && pd->get_xfer_signal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) ret = pd->get_xfer_signal(plchan->cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) plchan->mux_use = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) plchan->signal = ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) static void pl08x_release_mux(struct pl08x_dma_chan *plchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) const struct pl08x_platform_data *pd = plchan->host->pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (plchan->signal >= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) WARN_ON(plchan->mux_use == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) if (--plchan->mux_use == 0 && pd->put_xfer_signal) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) pd->put_xfer_signal(plchan->cd, plchan->signal);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) plchan->signal = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) * Physical channel handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* Whether a certain channel is busy or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) static int pl08x_phy_channel_busy(struct pl08x_phy_chan *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* If we have a special busy register, take a shortcut */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (ch->reg_busy) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) val = readl(ch->reg_busy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) return !!(val & BIT(ch->id));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) val = readl(ch->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return val & PL080_CONFIG_ACTIVE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) * pl08x_write_lli() - Write an LLI into the DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * The PL08x derivatives support linked lists, but the first item of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) * list containing the source, destination, control word and next LLI is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) * ignored. Instead the driver has to write those values directly into the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * SRC, DST, LLI and control registers. On FTDMAC020 also the SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * register need to be set up for the first transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) static void pl08x_write_lli(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) struct pl08x_phy_chan *phychan, const u32 *lli, u32 ccfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (pl08x->vd->pl080s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) dev_vdbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) "clli=0x%08x, cctl=0x%08x, cctl2=0x%08x, ccfg=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) lli[PL080S_LLI_CCTL2], ccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_vdbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) "WRITE channel %d: csrc=0x%08x, cdst=0x%08x, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) "clli=0x%08x, cctl=0x%08x, ccfg=0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) lli[PL080_LLI_LLI], lli[PL080_LLI_CCTL], ccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) writel_relaxed(lli[PL080_LLI_SRC], phychan->reg_src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) writel_relaxed(lli[PL080_LLI_DST], phychan->reg_dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) writel_relaxed(lli[PL080_LLI_LLI], phychan->reg_lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) * The FTMAC020 has a different layout in the CCTL word of the LLI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * and the CCTL register which is split in CSR and SIZE registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) * Convert the LLI item CCTL into the proper values to write into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) * the CSR and SIZE registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (phychan->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) u32 llictl = lli[PL080_LLI_CCTL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) /* Write the transfer size (12 bits) to the size register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) writel_relaxed(llictl & FTDMAC020_LLI_TRANSFER_SIZE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) phychan->base + FTDMAC020_CH_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) * Then write the control bits 28..16 to the control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * by shuffleing the bits around to where they are in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * main register. The mapping is as follows:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * Bit 28: TC_MSK - mask on all except last LLI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * Bit 27..25: SRC_WIDTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * Bit 24..22: DST_WIDTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * Bit 21..20: SRCAD_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * Bit 19..17: DSTAD_CTRL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * Bit 17: SRC_SEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * Bit 16: DST_SEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) if (llictl & FTDMAC020_LLI_TC_MSK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) val |= FTDMAC020_CH_CSR_TC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) val |= ((llictl & FTDMAC020_LLI_SRC_WIDTH_MSK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) (FTDMAC020_LLI_SRC_WIDTH_SHIFT -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) val |= ((llictl & FTDMAC020_LLI_DST_WIDTH_MSK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) (FTDMAC020_LLI_DST_WIDTH_SHIFT -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) FTDMAC020_CH_CSR_DST_WIDTH_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) val |= ((llictl & FTDMAC020_LLI_SRCAD_CTL_MSK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) (FTDMAC020_LLI_SRCAD_CTL_SHIFT -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) FTDMAC020_CH_CSR_SRCAD_CTL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) val |= ((llictl & FTDMAC020_LLI_DSTAD_CTL_MSK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) (FTDMAC020_LLI_DSTAD_CTL_SHIFT -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) FTDMAC020_CH_CSR_DSTAD_CTL_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (llictl & FTDMAC020_LLI_SRC_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) val |= FTDMAC020_CH_CSR_SRC_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) if (llictl & FTDMAC020_LLI_DST_SEL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) val |= FTDMAC020_CH_CSR_DST_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) * Set up the bits that exist in the CSR but are not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * part the LLI, i.e. only gets written to the control
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) * register right here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * FIXME: do not just handle memcpy, also handle slave DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) switch (pl08x->pd->memcpy_burst_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) case PL08X_BURST_SZ_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) val |= PL080_BSIZE_1 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) case PL08X_BURST_SZ_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) val |= PL080_BSIZE_4 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) case PL08X_BURST_SZ_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) val |= PL080_BSIZE_8 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) case PL08X_BURST_SZ_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) val |= PL080_BSIZE_16 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) case PL08X_BURST_SZ_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) val |= PL080_BSIZE_32 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) case PL08X_BURST_SZ_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) val |= PL080_BSIZE_64 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) case PL08X_BURST_SZ_128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) val |= PL080_BSIZE_128 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) case PL08X_BURST_SZ_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) val |= PL080_BSIZE_256 <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) FTDMAC020_CH_CSR_SRC_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /* Protection flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) if (pl08x->pd->memcpy_prot_buff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) val |= FTDMAC020_CH_CSR_PROT2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) if (pl08x->pd->memcpy_prot_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) val |= FTDMAC020_CH_CSR_PROT3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /* We are the kernel, so we are in privileged mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) val |= FTDMAC020_CH_CSR_PROT1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) writel_relaxed(val, phychan->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /* Bits are just identical */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) writel_relaxed(lli[PL080_LLI_CCTL], phychan->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Second control word on the PL080s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (pl08x->vd->pl080s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) writel_relaxed(lli[PL080S_LLI_CCTL2],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) phychan->base + PL080S_CH_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) writel(ccfg, phychan->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) * Set the initial DMA register values i.e. those for the first LLI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * The next LLI pointer and the configuration interrupt bit have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * been set when the LLIs were constructed. Poke them into the hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) * and start the transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) static void pl08x_start_next_txd(struct pl08x_dma_chan *plchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct pl08x_driver_data *pl08x = plchan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct pl08x_phy_chan *phychan = plchan->phychan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct virt_dma_desc *vd = vchan_next_desc(&plchan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) list_del(&txd->vd.node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) plchan->at = txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /* Wait for channel inactive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) while (pl08x_phy_channel_busy(phychan))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) pl08x_write_lli(pl08x, phychan, &txd->llis_va[0], txd->ccfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /* Enable the DMA channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) /* Do not access config register until channel shows as disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) while (readl(pl08x->base + PL080_EN_CHAN) & BIT(phychan->id))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /* Do not access config register until channel shows as inactive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) if (phychan->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) val = readl(phychan->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) while (val & FTDMAC020_CH_CFG_BUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) val = readl(phychan->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) val = readl(phychan->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) while (val & FTDMAC020_CH_CSR_EN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) val = readl(phychan->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) writel(val | FTDMAC020_CH_CSR_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) phychan->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) val = readl(phychan->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) while ((val & PL080_CONFIG_ACTIVE) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) (val & PL080_CONFIG_ENABLE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) val = readl(phychan->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) writel(val | PL080_CONFIG_ENABLE, phychan->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) * Pause the channel by setting the HALT bit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * For M->P transfers, pause the DMAC first and then stop the peripheral -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) * the FIFO can only drain if the peripheral is still requesting data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * (note: this can still timeout if the DMAC FIFO never drains of data.)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) * For P->M transfers, disable the peripheral first to stop it filling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) * the DMAC FIFO, and then pause the DMAC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static void pl08x_pause_phy_chan(struct pl08x_phy_chan *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) int timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) if (ch->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* Use the enable bit on the FTDMAC020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) val = readl(ch->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) val &= ~FTDMAC020_CH_CSR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) writel(val, ch->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /* Set the HALT bit and wait for the FIFO to drain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) val = readl(ch->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) val |= PL080_CONFIG_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) writel(val, ch->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) /* Wait for channel inactive */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) for (timeout = 1000; timeout; timeout--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) if (!pl08x_phy_channel_busy(ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) if (pl08x_phy_channel_busy(ch))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) static void pl08x_resume_phy_chan(struct pl08x_phy_chan *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) /* Use the enable bit on the FTDMAC020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (ch->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) val = readl(ch->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) val |= FTDMAC020_CH_CSR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) writel(val, ch->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) /* Clear the HALT bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) val = readl(ch->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) val &= ~PL080_CONFIG_HALT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) writel(val, ch->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) * pl08x_terminate_phy_chan() stops the channel, clears the FIFO and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) * clears any pending interrupt status. This should not be used for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) * an on-going transfer, but as a method of shutting down a channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) * (eg, when it's no longer used) or terminating a transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) struct pl08x_phy_chan *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /* The layout for the FTDMAC020 is different */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (ch->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /* Disable all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) val = readl(ch->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) val |= (FTDMAC020_CH_CFG_INT_ABT_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) FTDMAC020_CH_CFG_INT_ERR_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) FTDMAC020_CH_CFG_INT_TC_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) writel(val, ch->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) /* Abort and disable channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) val = readl(ch->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) val &= ~FTDMAC020_CH_CSR_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) val |= FTDMAC020_CH_CSR_ABT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) writel(val, ch->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* Clear ABT and ERR interrupt flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) writel(BIT(ch->id) | BIT(ch->id + 16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) pl08x->base + PL080_ERR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) val = readl(ch->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) PL080_CONFIG_TC_IRQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) writel(val, ch->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) writel(BIT(ch->id), pl08x->base + PL080_ERR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static u32 get_bytes_in_phy_channel(struct pl08x_phy_chan *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) if (ch->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) bytes = readl(ch->base + FTDMAC020_CH_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) val = readl(ch->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) val &= FTDMAC020_CH_CSR_SRC_WIDTH_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) val >>= FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) } else if (ch->pl080s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) val = readl(ch->base + PL080S_CH_CONTROL2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) bytes = val & PL080S_CONTROL_TRANSFER_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) val = readl(ch->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) val &= PL080_CONTROL_SWIDTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) val >>= PL080_CONTROL_SWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) /* Plain PL08x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) val = readl(ch->reg_control);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) bytes = val & PL080_CONTROL_TRANSFER_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) val &= PL080_CONTROL_SWIDTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) val >>= PL080_CONTROL_SWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) case PL080_WIDTH_8BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) case PL080_WIDTH_16BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) bytes *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) case PL080_WIDTH_32BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) bytes *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) return bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static u32 get_bytes_in_lli(struct pl08x_phy_chan *ch, const u32 *llis_va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) u32 bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) if (ch->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) val = llis_va[PL080_LLI_CCTL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) bytes = val & FTDMAC020_LLI_TRANSFER_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) val = llis_va[PL080_LLI_CCTL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) val &= FTDMAC020_LLI_SRC_WIDTH_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) val >>= FTDMAC020_LLI_SRC_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) } else if (ch->pl080s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) val = llis_va[PL080S_LLI_CCTL2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) bytes = val & PL080S_CONTROL_TRANSFER_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) val = llis_va[PL080_LLI_CCTL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) val &= PL080_CONTROL_SWIDTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) val >>= PL080_CONTROL_SWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* Plain PL08x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) val = llis_va[PL080_LLI_CCTL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) bytes = val & PL080_CONTROL_TRANSFER_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) val &= PL080_CONTROL_SWIDTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) val >>= PL080_CONTROL_SWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) case PL080_WIDTH_8BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) case PL080_WIDTH_16BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) bytes *= 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) case PL080_WIDTH_32BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) bytes *= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) return bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) /* The channel should be paused when calling this */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static u32 pl08x_getbytes_chan(struct pl08x_dma_chan *plchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct pl08x_driver_data *pl08x = plchan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) const u32 *llis_va, *llis_va_limit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) struct pl08x_phy_chan *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) dma_addr_t llis_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct pl08x_txd *txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) u32 llis_max_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) size_t bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) u32 clli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) ch = plchan->phychan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) txd = plchan->at;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) if (!ch || !txd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * Follow the LLIs to get the number of remaining
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * bytes in the currently active transaction.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) clli = readl(ch->reg_lli) & ~PL080_LLI_LM_AHB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /* First get the remaining bytes in the active transfer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) bytes = get_bytes_in_phy_channel(ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) if (!clli)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) return bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) llis_va = txd->llis_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) llis_bus = txd->llis_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) llis_max_words = pl08x->lli_words * MAX_NUM_TSFR_LLIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) BUG_ON(clli < llis_bus || clli >= llis_bus +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) sizeof(u32) * llis_max_words);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) * Locate the next LLI - as this is an array,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) * it's simple maths to find.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) llis_va += (clli - llis_bus) / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) llis_va_limit = llis_va + llis_max_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) for (; llis_va < llis_va_limit; llis_va += pl08x->lli_words) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) bytes += get_bytes_in_lli(ch, llis_va);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) * A LLI pointer going backward terminates the LLI list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (llis_va[PL080_LLI_LLI] <= clli)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) return bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) * Allocate a physical channel for a virtual channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) * Try to locate a physical channel to be used for this transfer. If all
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) * are taken return NULL and the requester will have to cope by using
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) * some fallback PIO mode or retrying later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) static struct pl08x_phy_chan *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct pl08x_dma_chan *virt_chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) struct pl08x_phy_chan *ch = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) for (i = 0; i < pl08x->vd->channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) ch = &pl08x->phy_chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) spin_lock_irqsave(&ch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (!ch->locked && !ch->serving) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ch->serving = virt_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) spin_unlock_irqrestore(&ch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) spin_unlock_irqrestore(&ch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (i == pl08x->vd->channels) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) /* No physical channel available, cope with it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) return ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) /* Mark the physical channel as free. Note, this write is atomic. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct pl08x_phy_chan *ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) ch->serving = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) * Try to allocate a physical channel. When successful, assign it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) * this virtual channel, and initiate the next descriptor. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) * virtual channel lock must be held at this point.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static void pl08x_phy_alloc_and_start(struct pl08x_dma_chan *plchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) struct pl08x_driver_data *pl08x = plchan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) struct pl08x_phy_chan *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) ch = pl08x_get_phy_channel(pl08x, plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) if (!ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) plchan->state = PL08X_CHAN_WAITING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) plchan->waiting_at = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) ch->id, plchan->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) plchan->phychan = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) plchan->state = PL08X_CHAN_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) pl08x_start_next_txd(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static void pl08x_phy_reassign_start(struct pl08x_phy_chan *ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct pl08x_dma_chan *plchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) struct pl08x_driver_data *pl08x = plchan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) ch->id, plchan->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) * We do this without taking the lock; we're really only concerned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) * about whether this pointer is NULL or not, and we're guaranteed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) * that this will only be called when it _already_ is non-NULL.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) ch->serving = plchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) plchan->phychan = ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) plchan->state = PL08X_CHAN_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) pl08x_start_next_txd(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) * Free a physical DMA channel, potentially reallocating it to another
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) * virtual channel if we have any pending.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) static void pl08x_phy_free(struct pl08x_dma_chan *plchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) struct pl08x_driver_data *pl08x = plchan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) struct pl08x_dma_chan *p, *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) unsigned long waiting_at;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) retry:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) next = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) waiting_at = jiffies;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * Find a waiting virtual channel for the next transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) * To be fair, time when each channel reached waiting state is compared
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * to select channel that is waiting for the longest time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) if (p->state == PL08X_CHAN_WAITING &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) p->waiting_at <= waiting_at) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) next = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) waiting_at = p->waiting_at;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) if (!next && pl08x->has_slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (p->state == PL08X_CHAN_WAITING &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) p->waiting_at <= waiting_at) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) next = p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) waiting_at = p->waiting_at;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /* Ensure that the physical channel is stopped */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) pl08x_terminate_phy_chan(pl08x, plchan->phychan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) if (next) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) bool success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) * Eww. We know this isn't going to deadlock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) * but lockdep probably doesn't.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) spin_lock(&next->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) /* Re-check the state now that we have the lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) success = next->state == PL08X_CHAN_WAITING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) if (success)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) pl08x_phy_reassign_start(plchan->phychan, next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) spin_unlock(&next->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) /* If the state changed, try to find another channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) if (!success)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) goto retry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) /* No more jobs, so free up the physical channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) pl08x_put_phy_channel(pl08x, plchan->phychan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) plchan->phychan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) plchan->state = PL08X_CHAN_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) * LLI handling
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) pl08x_get_bytes_for_lli(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u32 cctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) bool source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) if (pl08x->vd->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) val = (cctl & FTDMAC020_LLI_SRC_WIDTH_MSK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) FTDMAC020_LLI_SRC_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) val = (cctl & FTDMAC020_LLI_DST_WIDTH_MSK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) FTDMAC020_LLI_DST_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) if (source)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) val = (cctl & PL080_CONTROL_SWIDTH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) PL080_CONTROL_SWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) val = (cctl & PL080_CONTROL_DWIDTH_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) PL080_CONTROL_DWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) case PL080_WIDTH_8BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) case PL080_WIDTH_16BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) case PL080_WIDTH_32BIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) static inline u32 pl08x_lli_control_bits(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) u32 cctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) u8 srcwidth, u8 dstwidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) size_t tsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) u32 retbits = cctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) * Remove all src, dst and transfer size bits, then set the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) * width and size according to the parameters. The bit offsets
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) * are different in the FTDMAC020 so we need to accound for this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) if (pl08x->vd->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) retbits &= ~FTDMAC020_LLI_DST_WIDTH_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) retbits &= ~FTDMAC020_LLI_SRC_WIDTH_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) retbits &= ~FTDMAC020_LLI_TRANSFER_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) switch (srcwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) retbits |= PL080_WIDTH_8BIT <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) FTDMAC020_LLI_SRC_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) retbits |= PL080_WIDTH_16BIT <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) FTDMAC020_LLI_SRC_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) retbits |= PL080_WIDTH_32BIT <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) FTDMAC020_LLI_SRC_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) switch (dstwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) retbits |= PL080_WIDTH_8BIT <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) FTDMAC020_LLI_DST_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) retbits |= PL080_WIDTH_16BIT <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) FTDMAC020_LLI_DST_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) retbits |= PL080_WIDTH_32BIT <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) FTDMAC020_LLI_DST_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) tsize &= FTDMAC020_LLI_TRANSFER_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) retbits |= tsize << FTDMAC020_LLI_TRANSFER_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) retbits &= ~PL080_CONTROL_DWIDTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) retbits &= ~PL080_CONTROL_SWIDTH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) retbits &= ~PL080_CONTROL_TRANSFER_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) switch (srcwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) retbits |= PL080_WIDTH_8BIT <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) PL080_CONTROL_SWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) retbits |= PL080_WIDTH_16BIT <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) PL080_CONTROL_SWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) retbits |= PL080_WIDTH_32BIT <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) PL080_CONTROL_SWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) switch (dstwidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) retbits |= PL080_WIDTH_8BIT <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) PL080_CONTROL_DWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) case 2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) retbits |= PL080_WIDTH_16BIT <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) PL080_CONTROL_DWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) retbits |= PL080_WIDTH_32BIT <<
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) PL080_CONTROL_DWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) tsize &= PL080_CONTROL_TRANSFER_SIZE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) retbits |= tsize << PL080_CONTROL_TRANSFER_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) return retbits;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct pl08x_lli_build_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) struct pl08x_txd *txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) struct pl08x_bus_data srcbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) struct pl08x_bus_data dstbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) size_t remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) u32 lli_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) * Autoselect a master bus to use for the transfer. Slave will be the chosen as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) * victim in case src & dest are not similarly aligned. i.e. If after aligning
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) * masters address with width requirements of transfer (by sending few byte by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) * byte data), slave is still not aligned, then its width will be reduced to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) * BYTE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) * - prefers the destination bus if both available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) * - prefers bus with fixed address (i.e. peripheral)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static void pl08x_choose_master_bus(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) struct pl08x_lli_build_data *bd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) struct pl08x_bus_data **mbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) struct pl08x_bus_data **sbus,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) u32 cctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) bool dst_incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) bool src_incr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) * The FTDMAC020 only supports memory-to-memory transfer, so
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) * source and destination always increase.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (pl08x->vd->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) dst_incr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) src_incr = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) dst_incr = !!(cctl & PL080_CONTROL_DST_INCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) src_incr = !!(cctl & PL080_CONTROL_SRC_INCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) * If either bus is not advancing, i.e. it is a peripheral, that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) * one becomes master
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (!dst_incr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) *mbus = &bd->dstbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) *sbus = &bd->srcbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) } else if (!src_incr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) *mbus = &bd->srcbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) *sbus = &bd->dstbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) if (bd->dstbus.buswidth >= bd->srcbus.buswidth) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) *mbus = &bd->dstbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) *sbus = &bd->srcbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) *mbus = &bd->srcbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) *sbus = &bd->dstbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) * Fills in one LLI for a certain transfer descriptor and advance the counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) static void pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) struct pl08x_lli_build_data *bd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) int num_llis, int len, u32 cctl, u32 cctl2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) u32 offset = num_llis * pl08x->lli_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) u32 *llis_va = bd->txd->llis_va + offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) dma_addr_t llis_bus = bd->txd->llis_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) BUG_ON(num_llis >= MAX_NUM_TSFR_LLIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) /* Advance the offset to next LLI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) offset += pl08x->lli_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) llis_va[PL080_LLI_SRC] = bd->srcbus.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) llis_va[PL080_LLI_DST] = bd->dstbus.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) llis_va[PL080_LLI_LLI] = (llis_bus + sizeof(u32) * offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) llis_va[PL080_LLI_LLI] |= bd->lli_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) llis_va[PL080_LLI_CCTL] = cctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) if (pl08x->vd->pl080s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) llis_va[PL080S_LLI_CCTL2] = cctl2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) if (pl08x->vd->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) /* FIXME: only memcpy so far so both increase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) bd->srcbus.addr += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) bd->dstbus.addr += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (cctl & PL080_CONTROL_SRC_INCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) bd->srcbus.addr += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) if (cctl & PL080_CONTROL_DST_INCR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) bd->dstbus.addr += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) BUG_ON(bd->remainder < len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) bd->remainder -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) struct pl08x_lli_build_data *bd, u32 *cctl, u32 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) int num_llis, size_t *total_bytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) *cctl = pl08x_lli_control_bits(pl08x, *cctl, 1, 1, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) pl08x_fill_lli_for_desc(pl08x, bd, num_llis, len, *cctl, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) (*total_bytes) += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) #if 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) static void pl08x_dump_lli(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) const u32 *llis_va, int num_llis)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (pl08x->vd->pl080s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) dev_vdbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) "%-3s %-9s %-10s %-10s %-10s %-10s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) "lli", "", "csrc", "cdst", "clli", "cctl", "cctl2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) for (i = 0; i < num_llis; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) dev_vdbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) i, llis_va, llis_va[PL080_LLI_SRC],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) llis_va[PL080_LLI_CCTL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) llis_va[PL080S_LLI_CCTL2]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) llis_va += pl08x->lli_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) dev_vdbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) "%-3s %-9s %-10s %-10s %-10s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) "lli", "", "csrc", "cdst", "clli", "cctl");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) for (i = 0; i < num_llis; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) dev_vdbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) "%3d @%p: 0x%08x 0x%08x 0x%08x 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) i, llis_va, llis_va[PL080_LLI_SRC],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) llis_va[PL080_LLI_DST], llis_va[PL080_LLI_LLI],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) llis_va[PL080_LLI_CCTL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) llis_va += pl08x->lli_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) static inline void pl08x_dump_lli(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) const u32 *llis_va, int num_llis) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) * This fills in the table of LLIs for the transfer descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) * Note that we assume we never have to change the burst sizes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) * Return 0 for error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) struct pl08x_txd *txd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct pl08x_bus_data *mbus, *sbus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct pl08x_lli_build_data bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) int num_llis = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) u32 cctl, early_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) size_t max_bytes_per_lli, total_bytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) u32 *llis_va, *last_lli;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) struct pl08x_sg *dsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (!txd->llis_va) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) bd.txd = txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) cctl = txd->cctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) /* Find maximum width of the source bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) bd.srcbus.maxwidth = pl08x_get_bytes_for_lli(pl08x, cctl, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* Find maximum width of the destination bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) bd.dstbus.maxwidth = pl08x_get_bytes_for_lli(pl08x, cctl, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) list_for_each_entry(dsg, &txd->dsg_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) total_bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) cctl = txd->cctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) bd.srcbus.addr = dsg->src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) bd.dstbus.addr = dsg->dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) bd.remainder = dsg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) bd.srcbus.buswidth = bd.srcbus.maxwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) bd.dstbus.buswidth = bd.dstbus.maxwidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) pl08x_choose_master_bus(pl08x, &bd, &mbus, &sbus, cctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) dev_vdbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) "src=0x%08llx%s/%u dst=0x%08llx%s/%u len=%zu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) (u64)bd.srcbus.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) cctl & PL080_CONTROL_SRC_INCR ? "+" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) bd.srcbus.buswidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) (u64)bd.dstbus.addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) cctl & PL080_CONTROL_DST_INCR ? "+" : "",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) bd.dstbus.buswidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) bd.remainder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) mbus == &bd.srcbus ? "src" : "dst",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) sbus == &bd.srcbus ? "src" : "dst");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) * Zero length is only allowed if all these requirements are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) * met:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) * - flow controller is peripheral.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) * - src.addr is aligned to src.width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) * - dst.addr is aligned to dst.width
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * sg_len == 1 should be true, as there can be two cases here:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) * - Memory addresses are contiguous and are not scattered.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) * Here, Only one sg will be passed by user driver, with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) * memory address and zero length. We pass this to controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) * and after the transfer it will receive the last burst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) * request from peripheral and so transfer finishes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) * - Memory addresses are scattered and are not contiguous.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) * Here, Obviously as DMA controller doesn't know when a lli's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) * transfer gets over, it can't load next lli. So in this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) * case, there has to be an assumption that only one lli is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) * supported. Thus, we can't have scattered addresses.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) if (!bd.remainder) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) u32 fc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) /* FTDMAC020 only does memory-to-memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) if (pl08x->vd->ftdmac020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) fc = PL080_FLOW_MEM2MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) fc = (txd->ccfg & PL080_CONFIG_FLOW_CONTROL_MASK) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) PL080_CONFIG_FLOW_CONTROL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (!((fc >= PL080_FLOW_SRC2DST_DST) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) (fc <= PL080_FLOW_SRC2DST_SRC))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) dev_err(&pl08x->adev->dev, "%s sg len can't be zero",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) if (!IS_BUS_ALIGNED(&bd.srcbus) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) !IS_BUS_ALIGNED(&bd.dstbus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) dev_err(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) "%s src & dst address must be aligned to src"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) " & dst width if peripheral is flow controller",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) cctl = pl08x_lli_control_bits(pl08x, cctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) bd.srcbus.buswidth, bd.dstbus.buswidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) 0, cctl, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) * Send byte by byte for following cases
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) * - Less than a bus width available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) * - until master bus is aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) if (bd.remainder < mbus->buswidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) early_bytes = bd.remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) else if (!IS_BUS_ALIGNED(mbus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) early_bytes = mbus->buswidth -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) (mbus->addr & (mbus->buswidth - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) if ((bd.remainder - early_bytes) < mbus->buswidth)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) early_bytes = bd.remainder;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (early_bytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) dev_vdbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) "%s byte width LLIs (remain 0x%08zx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) __func__, bd.remainder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) num_llis++, &total_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) if (bd.remainder) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) * Master now aligned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) * - if slave is not then we must set its width down
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) if (!IS_BUS_ALIGNED(sbus)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) dev_dbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) "%s set down bus width to one byte\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) sbus->buswidth = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) * Bytes transferred = tsize * src width, not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) * MIN(buswidths)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) max_bytes_per_lli = bd.srcbus.buswidth *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) pl08x->vd->max_transfer_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) dev_vdbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) "%s max bytes per lli = %zu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) __func__, max_bytes_per_lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) * Make largest possible LLIs until less than one bus
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) * width left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) while (bd.remainder > (mbus->buswidth - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) size_t lli_len, tsize, width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) * If enough left try to send max possible,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) * otherwise try to send the remainder
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) lli_len = min(bd.remainder, max_bytes_per_lli);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) * Check against maximum bus alignment:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) * Calculate actual transfer size in relation to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) * bus width an get a maximum remainder of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) * highest bus width - 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) width = max(mbus->buswidth, sbus->buswidth);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) lli_len = (lli_len / width) * width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) tsize = lli_len / bd.srcbus.buswidth;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) dev_vdbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) "%s fill lli with single lli chunk of "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) "size 0x%08zx (remainder 0x%08zx)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) __func__, lli_len, bd.remainder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) cctl = pl08x_lli_control_bits(pl08x, cctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) bd.srcbus.buswidth, bd.dstbus.buswidth,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) tsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) lli_len, cctl, tsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) total_bytes += lli_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) * Send any odd bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (bd.remainder) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) dev_vdbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) "%s align with boundary, send odd bytes (remain %zu)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) __func__, bd.remainder);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) prep_byte_width_lli(pl08x, &bd, &cctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) bd.remainder, num_llis++, &total_bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) if (total_bytes != dsg->len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) dev_err(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) "%s size of encoded lli:s don't match total txd, transferred 0x%08zx from size 0x%08zx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) __func__, total_bytes, dsg->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) if (num_llis >= MAX_NUM_TSFR_LLIS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) dev_err(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) "%s need to increase MAX_NUM_TSFR_LLIS from 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) __func__, MAX_NUM_TSFR_LLIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) llis_va = txd->llis_va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) last_lli = llis_va + (num_llis - 1) * pl08x->lli_words;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (txd->cyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /* Link back to the first LLI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) last_lli[PL080_LLI_LLI] = txd->llis_bus | bd.lli_bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) /* The final LLI terminates the LLI. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) last_lli[PL080_LLI_LLI] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) /* The final LLI element shall also fire an interrupt. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (pl08x->vd->ftdmac020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) last_lli[PL080_LLI_CCTL] &= ~FTDMAC020_LLI_TC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) last_lli[PL080_LLI_CCTL] |= PL080_CONTROL_TC_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) pl08x_dump_lli(pl08x, llis_va, num_llis);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) return num_llis;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) struct pl08x_txd *txd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) struct pl08x_sg *dsg, *_dsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (txd->llis_va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) list_for_each_entry_safe(dsg, _dsg, &txd->dsg_list, node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) list_del(&dsg->node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) kfree(dsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) kfree(txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) static void pl08x_desc_free(struct virt_dma_desc *vd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) struct pl08x_dma_chan *plchan = to_pl08x_chan(vd->tx.chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) dma_descriptor_unmap(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) if (!txd->done)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) pl08x_release_mux(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) pl08x_free_txd(plchan->host, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct pl08x_dma_chan *plchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) vchan_get_all_descriptors(&plchan->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) vchan_dma_desc_free_list(&plchan->vc, &head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) * The DMA ENGINE API
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) static void pl08x_free_chan_resources(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) /* Ensure all queued descriptors are freed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) vchan_free_chan_resources(to_virt_chan(chan));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) static struct dma_async_tx_descriptor *pl08x_prep_dma_interrupt(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) struct dma_chan *chan, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) struct dma_async_tx_descriptor *retval = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) * Code accessing dma_async_is_complete() in a tight loop may give problems.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) * If slaves are relying on interrupts to signal completion this function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) * must not be called with interrupts disabled.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) static enum dma_status pl08x_dma_tx_status(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) dma_cookie_t cookie, struct dma_tx_state *txstate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) struct virt_dma_desc *vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) enum dma_status ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) size_t bytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) ret = dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) if (ret == DMA_COMPLETE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) * There's no point calculating the residue if there's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) * no txstate to store the value.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) if (!txstate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) if (plchan->state == PL08X_CHAN_PAUSED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) ret = DMA_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) spin_lock_irqsave(&plchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) ret = dma_cookie_status(chan, cookie, txstate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) if (ret != DMA_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) vd = vchan_find_desc(&plchan->vc, cookie);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) if (vd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) /* On the issued list, so hasn't been processed yet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) struct pl08x_txd *txd = to_pl08x_txd(&vd->tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) struct pl08x_sg *dsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) list_for_each_entry(dsg, &txd->dsg_list, node)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) bytes += dsg->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) bytes = pl08x_getbytes_chan(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) spin_unlock_irqrestore(&plchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) * This cookie not complete yet
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) * Get number of bytes left in the active transactions and queue
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) dma_set_residue(txstate, bytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) if (plchan->state == PL08X_CHAN_PAUSED && ret == DMA_IN_PROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) ret = DMA_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /* Whether waiting or running, we're in progress */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) /* PrimeCell DMA extension */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) struct burst_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) u32 burstwords;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) static const struct burst_table burst_sizes[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .burstwords = 256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .reg = PL080_BSIZE_256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .burstwords = 128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .reg = PL080_BSIZE_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .burstwords = 64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .reg = PL080_BSIZE_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .burstwords = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .reg = PL080_BSIZE_32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .burstwords = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .reg = PL080_BSIZE_16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) .burstwords = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .reg = PL080_BSIZE_8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .burstwords = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .reg = PL080_BSIZE_4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .burstwords = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .reg = PL080_BSIZE_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) * Given the source and destination available bus masks, select which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) * will be routed to each port. We try to have source and destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) * on separate ports, but always respect the allowable settings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static u32 pl08x_select_bus(bool ftdmac020, u8 src, u8 dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) u32 cctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) u32 dst_ahb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) u32 src_ahb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) /* The FTDMAC020 use different bits to indicate src/dst bus */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) if (ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) dst_ahb2 = FTDMAC020_LLI_DST_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) src_ahb2 = FTDMAC020_LLI_SRC_SEL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) dst_ahb2 = PL080_CONTROL_DST_AHB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) src_ahb2 = PL080_CONTROL_SRC_AHB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) if (!(dst & PL08X_AHB1) || ((dst & PL08X_AHB2) && (src & PL08X_AHB1)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) cctl |= dst_ahb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) if (!(src & PL08X_AHB1) || ((src & PL08X_AHB2) && !(dst & PL08X_AHB2)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) cctl |= src_ahb2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) return cctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) static u32 pl08x_cctl(u32 cctl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) cctl &= ~(PL080_CONTROL_SRC_AHB2 | PL080_CONTROL_DST_AHB2 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) PL080_CONTROL_PROT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) /* Access the cell in privileged mode, non-bufferable, non-cacheable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) return cctl | PL080_CONTROL_PROT_SYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) static u32 pl08x_width(enum dma_slave_buswidth width)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) switch (width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) case DMA_SLAVE_BUSWIDTH_1_BYTE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return PL080_WIDTH_8BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) case DMA_SLAVE_BUSWIDTH_2_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) return PL080_WIDTH_16BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) case DMA_SLAVE_BUSWIDTH_4_BYTES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) return PL080_WIDTH_32BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) return ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) static u32 pl08x_burst(u32 maxburst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) for (i = 0; i < ARRAY_SIZE(burst_sizes); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) if (burst_sizes[i].burstwords <= maxburst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) return burst_sizes[i].reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) static u32 pl08x_get_cctl(struct pl08x_dma_chan *plchan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) enum dma_slave_buswidth addr_width, u32 maxburst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) u32 width, burst, cctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) width = pl08x_width(addr_width);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) if (width == ~0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) return ~0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) * If this channel will only request single transfers, set this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) * down to ONE element. Also select one element if no maxburst
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) * is specified.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) if (plchan->cd->single)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) maxburst = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) burst = pl08x_burst(maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) cctl |= burst << PL080_CONTROL_SB_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) cctl |= burst << PL080_CONTROL_DB_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) return pl08x_cctl(cctl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) * Slave transactions callback to the slave device to allow
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) * synchronization of slave DMA signals with the DMAC enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) static void pl08x_issue_pending(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) spin_lock_irqsave(&plchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (vchan_issue_pending(&plchan->vc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) pl08x_phy_alloc_and_start(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) spin_unlock_irqrestore(&plchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) static struct pl08x_txd *pl08x_get_txd(struct pl08x_dma_chan *plchan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) struct pl08x_txd *txd = kzalloc(sizeof(*txd), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) if (txd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) INIT_LIST_HEAD(&txd->dsg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) return txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) static u32 pl08x_memcpy_cctl(struct pl08x_driver_data *pl08x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) u32 cctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) /* Conjure cctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) switch (pl08x->pd->memcpy_burst_size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) dev_err(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) "illegal burst size for memcpy, set to 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) case PL08X_BURST_SZ_1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) cctl |= PL080_BSIZE_1 << PL080_CONTROL_SB_SIZE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) PL080_BSIZE_1 << PL080_CONTROL_DB_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) case PL08X_BURST_SZ_4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) cctl |= PL080_BSIZE_4 << PL080_CONTROL_SB_SIZE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) PL080_BSIZE_4 << PL080_CONTROL_DB_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) case PL08X_BURST_SZ_8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) cctl |= PL080_BSIZE_8 << PL080_CONTROL_SB_SIZE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) PL080_BSIZE_8 << PL080_CONTROL_DB_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) case PL08X_BURST_SZ_16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) cctl |= PL080_BSIZE_16 << PL080_CONTROL_SB_SIZE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) PL080_BSIZE_16 << PL080_CONTROL_DB_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) case PL08X_BURST_SZ_32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) cctl |= PL080_BSIZE_32 << PL080_CONTROL_SB_SIZE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) PL080_BSIZE_32 << PL080_CONTROL_DB_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) case PL08X_BURST_SZ_64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) cctl |= PL080_BSIZE_64 << PL080_CONTROL_SB_SIZE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) PL080_BSIZE_64 << PL080_CONTROL_DB_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) case PL08X_BURST_SZ_128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) cctl |= PL080_BSIZE_128 << PL080_CONTROL_SB_SIZE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) PL080_BSIZE_128 << PL080_CONTROL_DB_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) case PL08X_BURST_SZ_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) cctl |= PL080_BSIZE_256 << PL080_CONTROL_SB_SIZE_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) PL080_BSIZE_256 << PL080_CONTROL_DB_SIZE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) switch (pl08x->pd->memcpy_bus_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) dev_err(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) "illegal bus width for memcpy, set to 8 bits\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) case PL08X_BUS_WIDTH_8_BITS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) cctl |= PL080_WIDTH_8BIT << PL080_CONTROL_SWIDTH_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) PL080_WIDTH_8BIT << PL080_CONTROL_DWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) case PL08X_BUS_WIDTH_16_BITS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) cctl |= PL080_WIDTH_16BIT << PL080_CONTROL_SWIDTH_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) PL080_WIDTH_16BIT << PL080_CONTROL_DWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) case PL08X_BUS_WIDTH_32_BITS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) cctl |= PL080_WIDTH_32BIT << PL080_CONTROL_SWIDTH_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) PL080_WIDTH_32BIT << PL080_CONTROL_DWIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) /* Protection flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) if (pl08x->pd->memcpy_prot_buff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) cctl |= PL080_CONTROL_PROT_BUFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) if (pl08x->pd->memcpy_prot_cache)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) cctl |= PL080_CONTROL_PROT_CACHE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) /* We are the kernel, so we are in privileged mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) cctl |= PL080_CONTROL_PROT_SYS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) /* Both to be incremented or the code will break */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) cctl |= PL080_CONTROL_SRC_INCR | PL080_CONTROL_DST_INCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) if (pl08x->vd->dualmaster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) cctl |= pl08x_select_bus(false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) pl08x->mem_buses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) pl08x->mem_buses);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) return cctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) static u32 pl08x_ftdmac020_memcpy_cctl(struct pl08x_driver_data *pl08x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) u32 cctl = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) /* Conjure cctl */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) switch (pl08x->pd->memcpy_bus_width) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) dev_err(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) "illegal bus width for memcpy, set to 8 bits\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) case PL08X_BUS_WIDTH_8_BITS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) cctl |= PL080_WIDTH_8BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) PL080_WIDTH_8BIT << FTDMAC020_LLI_DST_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) case PL08X_BUS_WIDTH_16_BITS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) cctl |= PL080_WIDTH_16BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) PL080_WIDTH_16BIT << FTDMAC020_LLI_DST_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) case PL08X_BUS_WIDTH_32_BITS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) cctl |= PL080_WIDTH_32BIT << FTDMAC020_LLI_SRC_WIDTH_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) PL080_WIDTH_32BIT << FTDMAC020_LLI_DST_WIDTH_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) * By default mask the TC IRQ on all LLIs, it will be unmasked on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) * the last LLI item by other code.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) cctl |= FTDMAC020_LLI_TC_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) * Both to be incremented so leave bits FTDMAC020_LLI_SRCAD_CTL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) * and FTDMAC020_LLI_DSTAD_CTL as zero
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) if (pl08x->vd->dualmaster)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) cctl |= pl08x_select_bus(true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) pl08x->mem_buses,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) pl08x->mem_buses);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) return cctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) * Initialize a descriptor to be used by memcpy submit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) static struct dma_async_tx_descriptor *pl08x_prep_dma_memcpy(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) size_t len, unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) struct pl08x_driver_data *pl08x = plchan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) struct pl08x_txd *txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) struct pl08x_sg *dsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) txd = pl08x_get_txd(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) if (!txd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) dev_err(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) "%s no memory for descriptor\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) if (!dsg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) pl08x_free_txd(pl08x, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) list_add_tail(&dsg->node, &txd->dsg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) dsg->src_addr = src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) dsg->dst_addr = dest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) dsg->len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) if (pl08x->vd->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) /* Writing CCFG zero ENABLES all interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) txd->ccfg = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) txd->cctl = pl08x_ftdmac020_memcpy_cctl(pl08x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) PL080_CONFIG_TC_IRQ_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) PL080_FLOW_MEM2MEM << PL080_CONFIG_FLOW_CONTROL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) txd->cctl = pl08x_memcpy_cctl(pl08x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) ret = pl08x_fill_llis_for_desc(plchan->host, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) pl08x_free_txd(pl08x, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) static struct pl08x_txd *pl08x_init_txd(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) dma_addr_t *slave_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) struct pl08x_driver_data *pl08x = plchan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) struct pl08x_txd *txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) enum dma_slave_buswidth addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) int ret, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) u8 src_buses, dst_buses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) u32 maxburst, cctl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) txd = pl08x_get_txd(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (!txd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) * Set up addresses, the PrimeCell configured address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) * will take precedence since this may configure the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) * channel target address dynamically at runtime.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) if (direction == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) cctl = PL080_CONTROL_SRC_INCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) *slave_addr = plchan->cfg.dst_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) addr_width = plchan->cfg.dst_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) maxburst = plchan->cfg.dst_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) src_buses = pl08x->mem_buses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) dst_buses = plchan->cd->periph_buses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) } else if (direction == DMA_DEV_TO_MEM) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) cctl = PL080_CONTROL_DST_INCR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) *slave_addr = plchan->cfg.src_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) addr_width = plchan->cfg.src_addr_width;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) maxburst = plchan->cfg.src_maxburst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) src_buses = plchan->cd->periph_buses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) dst_buses = pl08x->mem_buses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) pl08x_free_txd(pl08x, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) dev_err(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) "%s direction unsupported\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) cctl |= pl08x_get_cctl(plchan, addr_width, maxburst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (cctl == ~0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) pl08x_free_txd(pl08x, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) dev_err(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) "DMA slave configuration botched?\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) txd->cctl = cctl | pl08x_select_bus(false, src_buses, dst_buses);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) if (plchan->cfg.device_fc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER_PER :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) PL080_FLOW_PER2MEM_PER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) tmp = (direction == DMA_MEM_TO_DEV) ? PL080_FLOW_MEM2PER :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) PL080_FLOW_PER2MEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) txd->ccfg = PL080_CONFIG_ERR_IRQ_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) PL080_CONFIG_TC_IRQ_MASK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) tmp << PL080_CONFIG_FLOW_CONTROL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) ret = pl08x_request_mux(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) pl08x_free_txd(pl08x, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) dev_dbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) "unable to mux for transfer on %s due to platform restrictions\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) plchan->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) plchan->signal, plchan->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) /* Assign the flow control signal to this channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) if (direction == DMA_MEM_TO_DEV)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) txd->ccfg |= plchan->signal << PL080_CONFIG_DST_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) txd->ccfg |= plchan->signal << PL080_CONFIG_SRC_SEL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) return txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) static int pl08x_tx_add_sg(struct pl08x_txd *txd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) dma_addr_t slave_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) dma_addr_t buf_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) struct pl08x_sg *dsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) dsg = kzalloc(sizeof(struct pl08x_sg), GFP_NOWAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) if (!dsg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) list_add_tail(&dsg->node, &txd->dsg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) dsg->len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if (direction == DMA_MEM_TO_DEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) dsg->src_addr = buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) dsg->dst_addr = slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) dsg->src_addr = slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) dsg->dst_addr = buf_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) static struct dma_async_tx_descriptor *pl08x_prep_slave_sg(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) struct dma_chan *chan, struct scatterlist *sgl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) unsigned int sg_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) unsigned long flags, void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) struct pl08x_driver_data *pl08x = plchan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) struct pl08x_txd *txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) int ret, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) dma_addr_t slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) __func__, sg_dma_len(sgl), plchan->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) txd = pl08x_init_txd(chan, direction, &slave_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) if (!txd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) for_each_sg(sgl, sg, sg_len, tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) ret = pl08x_tx_add_sg(txd, direction, slave_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) sg_dma_address(sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) sg_dma_len(sg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) pl08x_release_mux(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) pl08x_free_txd(pl08x, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) ret = pl08x_fill_llis_for_desc(plchan->host, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) pl08x_release_mux(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) pl08x_free_txd(pl08x, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) static struct dma_async_tx_descriptor *pl08x_prep_dma_cyclic(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) size_t period_len, enum dma_transfer_direction direction,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) unsigned long flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) struct pl08x_driver_data *pl08x = plchan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) struct pl08x_txd *txd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) int ret, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) dma_addr_t slave_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) dev_dbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) "%s prepare cyclic transaction of %zd/%zd bytes %s %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) __func__, period_len, buf_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) direction == DMA_MEM_TO_DEV ? "to" : "from",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) plchan->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) txd = pl08x_init_txd(chan, direction, &slave_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) if (!txd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) txd->cyclic = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) txd->cctl |= PL080_CONTROL_TC_IRQ_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) for (tmp = 0; tmp < buf_len; tmp += period_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) ret = pl08x_tx_add_sg(txd, direction, slave_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) buf_addr + tmp, period_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) pl08x_release_mux(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) pl08x_free_txd(pl08x, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) ret = pl08x_fill_llis_for_desc(plchan->host, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) pl08x_release_mux(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) pl08x_free_txd(pl08x, txd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) return vchan_tx_prep(&plchan->vc, &txd->vd, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) static int pl08x_config(struct dma_chan *chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) struct dma_slave_config *config)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) struct pl08x_driver_data *pl08x = plchan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) if (!plchan->slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) /* Reject definitely invalid configurations */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) if (config->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) config->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) if (config->device_fc && pl08x->vd->pl080s) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) dev_err(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) "%s: PL080S does not support peripheral flow control\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) plchan->cfg = *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) static int pl08x_terminate_all(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) struct pl08x_driver_data *pl08x = plchan->host;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) spin_lock_irqsave(&plchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) if (!plchan->phychan && !plchan->at) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) spin_unlock_irqrestore(&plchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) plchan->state = PL08X_CHAN_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) if (plchan->phychan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) * Mark physical channel as free and free any slave
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) * signal
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) pl08x_phy_free(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) /* Dequeue jobs and free LLIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (plchan->at) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) vchan_terminate_vdesc(&plchan->at->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) plchan->at = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) /* Dequeue jobs not yet fired as well */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) pl08x_free_txd_list(pl08x, plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) spin_unlock_irqrestore(&plchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) static void pl08x_synchronize(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) vchan_synchronize(&plchan->vc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) static int pl08x_pause(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) * Anything succeeds on channels with no physical allocation and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) * no queued transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) spin_lock_irqsave(&plchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) if (!plchan->phychan && !plchan->at) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) spin_unlock_irqrestore(&plchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) pl08x_pause_phy_chan(plchan->phychan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) plchan->state = PL08X_CHAN_PAUSED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) spin_unlock_irqrestore(&plchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) static int pl08x_resume(struct dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) * Anything succeeds on channels with no physical allocation and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) * no queued transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) spin_lock_irqsave(&plchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) if (!plchan->phychan && !plchan->at) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) spin_unlock_irqrestore(&plchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) pl08x_resume_phy_chan(plchan->phychan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) plchan->state = PL08X_CHAN_RUNNING;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) spin_unlock_irqrestore(&plchan->vc.lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) bool pl08x_filter_id(struct dma_chan *chan, void *chan_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) struct pl08x_dma_chan *plchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) char *name = chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) /* Reject channels for devices not bound to this driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) if (chan->device->dev->driver != &pl08x_amba_driver.drv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) plchan = to_pl08x_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) /* Check that the channel is not taken! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) if (!strcmp(plchan->name, name))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) EXPORT_SYMBOL_GPL(pl08x_filter_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) static bool pl08x_filter_fn(struct dma_chan *chan, void *chan_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) struct pl08x_dma_chan *plchan = to_pl08x_chan(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) return plchan->cd == chan_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) * Just check that the device is there and active
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) * TODO: turn this bit on/off depending on the number of physical channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) * actually used, if it is zero... well shut it off. That will save some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) * power. Cut the clock at the same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) /* The Nomadik variant does not have the config register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) if (pl08x->vd->nomadik)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) /* The FTDMAC020 variant does this in another register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) if (pl08x->vd->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) writel(PL080_CONFIG_ENABLE, pl08x->base + FTDMAC020_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) static irqreturn_t pl08x_irq(int irq, void *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) struct pl08x_driver_data *pl08x = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) u32 mask = 0, err, tc, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) /* check & clear - ERR & TC interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) err = readl(pl08x->base + PL080_ERR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) writel(err, pl08x->base + PL080_ERR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) tc = readl(pl08x->base + PL080_TC_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) if (tc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) writel(tc, pl08x->base + PL080_TC_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) if (!err && !tc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) for (i = 0; i < pl08x->vd->channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) if ((BIT(i) & err) || (BIT(i) & tc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) /* Locate physical channel */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) struct pl08x_dma_chan *plchan = phychan->serving;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) struct pl08x_txd *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) if (!plchan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) dev_err(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) "%s Error TC interrupt on unused channel: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) __func__, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) spin_lock(&plchan->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) tx = plchan->at;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) if (tx && tx->cyclic) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) vchan_cyclic_callback(&tx->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) } else if (tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) plchan->at = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) * This descriptor is done, release its mux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) * reservation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) pl08x_release_mux(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) tx->done = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) vchan_cookie_complete(&tx->vd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) * And start the next descriptor (if any),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) * otherwise free this channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) if (vchan_next_desc(&plchan->vc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) pl08x_start_next_txd(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) pl08x_phy_free(plchan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) spin_unlock(&plchan->vc.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) mask |= BIT(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) return mask ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) static void pl08x_dma_slave_init(struct pl08x_dma_chan *chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) chan->slave = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) chan->name = chan->cd->bus_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) chan->cfg.src_addr = chan->cd->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) chan->cfg.dst_addr = chan->cd->addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) * Initialise the DMAC memcpy/slave channels.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) * Make a local wrapper to hold required data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) struct dma_device *dmadev, unsigned int channels, bool slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) struct pl08x_dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) INIT_LIST_HEAD(&dmadev->channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) * Register as many many memcpy as we have physical channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) * we won't always be able to use all but the code will have
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) * to cope with that situation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) for (i = 0; i < channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) chan = kzalloc(sizeof(*chan), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) if (!chan)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) chan->host = pl08x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) chan->state = PL08X_CHAN_IDLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) chan->signal = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) if (slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) chan->cd = &pl08x->pd->slave_channels[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) * Some implementations have muxed signals, whereas some
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) * use a mux in front of the signals and need dynamic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) * assignment of signals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) chan->signal = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) pl08x_dma_slave_init(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) chan->cd = kzalloc(sizeof(*chan->cd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) if (!chan->cd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) kfree(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) chan->cd->bus_id = "memcpy";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) chan->cd->periph_buses = pl08x->pd->mem_buses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) chan->name = kasprintf(GFP_KERNEL, "memcpy%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) if (!chan->name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) kfree(chan->cd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) kfree(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) dev_dbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) "initialize virtual channel \"%s\"\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) chan->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) chan->vc.desc_free = pl08x_desc_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) vchan_init(&chan->vc, dmadev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) i, slave ? "slave" : "memcpy");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) static void pl08x_free_virtual_channels(struct dma_device *dmadev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) struct pl08x_dma_chan *chan = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) struct pl08x_dma_chan *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) list_for_each_entry_safe(chan,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) next, &dmadev->channels, vc.chan.device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) list_del(&chan->vc.chan.device_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) kfree(chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) #ifdef CONFIG_DEBUG_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) static const char *pl08x_state_str(enum pl08x_dma_chan_state state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) switch (state) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) case PL08X_CHAN_IDLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) return "idle";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) case PL08X_CHAN_RUNNING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) return "running";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) case PL08X_CHAN_PAUSED:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) return "paused";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) case PL08X_CHAN_WAITING:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) return "waiting";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) return "UNKNOWN STATE";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) static int pl08x_debugfs_show(struct seq_file *s, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) struct pl08x_driver_data *pl08x = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) struct pl08x_dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) struct pl08x_phy_chan *ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) seq_printf(s, "PL08x physical channels:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) seq_printf(s, "CHANNEL:\tUSER:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) seq_printf(s, "--------\t-----\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) for (i = 0; i < pl08x->vd->channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) struct pl08x_dma_chan *virt_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) ch = &pl08x->phy_chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) spin_lock_irqsave(&ch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) virt_chan = ch->serving;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) seq_printf(s, "%d\t\t%s%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) ch->id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) virt_chan ? virt_chan->name : "(none)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) ch->locked ? " LOCKED" : "");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) spin_unlock_irqrestore(&ch->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) seq_printf(s, "\nPL08x virtual memcpy channels:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) seq_printf(s, "CHANNEL:\tSTATE:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) seq_printf(s, "--------\t------\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) seq_printf(s, "%s\t\t%s\n", chan->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) pl08x_state_str(chan->state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) if (pl08x->has_slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) seq_printf(s, "\nPL08x virtual slave channels:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) seq_printf(s, "CHANNEL:\tSTATE:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) seq_printf(s, "--------\t------\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) list_for_each_entry(chan, &pl08x->slave.channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) vc.chan.device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) seq_printf(s, "%s\t\t%s\n", chan->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) pl08x_state_str(chan->state));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) DEFINE_SHOW_ATTRIBUTE(pl08x_debugfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) /* Expose a simple debugfs interface to view all clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) NULL, pl08x, &pl08x_debugfs_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) static struct dma_chan *pl08x_find_chan_id(struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) u32 id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) struct pl08x_dma_chan *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) /* Trying to get a slave channel from something with no slave support */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) if (!pl08x->has_slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) if (chan->signal == id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) return &chan->vc.chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) static struct dma_chan *pl08x_of_xlate(struct of_phandle_args *dma_spec,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) struct of_dma *ofdma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) struct pl08x_driver_data *pl08x = ofdma->of_dma_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) struct dma_chan *dma_chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) struct pl08x_dma_chan *plchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) if (!pl08x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) if (dma_spec->args_count != 2) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) dev_err(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) "DMA channel translation requires two cells\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) dma_chan = pl08x_find_chan_id(pl08x, dma_spec->args[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) if (!dma_chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) dev_err(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) "DMA slave channel not found\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) plchan = to_pl08x_chan(dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) dev_dbg(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) "translated channel for signal %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) dma_spec->args[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) /* Augment channel data for applicable AHB buses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) plchan->cd->periph_buses = dma_spec->args[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) return dma_get_slave_channel(dma_chan);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) static int pl08x_of_probe(struct amba_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) struct pl08x_platform_data *pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) struct pl08x_channel_data *chanp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) pd = devm_kzalloc(&adev->dev, sizeof(*pd), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) if (!pd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) /* Eligible bus masters for fetching LLIs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) if (of_property_read_bool(np, "lli-bus-interface-ahb1"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) pd->lli_buses |= PL08X_AHB1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) if (of_property_read_bool(np, "lli-bus-interface-ahb2"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) pd->lli_buses |= PL08X_AHB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) if (!pd->lli_buses) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) dev_info(&adev->dev, "no bus masters for LLIs stated, assume all\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) pd->lli_buses |= PL08X_AHB1 | PL08X_AHB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) /* Eligible bus masters for memory access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) if (of_property_read_bool(np, "mem-bus-interface-ahb1"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) pd->mem_buses |= PL08X_AHB1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) if (of_property_read_bool(np, "mem-bus-interface-ahb2"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) pd->mem_buses |= PL08X_AHB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) if (!pd->mem_buses) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) dev_info(&adev->dev, "no bus masters for memory stated, assume all\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) pd->mem_buses |= PL08X_AHB1 | PL08X_AHB2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) /* Parse the memcpy channel properties */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) ret = of_property_read_u32(np, "memcpy-burst-size", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) dev_info(&adev->dev, "no memcpy burst size specified, using 1 byte\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) val = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) dev_err(&adev->dev, "illegal burst size for memcpy, set to 1\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) case 1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) pd->memcpy_burst_size = PL08X_BURST_SZ_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) pd->memcpy_burst_size = PL08X_BURST_SZ_4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) pd->memcpy_burst_size = PL08X_BURST_SZ_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) pd->memcpy_burst_size = PL08X_BURST_SZ_16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) pd->memcpy_burst_size = PL08X_BURST_SZ_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) case 64:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) pd->memcpy_burst_size = PL08X_BURST_SZ_64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) case 128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) pd->memcpy_burst_size = PL08X_BURST_SZ_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) case 256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) pd->memcpy_burst_size = PL08X_BURST_SZ_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) ret = of_property_read_u32(np, "memcpy-bus-width", &val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) dev_info(&adev->dev, "no memcpy bus width specified, using 8 bits\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) val = 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) switch (val) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) dev_err(&adev->dev, "illegal bus width for memcpy, set to 8 bits\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) fallthrough;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) pd->memcpy_bus_width = PL08X_BUS_WIDTH_8_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) pd->memcpy_bus_width = PL08X_BUS_WIDTH_16_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) case 32:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) pd->memcpy_bus_width = PL08X_BUS_WIDTH_32_BITS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) * Allocate channel data for all possible slave channels (one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) * for each possible signal), channels will then be allocated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) * for a device and have it's AHB interfaces set up at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) * translation time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) if (pl08x->vd->signals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) chanp = devm_kcalloc(&adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) pl08x->vd->signals,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) sizeof(struct pl08x_channel_data),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) if (!chanp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) pd->slave_channels = chanp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) for (i = 0; i < pl08x->vd->signals; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) * chanp->periph_buses will be assigned at translation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) chanp->bus_id = kasprintf(GFP_KERNEL, "slave%d", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) chanp++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) pd->num_slave_channels = pl08x->vd->signals;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) pl08x->pd = pd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) return of_dma_controller_register(adev->dev.of_node, pl08x_of_xlate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) pl08x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) static inline int pl08x_of_probe(struct amba_device *adev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) struct pl08x_driver_data *pl08x,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) struct device_node *np)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) static int pl08x_probe(struct amba_device *adev, const struct amba_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) struct pl08x_driver_data *pl08x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) struct vendor_data *vd = id->data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) struct device_node *np = adev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) u32 tsfr_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) ret = amba_request_regions(adev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) /* Ensure that we can do DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) ret = dma_set_mask_and_coherent(&adev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) goto out_no_pl08x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) /* Create the driver state holder */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) if (!pl08x) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) goto out_no_pl08x;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) /* Assign useful pointers to the driver state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) pl08x->adev = adev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) pl08x->vd = vd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) if (!pl08x->base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) goto out_no_ioremap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) if (vd->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) val = readl(pl08x->base + FTDMAC020_REVISION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) dev_info(&pl08x->adev->dev, "FTDMAC020 %d.%d rel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) val = readl(pl08x->base + FTDMAC020_FEATURE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) dev_info(&pl08x->adev->dev, "FTDMAC020 %d channels, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) "%s built-in bridge, %s, %s linked lists\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) (val >> 12) & 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) (val & BIT(10)) ? "no" : "has",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) (val & BIT(9)) ? "AHB0 and AHB1" : "AHB0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) (val & BIT(8)) ? "supports" : "does not support");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) /* Vendor data from feature register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) if (!(val & BIT(8)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) dev_warn(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) "linked lists not supported, required\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) vd->channels = (val >> 12) & 0x0f;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) vd->dualmaster = !!(val & BIT(9));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) /* Initialize memcpy engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) pl08x->memcpy.dev = &adev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) pl08x->memcpy.device_config = pl08x_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) pl08x->memcpy.device_pause = pl08x_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) pl08x->memcpy.device_resume = pl08x_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) pl08x->memcpy.device_terminate_all = pl08x_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) pl08x->memcpy.device_synchronize = pl08x_synchronize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) pl08x->memcpy.src_addr_widths = PL80X_DMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) pl08x->memcpy.dst_addr_widths = PL80X_DMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) pl08x->memcpy.directions = BIT(DMA_MEM_TO_MEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) pl08x->memcpy.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) if (vd->ftdmac020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) pl08x->memcpy.copy_align = DMAENGINE_ALIGN_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) * Initialize slave engine, if the block has no signals, that means
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) * we have no slave support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) if (vd->signals) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) pl08x->has_slave = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) dma_cap_set(DMA_CYCLIC, pl08x->slave.cap_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) pl08x->slave.dev = &adev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) pl08x->slave.device_free_chan_resources =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) pl08x_free_chan_resources;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) pl08x->slave.device_prep_dma_interrupt =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) pl08x_prep_dma_interrupt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) pl08x->slave.device_tx_status = pl08x_dma_tx_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) pl08x->slave.device_issue_pending = pl08x_issue_pending;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) pl08x->slave.device_prep_dma_cyclic = pl08x_prep_dma_cyclic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) pl08x->slave.device_config = pl08x_config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) pl08x->slave.device_pause = pl08x_pause;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) pl08x->slave.device_resume = pl08x_resume;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) pl08x->slave.device_terminate_all = pl08x_terminate_all;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) pl08x->slave.device_synchronize = pl08x_synchronize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) pl08x->slave.src_addr_widths = PL80X_DMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) pl08x->slave.dst_addr_widths = PL80X_DMA_BUSWIDTHS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) pl08x->slave.directions =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) pl08x->slave.residue_granularity =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) DMA_RESIDUE_GRANULARITY_SEGMENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) /* Get the platform data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) pl08x->pd = dev_get_platdata(&adev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) if (!pl08x->pd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) if (np) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) ret = pl08x_of_probe(adev, pl08x, np);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) goto out_no_platdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) dev_err(&adev->dev, "no platform data supplied\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) goto out_no_platdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) pl08x->slave.filter.map = pl08x->pd->slave_map;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) pl08x->slave.filter.mapcnt = pl08x->pd->slave_map_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) pl08x->slave.filter.fn = pl08x_filter_fn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) /* By default, AHB1 only. If dualmaster, from platform */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) pl08x->lli_buses = PL08X_AHB1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) pl08x->mem_buses = PL08X_AHB1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) if (pl08x->vd->dualmaster) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) pl08x->lli_buses = pl08x->pd->lli_buses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) pl08x->mem_buses = pl08x->pd->mem_buses;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) if (vd->pl080s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) pl08x->lli_words = PL080S_LLI_WORDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) pl08x->lli_words = PL080_LLI_WORDS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) tsfr_size = MAX_NUM_TSFR_LLIS * pl08x->lli_words * sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) /* A DMA memory pool for LLIs, align on 1-byte boundary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) tsfr_size, PL08X_ALIGN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) if (!pl08x->pool) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) goto out_no_lli_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) /* Turn on the PL08x */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) pl08x_ensure_on(pl08x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) /* Clear any pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) if (vd->ftdmac020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) /* This variant has error IRQs in bits 16-19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) writel(0x0000FFFF, pl08x->base + PL080_ERR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) /* Attach the interrupt handler */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) ret = request_irq(adev->irq[0], pl08x_irq, 0, DRIVER_NAME, pl08x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) dev_err(&adev->dev, "%s failed to request interrupt %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) __func__, adev->irq[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) goto out_no_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) /* Initialize physical channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) if (!pl08x->phy_chans) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) goto out_no_phychans;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) for (i = 0; i < vd->channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) ch->id = i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) ch->base = pl08x->base + PL080_Cx_BASE(i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) if (vd->ftdmac020) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) /* FTDMA020 has a special channel busy register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) ch->reg_busy = ch->base + FTDMAC020_CH_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) ch->reg_config = ch->base + FTDMAC020_CH_CFG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) ch->reg_control = ch->base + FTDMAC020_CH_CSR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) ch->reg_src = ch->base + FTDMAC020_CH_SRC_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) ch->reg_dst = ch->base + FTDMAC020_CH_DST_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) ch->reg_lli = ch->base + FTDMAC020_CH_LLP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) ch->ftdmac020 = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) ch->reg_config = ch->base + vd->config_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) ch->reg_control = ch->base + PL080_CH_CONTROL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) ch->reg_src = ch->base + PL080_CH_SRC_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) ch->reg_dst = ch->base + PL080_CH_DST_ADDR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) ch->reg_lli = ch->base + PL080_CH_LLI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) if (vd->pl080s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) ch->pl080s = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) spin_lock_init(&ch->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) * Nomadik variants can have channels that are locked
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) * down for the secure world only. Lock up these channels
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) * by perpetually serving a dummy virtual channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) if (vd->nomadik) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) val = readl(ch->reg_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) dev_info(&adev->dev, "physical channel %d reserved for secure access only\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) ch->locked = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) dev_dbg(&adev->dev, "physical channel %d is %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) i, pl08x_phy_channel_busy(ch) ? "BUSY" : "FREE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) /* Register as many memcpy channels as there are physical channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) pl08x->vd->channels, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) if (ret <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) dev_warn(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) "%s failed to enumerate memcpy channels - %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) goto out_no_memcpy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) /* Register slave channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) if (pl08x->has_slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) pl08x->pd->num_slave_channels, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) dev_warn(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) "%s failed to enumerate slave channels - %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) goto out_no_slave;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) ret = dma_async_device_register(&pl08x->memcpy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) dev_warn(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) "%s failed to register memcpy as an async device - %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) goto out_no_memcpy_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) if (pl08x->has_slave) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) ret = dma_async_device_register(&pl08x->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) dev_warn(&pl08x->adev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) "%s failed to register slave as an async device - %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) __func__, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) goto out_no_slave_reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) amba_set_drvdata(adev, pl08x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) init_pl08x_debugfs(pl08x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) dev_info(&pl08x->adev->dev, "DMA: PL%03x%s rev%u at 0x%08llx irq %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) amba_part(adev), pl08x->vd->pl080s ? "s" : "", amba_rev(adev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) (unsigned long long)adev->res.start, adev->irq[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) out_no_slave_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) dma_async_device_unregister(&pl08x->memcpy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) out_no_memcpy_reg:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) if (pl08x->has_slave)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) pl08x_free_virtual_channels(&pl08x->slave);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) out_no_slave:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) pl08x_free_virtual_channels(&pl08x->memcpy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) out_no_memcpy:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) kfree(pl08x->phy_chans);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) out_no_phychans:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) free_irq(adev->irq[0], pl08x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) out_no_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) dma_pool_destroy(pl08x->pool);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) out_no_lli_pool:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) out_no_platdata:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) iounmap(pl08x->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) out_no_ioremap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) kfree(pl08x);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) out_no_pl08x:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) amba_release_regions(adev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) /* PL080 has 8 channels and the PL080 have just 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) static struct vendor_data vendor_pl080 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) .config_offset = PL080_CH_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) .channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) .signals = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) .dualmaster = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) static struct vendor_data vendor_nomadik = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) .config_offset = PL080_CH_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) .channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) .signals = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) .dualmaster = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) .nomadik = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) static struct vendor_data vendor_pl080s = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) .config_offset = PL080S_CH_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) .channels = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) .signals = 32,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) .pl080s = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) .max_transfer_size = PL080S_CONTROL_TRANSFER_SIZE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) static struct vendor_data vendor_pl081 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) .config_offset = PL080_CH_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) .channels = 2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) .signals = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) .dualmaster = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) static struct vendor_data vendor_ftdmac020 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) .config_offset = PL080_CH_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) .ftdmac020 = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) .max_transfer_size = PL080_CONTROL_TRANSFER_SIZE_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) static const struct amba_id pl08x_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) /* Samsung PL080S variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) .id = 0x0a141080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) .mask = 0xffffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) .data = &vendor_pl080s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039) /* PL080 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) .id = 0x00041080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) .mask = 0x000fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) .data = &vendor_pl080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045) /* PL081 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) .id = 0x00041081,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) .mask = 0x000fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) .data = &vendor_pl081,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) /* Nomadik 8815 PL080 variant */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) .id = 0x00280080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) .mask = 0x00ffffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) .data = &vendor_nomadik,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) /* Faraday Technology FTDMAC020 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) .id = 0x0003b080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) .mask = 0x000fffff,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) .data = &vendor_ftdmac020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) { 0, 0 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) MODULE_DEVICE_TABLE(amba, pl08x_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) static struct amba_driver pl08x_amba_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) .drv.name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) .id_table = pl08x_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) .probe = pl08x_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) static int __init pl08x_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) int retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) retval = amba_driver_register(&pl08x_amba_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) if (retval)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) printk(KERN_WARNING DRIVER_NAME
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) "failed to register as an AMBA device (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) retval);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) return retval;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) subsys_initcall(pl08x_init);
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags