^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) # DMA engine configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) menuconfig DMADEVICES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) bool "DMA Engine support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) depends on HAS_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) DMA engines can do asynchronous data transfers without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) involving the host CPU. Currently, this framework can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) used to offload memory copies in the network stack and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) RAID operations in the MD driver. This menu only presents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) DMA Device drivers supported by the configured arch, it may
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) be empty in some cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) config DMADEVICES_DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) bool "DMA Engine debugging"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) depends on DMADEVICES != n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) This is an option for use by developers; most people should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) say N here. This enables DMA engine core and driver debugging.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) config DMADEVICES_VDEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) bool "DMA Engine verbose debugging"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) depends on DMADEVICES_DEBUG != n
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) This is an option for use by developers; most people should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) say N here. This enables deeper (more verbose) debugging of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) the DMA engine core and drivers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) if DMADEVICES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) comment "DMA Devices"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #core
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) config ASYNC_TX_ENABLE_CHANNEL_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) config ARCH_HAS_ASYNC_TX_FIND_CHANNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) config DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) config DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) tristate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) config DMA_ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) depends on ACPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) config DMA_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) def_bool y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #devices
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) config ALTERA_MSGDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) tristate "Altera / Intel mSGDMA Engine"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) depends on HAS_IOMEM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) Enable support for Altera / Intel mSGDMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) config AMBA_PL08X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) bool "ARM PrimeCell PL080 or PL081 support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) depends on ARM_AMBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) Say yes if your platform has a PL08x DMAC device which can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) provide DMA engine support. This includes the original ARM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) PL080 and PL081, Samsungs PL080 derivative and Faraday
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) Technology's FTDMAC020 PL080 derivative.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) config AMCC_PPC440SPE_ADMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) tristate "AMCC PPC440SPe ADMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) depends on 440SPe || 440SP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) select DMA_ENGINE_RAID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) select ARCH_HAS_ASYNC_TX_FIND_CHANNEL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) select ASYNC_TX_ENABLE_CHANNEL_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) Enable support for the AMCC PPC440SPe RAID engines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) config AT_HDMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) tristate "Atmel AHB DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) depends on ARCH_AT91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) Support the Atmel AHB DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) config AT_XDMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) tristate "Atmel XDMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) depends on ARCH_AT91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) Support the Atmel XDMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) config AXI_DMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tristate "Analog Devices AXI-DMAC DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) depends on MICROBLAZE || NIOS2 || ARCH_ZYNQ || ARCH_ZYNQMP || ARCH_SOCFPGA || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) select REGMAP_MMIO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) Enable support for the Analog Devices AXI-DMAC peripheral. This DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) controller is often used in Analog Devices' reference designs for FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) config BCM_SBA_RAID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) tristate "Broadcom SBA RAID engine support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) depends on ARM64 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) depends on MAILBOX && RAID6_PQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) select DMA_ENGINE_RAID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) select ASYNC_TX_DISABLE_XOR_VAL_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) select ASYNC_TX_DISABLE_PQ_VAL_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) default m if ARCH_BCM_IPROC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) Enable support for Broadcom SBA RAID Engine. The SBA RAID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) engine is available on most of the Broadcom iProc SoCs. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) has the capability to offload memcpy, xor and pq computation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) for raid5/6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) config COH901318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) bool "ST-Ericsson COH901318 DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) depends on ARCH_U300 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) Enable support for ST-Ericsson COH 901 318 DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) config DMA_BCM2835
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) tristate "BCM2835 DMA engine support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) depends on ARCH_BCM2835
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) config DMA_JZ4780
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) tristate "JZ4780 DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) depends on MIPS || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) This selects support for the DMA controller in Ingenic JZ4780 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) If you have a board based on such a SoC and wish to use DMA for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) devices which can use the DMA controller, say Y or M here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) config DMA_SA11X0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) tristate "SA-11x0 DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) depends on ARCH_SA1100 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) Support the DMA engine found on Intel StrongARM SA-1100 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) SA-1110 SoCs. This DMA engine can only be used with on-chip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) config DMA_SUN4I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) tristate "Allwinner A10 DMA SoCs support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) depends on MACH_SUN4I || MACH_SUN5I || MACH_SUN7I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) default (MACH_SUN4I || MACH_SUN5I || MACH_SUN7I)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) Enable support for the DMA controller present in the sun4i,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) sun5i and sun7i Allwinner ARM SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) config DMA_SUN6I
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) tristate "Allwinner A31 SoCs DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) depends on MACH_SUN6I || MACH_SUN8I || (ARM64 && ARCH_SUNXI) || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) depends on RESET_CONTROLLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) Support for the DMA engine first found in Allwinner A31 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) config DW_AXI_DMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) tristate "Synopsys DesignWare AXI DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) depends on OF || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) Enable support for Synopsys DesignWare AXI DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) NOTE: This driver wasn't tested on 64 bit platform because
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) of lack 64 bit platform with Synopsys DW AXI DMAC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) config EP93XX_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) bool "Cirrus Logic EP93xx DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) depends on ARCH_EP93XX || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) Enable support for the Cirrus Logic EP93xx M2P/M2M DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) config FSL_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) tristate "Freescale Elo series DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) depends on FSL_SOC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) select ASYNC_TX_ENABLE_CHANNEL_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) Enable support for the Freescale Elo series DMA controllers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) The Elo is the DMA controller on some mpc82xx and mpc83xx parts, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) EloPlus is on mpc85xx and mpc86xx and Pxxx parts, and the Elo3 is on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) some Txxx and Bxxx parts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) config FSL_EDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) tristate "Freescale eDMA engine support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) Support the Freescale eDMA engine with programmable channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) multiplexing capability for DMA request sources(slot).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) This module can be found on Freescale Vybrid and LS-1 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) config FSL_QDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) tristate "NXP Layerscape qDMA engine support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) depends on ARM || ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) select DMA_ENGINE_RAID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) select ASYNC_TX_ENABLE_CHANNEL_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) Support the NXP Layerscape qDMA engine with command queue and legacy mode.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) Channel virtualization is supported through enqueuing of DMA jobs to,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) or dequeuing DMA jobs from, different work queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) This module can be found on NXP Layerscape SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) The qdma driver only work on SoCs with a DPAA hardware block.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) config FSL_RAID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) tristate "Freescale RAID engine Support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) depends on FSL_SOC && !ASYNC_TX_ENABLE_CHANNEL_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) select DMA_ENGINE_RAID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) Enable support for Freescale RAID Engine. RAID Engine is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) available on some QorIQ SoCs (like P5020/P5040). It has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) the capability to offload memcpy, xor and pq computation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) for raid5/6.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) config HISI_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) tristate "HiSilicon DMA Engine support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) depends on ARM64 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) depends on PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) Support HiSilicon Kunpeng DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) config IMG_MDC_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) tristate "IMG MDC support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) depends on MIPS || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) depends on MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) Enable support for the IMG multi-threaded DMA controller (MDC).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) config IMX_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) tristate "i.MX DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) depends on ARCH_MXC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) Support the i.MX DMA engine. This engine is integrated into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) Freescale i.MX1/21/27 chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) config IMX_SDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) tristate "i.MX SDMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) depends on ARCH_MXC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) Support the i.MX SDMA engine. This engine is integrated into
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) Freescale i.MX25/31/35/51/53/6 chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) config INTEL_IDMA64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) tristate "Intel integrated DMA 64-bit support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) Enable DMA support for Intel Low Power Subsystem such as found on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) Intel Skylake PCH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) config INTEL_IDXD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) tristate "Intel Data Accelerators support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) depends on PCI && X86_64 && !UML
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) depends on PCI_MSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) depends on SBITMAP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) Enable support for the Intel(R) data accelerators present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) in Intel Xeon CPU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) Say Y if you have such a platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) config INTEL_IOATDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) tristate "Intel I/OAT DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) depends on PCI && X86_64 && !UML
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) select DMA_ENGINE_RAID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) select DCA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) Enable support for the Intel(R) I/OAT DMA engine present
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) in recent Intel Xeon chipsets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) Say Y here if you have such a chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) config INTEL_IOP_ADMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) tristate "Intel IOP32x ADMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) depends on ARCH_IOP32X || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) select ASYNC_TX_ENABLE_CHANNEL_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) Enable support for the Intel(R) IOP Series RAID engines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) config K3_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) tristate "Hisilicon K3 DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) depends on ARCH_HI3xxx || ARCH_HISI || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) Support the DMA engine for Hisilicon K3 platform
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) config LPC18XX_DMAMUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) bool "NXP LPC18xx/43xx DMA MUX for PL080"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) depends on ARCH_LPC18XX || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) depends on OF && AMBA_PL08X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) select MFD_SYSCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) Enable support for DMA on NXP LPC18xx/43xx platforms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) with PL080 and multiplexed DMA request lines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) config MCF_EDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) tristate "Freescale eDMA engine support, ColdFire mcf5441x SoCs"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) depends on M5441x || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) Support the Freescale ColdFire eDMA engine, 64-channel
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) implementation that performs complex data transfers with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) minimal intervention from a host processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) This module can be found on Freescale ColdFire mcf5441x SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) config MILBEAUT_HDMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) tristate "Milbeaut AHB DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) depends on ARCH_MILBEAUT || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) Say yes here to support the Socionext Milbeaut
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) HDMAC device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) config MILBEAUT_XDMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) tristate "Milbeaut AXI DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) depends on ARCH_MILBEAUT || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) Say yes here to support the Socionext Milbeaut
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) XDMAC device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) config MMP_PDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) bool "MMP PDMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) depends on ARCH_MMP || ARCH_PXA || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) Support the MMP PDMA engine for PXA and MMP platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) config MMP_TDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) bool "MMP Two-Channel DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) depends on ARCH_MMP || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) select GENERIC_ALLOCATOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) Support the MMP Two-Channel DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) This engine used for MMP Audio DMA and pxa910 SQU.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) config MOXART_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) tristate "MOXART DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) depends on ARCH_MOXART
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) Enable support for the MOXA ART SoC DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) Say Y here if you enabled MMP ADMA, otherwise say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) config MPC512X_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) tristate "Freescale MPC512x built-in DMA engine support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) depends on PPC_MPC512x || PPC_MPC831x
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) Enable support for the Freescale MPC512x built-in DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) config MV_XOR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) bool "Marvell XOR engine support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) depends on PLAT_ORION || ARCH_MVEBU || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) select DMA_ENGINE_RAID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) select ASYNC_TX_ENABLE_CHANNEL_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) Enable support for the Marvell XOR engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) config MV_XOR_V2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) bool "Marvell XOR engine version 2 support "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) depends on ARM64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) select DMA_ENGINE_RAID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) select ASYNC_TX_ENABLE_CHANNEL_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) select GENERIC_MSI_IRQ_DOMAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) Enable support for the Marvell version 2 XOR engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) This engine provides acceleration for copy, XOR and RAID6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) operations, and is available on Marvell Armada 7K and 8K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) config MXS_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) bool "MXS DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) depends on ARCH_MXS || ARCH_MXC || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) select STMP_DEVICE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) Support the MXS DMA engine. This engine including APBH-DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) and APBX-DMA is integrated into some Freescale chips.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) config MX3_IPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) bool "MX3x Image Processing Unit support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) depends on ARCH_MXC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) default y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) If you plan to use the Image Processing unit in the i.MX3x, say
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) Y here. If unsure, select Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) config MX3_IPU_IRQS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int "Number of dynamically mapped interrupts for IPU"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) depends on MX3_IPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) range 2 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) default 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) Out of 137 interrupt sources on i.MX31 IPU only very few are used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) To avoid bloating the irq_desc[] array we allocate a sufficient
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) number of IRQ slots and map them dynamically to specific sources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) config NBPFAXI_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) tristate "Renesas Type-AXI NBPF DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) depends on ARM || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) Support for "Type-AXI" NBPF DMA IPs from Renesas
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) config OWL_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) tristate "Actions Semi Owl SoCs DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) depends on ARCH_ACTIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) Enable support for the Actions Semi Owl SoCs DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) config PCH_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) tristate "Intel EG20T PCH / LAPIS Semicon IOH(ML7213/ML7223/ML7831) DMA"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) depends on PCI && (X86_32 || COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) Enable support for Intel EG20T PCH DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) This driver also can be used for LAPIS Semiconductor IOH(Input/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) Output Hub), ML7213, ML7223 and ML7831.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ML7213 IOH is for IVI(In-Vehicle Infotainment) use, ML7223 IOH is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) for MP(Media Phone) use and ML7831 IOH is for general purpose use.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ML7213/ML7223/ML7831 is companion chip for Intel Atom E6xx series.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) ML7213/ML7223/ML7831 is completely compatible for Intel EG20T PCH.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) config PL330_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) tristate "DMA API Driver for PL330"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) depends on ARM_AMBA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) Select if your platform has one or more PL330 DMACs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) You need to provide platform specific settings via
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) platform_data for a dma-pl330 device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) config PXA_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) bool "PXA DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) depends on (ARCH_MMP || ARCH_PXA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) Support the DMA engine for PXA. It is also compatible with MMP PDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) platform. The internal DMA IP of all PXA variants is supported, with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) 16 to 32 channels for peripheral to memory or memory to memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) config PLX_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) tristate "PLX ExpressLane PEX Switch DMA Engine Support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) depends on PCI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) Some PLX ExpressLane PCI Switches support additional DMA engines.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) These are exposed via extra functions on the switch's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) upstream port. Each function exposes one DMA channel.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) config SIRF_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) tristate "CSR SiRFprimaII/SiRFmarco DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) depends on ARCH_SIRF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) Enable support for the CSR SiRFprimaII DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) config STE_DMA40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) bool "ST-Ericsson DMA40 support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) depends on ARCH_U8500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) Support for ST-Ericsson DMA40 controller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) config ST_FDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) tristate "ST FDMA dmaengine support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) depends on ARCH_STI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) depends on REMOTEPROC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) select ST_SLIM_REMOTEPROC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) Enable support for ST FDMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) It supports 16 independent DMA channels, accepts up to 32 DMA requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) Say Y here if you have such a chipset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) config STM32_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) bool "STMicroelectronics STM32 DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) depends on ARCH_STM32 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) Enable support for the on-chip DMA controller on STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) STM32 MCUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) If you have a board based on such a MCU and wish to use DMA say Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) config STM32_DMAMUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) bool "STMicroelectronics STM32 dma multiplexer support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) depends on STM32_DMA || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) Enable support for the on-chip DMA multiplexer on STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) STM32 MCUs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) If you have a board based on such a MCU and wish to use DMAMUX say Y
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) config STM32_MDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) bool "STMicroelectronics STM32 master dma support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) depends on ARCH_STM32 || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) Enable support for the on-chip MDMA controller on STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) STM32 platforms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) If you have a board based on STM32 SoC and wish to use the master DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) say Y here.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) config SPRD_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) tristate "Spreadtrum DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) depends on ARCH_SPRD || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) Enable support for the on-chip DMA controller on Spreadtrum platform.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) config S3C24XX_DMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) bool "Samsung S3C24XX DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) depends on ARCH_S3C24XX || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) Support for the Samsung S3C24XX DMA controller driver. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) DMA controller is having multiple DMA channels which can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) configured for different peripherals like audio, UART, SPI.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) The DMA controller can transfer data from memory to peripheral,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) periphal to memory, periphal to periphal and memory to memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) config TXX9_DMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) tristate "Toshiba TXx9 SoC DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) depends on MACH_TX49XX || MACH_TX39XX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) Support the TXx9 SoC internal DMA controller. This can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) integrated in chips such as the Toshiba TX4927/38/39.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) config TEGRA20_APB_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) tristate "NVIDIA Tegra20 APB DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) depends on ARCH_TEGRA || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) Support for the NVIDIA Tegra20 APB DMA controller driver. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) DMA controller is having multiple DMA channel which can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) configured for different peripherals like audio, UART, SPI,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) I2C etc which is in APB bus.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) This DMA controller transfers data from memory to peripheral fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) or vice versa. It does not support memory to memory data transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) config TEGRA210_ADMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) tristate "NVIDIA Tegra210 ADMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) depends on (ARCH_TEGRA_210_SOC || COMPILE_TEST)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) Support for the NVIDIA Tegra210 ADMA controller driver. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) DMA controller has multiple DMA channels and is used to service
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) various audio clients in the Tegra210 audio processing engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) (APE). This DMA controller transfers data from memory to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) peripheral and vice versa. It does not support memory to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) memory data transfer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) config TIMB_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) tristate "Timberdale FPGA DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) depends on MFD_TIMBERDALE || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) Enable support for the Timberdale FPGA DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) config UNIPHIER_MDMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) tristate "UniPhier MIO DMAC"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) depends on ARCH_UNIPHIER || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) Enable support for the MIO DMAC (Media I/O DMA controller) on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) UniPhier platform. This DMA controller is used as the external
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) DMA engine of the SD/eMMC controllers of the LD4, Pro4, sLD8 SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) config UNIPHIER_XDMAC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) tristate "UniPhier XDMAC support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) depends on ARCH_UNIPHIER || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) depends on OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) Enable support for the XDMAC (external DMA controller) on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) UniPhier platform. This DMA controller can transfer data from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) memory to memory, memory to peripheral and peripheral to memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) config XGENE_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) tristate "APM X-Gene DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) depends on ARCH_XGENE || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) select DMA_ENGINE_RAID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) select ASYNC_TX_ENABLE_CHANNEL_SWITCH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) Enable support for the APM X-Gene SoC DMA engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) config XILINX_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) tristate "Xilinx AXI DMAS Engine"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) depends on (ARCH_ZYNQ || MICROBLAZE || ARM64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) Enable support for Xilinx AXI VDMA Soft IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) AXI VDMA engine provides high-bandwidth direct memory access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) between memory and AXI4-Stream video type target
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) peripherals including peripherals which support AXI4-
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) Stream Video Protocol. It has two stream interfaces/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) channels, Memory Mapped to Stream (MM2S) and Stream to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) Memory Mapped (S2MM) for the data transfers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) AXI CDMA engine provides high-bandwidth direct memory access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) between a memory-mapped source address and a memory-mapped
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) destination address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) AXI DMA engine provides high-bandwidth one dimensional direct
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) memory access between memory and AXI4-Stream target peripherals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) AXI MCDMA engine provides high-bandwidth direct memory access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) between memory and AXI4-Stream target peripherals. It provides
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) the scatter gather interface with multiple channels independent
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) configuration support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) config XILINX_ZYNQMP_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) tristate "Xilinx ZynqMP DMA Engine"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) depends on (ARCH_ZYNQ || MICROBLAZE || ARM64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) Enable support for Xilinx ZynqMP DMA controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) config XILINX_ZYNQMP_DPDMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) tristate "Xilinx DPDMA Engine"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) depends on HAS_IOMEM && OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) Enable support for Xilinx ZynqMP DisplayPort DMA. Choose this option
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) if you have a Xilinx ZynqMP SoC with a DisplayPort subsystem. The
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) driver provides the dmaengine required by the DisplayPort subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) display driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) config ZX_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) tristate "ZTE ZX DMA support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) depends on ARCH_ZX || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) select DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) select DMA_VIRTUAL_CHANNELS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) Support the DMA engine for ZTE ZX family platform devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) # driver files
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) source "drivers/dma/bestcomm/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) source "drivers/dma/mediatek/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) source "drivers/dma/qcom/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) source "drivers/dma/dw/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) source "drivers/dma/dw-edma/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) source "drivers/dma/hsu/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) source "drivers/dma/sf-pdma/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) source "drivers/dma/sh/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) source "drivers/dma/ti/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) source "drivers/dma/fsl-dpaa2-qdma/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) # clients
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) comment "DMA Clients"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) depends on DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) config ASYNC_TX_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) bool "Async_tx: Offload support for the async_tx api"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) depends on DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) This allows the async_tx api to take advantage of offload engines for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) memcpy, memset, xor, and raid6 p+q operations. If your platform has
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) a dma engine that can perform raid operations and you have enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) MD_RAID456 say Y.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) If unsure, say N.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) config DMATEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) tristate "DMA Test client"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) depends on DMA_ENGINE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) select DMA_ENGINE_RAID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) Simple DMA test client. Say N unless you're debugging a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) DMA Device driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) config DMA_ENGINE_RAID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) bool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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