^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * A devfreq driver for NVIDIA Tegra SoCs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2014 NVIDIA CORPORATION. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Copyright (C) 2014 Google, Inc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/devfreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/workqueue.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include "governor.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ACTMON_GLB_STATUS 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ACTMON_GLB_PERIOD_CTRL 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ACTMON_DEV_CTRL 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ACTMON_DEV_CTRL_K_VAL_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ACTMON_DEV_CTRL_ENB_PERIODIC BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN BIT(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN BIT(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ACTMON_DEV_CTRL_ENB BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ACTMON_DEV_CTRL_STOP 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ACTMON_DEV_UPPER_WMARK 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ACTMON_DEV_LOWER_WMARK 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ACTMON_DEV_INIT_AVG 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ACTMON_DEV_AVG_UPPER_WMARK 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ACTMON_DEV_AVG_LOWER_WMARK 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ACTMON_DEV_COUNT_WEIGHT 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ACTMON_DEV_AVG_COUNT 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ACTMON_DEV_INTR_STATUS 0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ACTMON_INTR_STATUS_CLEAR 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ACTMON_DEV_INTR_CONSECUTIVE_UPPER BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ACTMON_DEV_INTR_CONSECUTIVE_LOWER BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ACTMON_ABOVE_WMARK_WINDOW 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ACTMON_BELOW_WMARK_WINDOW 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ACTMON_BOOST_FREQ_STEP 16000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * Activity counter is incremented every 256 memory transactions, and each
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * transaction takes 4 EMC clocks for Tegra124; So the COUNT_WEIGHT is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) * 4 * 256 = 1024.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ACTMON_COUNT_WEIGHT 0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * ACTMON_AVERAGE_WINDOW_LOG2: default value for @DEV_CTRL_K_VAL, which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * translates to 2 ^ (K_VAL + 1). ex: 2 ^ (6 + 1) = 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ACTMON_AVERAGE_WINDOW_LOG2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ACTMON_SAMPLING_PERIOD 12 /* ms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ACTMON_DEFAULT_AVG_BAND 6 /* 1/10 of % */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define KHZ 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define KHZ_MAX (ULONG_MAX / KHZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* Assume that the bus is saturated if the utilization is 25% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define BUS_SATURATION_RATIO 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * struct tegra_devfreq_device_config - configuration specific to an ACTMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * Coefficients and thresholds are percentages unless otherwise noted
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct tegra_devfreq_device_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) u32 irq_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) /* Factors applied to boost_freq every consecutive watermark breach */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int boost_up_coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int boost_down_coeff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) /* Define the watermark bounds when applied to the current avg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned int boost_up_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int boost_down_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * Threshold of activity (cycles translated to kHz) below which the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * CPU frequency isn't to be taken into account. This is to avoid
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * increasing the EMC frequency when the CPU is very busy but not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * accessing the bus often.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 avg_dependency_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) enum tegra_actmon_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) MCALL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) MCCPU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) static const struct tegra_devfreq_device_config actmon_device_configs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* MCALL: All memory accesses (including from the CPUs) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) .offset = 0x1c0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) .irq_mask = 1 << 26,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) .boost_up_coeff = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) .boost_down_coeff = 50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) .boost_up_threshold = 60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) .boost_down_threshold = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* MCCPU: memory accesses from the CPUs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) .offset = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) .irq_mask = 1 << 25,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) .boost_up_coeff = 800,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) .boost_down_coeff = 40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) .boost_up_threshold = 27,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) .boost_down_threshold = 10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) .avg_dependency_threshold = 16000, /* 16MHz in kHz units */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * struct tegra_devfreq_device - state specific to an ACTMON device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * Frequencies are in kHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct tegra_devfreq_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) const struct tegra_devfreq_device_config *config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Average event count sampled in the last interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) u32 avg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * Extra frequency to increase the target by due to consecutive
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * watermark breaches.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned long boost_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* Optimal frequency calculated from the stats for this device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long target_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct tegra_devfreq {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct devfreq *devfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) struct reset_control *reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct clk *clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct clk *emc_clock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) unsigned long max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) unsigned long cur_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) struct notifier_block clk_rate_change_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) struct delayed_work cpufreq_update_work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) struct notifier_block cpu_rate_change_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct tegra_devfreq_device devices[ARRAY_SIZE(actmon_device_configs)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) unsigned int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) bool started;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) struct tegra_actmon_emc_ratio {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned long cpu_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned long emc_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) static const struct tegra_actmon_emc_ratio actmon_emc_ratios[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) { 1400000, KHZ_MAX },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) { 1200000, 750000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) { 1100000, 600000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) { 1000000, 500000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) { 800000, 375000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) { 500000, 200000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) { 250000, 100000 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) static u32 actmon_readl(struct tegra_devfreq *tegra, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) return readl_relaxed(tegra->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static void actmon_writel(struct tegra_devfreq *tegra, u32 val, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) writel_relaxed(val, tegra->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) static u32 device_readl(struct tegra_devfreq_device *dev, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) return readl_relaxed(dev->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) static void device_writel(struct tegra_devfreq_device *dev, u32 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) writel_relaxed(val, dev->regs + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) static unsigned long do_percent(unsigned long long val, unsigned int pct)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) val = val * pct;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) do_div(val, 100);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * High freq + high boosting percent + large polling interval are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * resulting in integer overflow when watermarks are calculated.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) return min_t(u64, val, U32_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) static void tegra_devfreq_update_avg_wmark(struct tegra_devfreq *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) struct tegra_devfreq_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 avg_band_freq = tegra->max_freq * ACTMON_DEFAULT_AVG_BAND / KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) u32 band = avg_band_freq * tegra->devfreq->profile->polling_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) u32 avg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) avg = min(dev->avg_count, U32_MAX - band);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) device_writel(dev, avg + band, ACTMON_DEV_AVG_UPPER_WMARK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) avg = max(dev->avg_count, band);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) device_writel(dev, avg - band, ACTMON_DEV_AVG_LOWER_WMARK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) static void tegra_devfreq_update_wmark(struct tegra_devfreq *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct tegra_devfreq_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) u32 val = tegra->cur_freq * tegra->devfreq->profile->polling_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) device_writel(dev, do_percent(val, dev->config->boost_up_threshold),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) ACTMON_DEV_UPPER_WMARK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) device_writel(dev, do_percent(val, dev->config->boost_down_threshold),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ACTMON_DEV_LOWER_WMARK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void actmon_isr_device(struct tegra_devfreq *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct tegra_devfreq_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) u32 intr_status, dev_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) dev->avg_count = device_readl(dev, ACTMON_DEV_AVG_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) tegra_devfreq_update_avg_wmark(tegra, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) intr_status = device_readl(dev, ACTMON_DEV_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) dev_ctrl = device_readl(dev, ACTMON_DEV_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_UPPER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * new_boost = min(old_boost * up_coef + step, max_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) dev->boost_freq = do_percent(dev->boost_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) dev->config->boost_up_coeff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) dev->boost_freq += ACTMON_BOOST_FREQ_STEP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) if (dev->boost_freq >= tegra->max_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) dev_ctrl &= ~ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) dev->boost_freq = tegra->max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) } else if (intr_status & ACTMON_DEV_INTR_CONSECUTIVE_LOWER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * new_boost = old_boost * down_coef
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * or 0 if (old_boost * down_coef < step / 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) dev->boost_freq = do_percent(dev->boost_freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) dev->config->boost_down_coeff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) dev_ctrl |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) if (dev->boost_freq < (ACTMON_BOOST_FREQ_STEP >> 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) dev_ctrl &= ~ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) dev->boost_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) device_writel(dev, dev_ctrl, ACTMON_DEV_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) static unsigned long actmon_cpu_to_emc_rate(struct tegra_devfreq *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) unsigned long cpu_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) const struct tegra_actmon_emc_ratio *ratio = actmon_emc_ratios;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) for (i = 0; i < ARRAY_SIZE(actmon_emc_ratios); i++, ratio++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (cpu_freq >= ratio->cpu_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) if (ratio->emc_freq >= tegra->max_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return tegra->max_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) return ratio->emc_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static unsigned long actmon_device_target_freq(struct tegra_devfreq *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct tegra_devfreq_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) unsigned int avg_sustain_coef;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) unsigned long target_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) target_freq = dev->avg_count / tegra->devfreq->profile->polling_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) avg_sustain_coef = 100 * 100 / dev->config->boost_up_threshold;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) target_freq = do_percent(target_freq, avg_sustain_coef);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) return target_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) static void actmon_update_target(struct tegra_devfreq *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) struct tegra_devfreq_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) unsigned long cpu_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) unsigned long static_cpu_emc_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) dev->target_freq = actmon_device_target_freq(tegra, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) if (dev->config->avg_dependency_threshold &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev->config->avg_dependency_threshold <= dev->target_freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) cpu_freq = cpufreq_quick_get(0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static_cpu_emc_freq = actmon_cpu_to_emc_rate(tegra, cpu_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev->target_freq += dev->boost_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev->target_freq = max(dev->target_freq, static_cpu_emc_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dev->target_freq += dev->boost_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static irqreturn_t actmon_thread_isr(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) struct tegra_devfreq *tegra = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) bool handled = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) mutex_lock(&tegra->devfreq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) val = actmon_readl(tegra, ACTMON_GLB_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) if (val & tegra->devices[i].config->irq_mask) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) actmon_isr_device(tegra, tegra->devices + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) handled = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) if (handled)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) update_devfreq(tegra->devfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) mutex_unlock(&tegra->devfreq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return handled ? IRQ_HANDLED : IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int tegra_actmon_clk_notify_cb(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) unsigned long action, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct clk_notifier_data *data = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct tegra_devfreq *tegra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) struct tegra_devfreq_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (action != POST_RATE_CHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) tegra = container_of(nb, struct tegra_devfreq, clk_rate_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) tegra->cur_freq = data->new_rate / KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev = &tegra->devices[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) tegra_devfreq_update_wmark(tegra, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static void tegra_actmon_delayed_update(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct tegra_devfreq *tegra = container_of(work, struct tegra_devfreq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cpufreq_update_work.work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) mutex_lock(&tegra->devfreq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) update_devfreq(tegra->devfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) mutex_unlock(&tegra->devfreq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) static unsigned long
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) tegra_actmon_cpufreq_contribution(struct tegra_devfreq *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned int cpu_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) struct tegra_devfreq_device *actmon_dev = &tegra->devices[MCCPU];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned long static_cpu_emc_freq, dev_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_freq = actmon_device_target_freq(tegra, actmon_dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) /* check whether CPU's freq is taken into account at all */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) if (dev_freq < actmon_dev->config->avg_dependency_threshold)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static_cpu_emc_freq = actmon_cpu_to_emc_rate(tegra, cpu_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (dev_freq + actmon_dev->boost_freq >= static_cpu_emc_freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return static_cpu_emc_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int tegra_actmon_cpu_notify_cb(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned long action, void *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct cpufreq_freqs *freqs = ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct tegra_devfreq *tegra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned long old, new, delay;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (action != CPUFREQ_POSTCHANGE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) tegra = container_of(nb, struct tegra_devfreq, cpu_rate_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * Quickly check whether CPU frequency should be taken into account
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * at all, without blocking CPUFreq's core.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) if (mutex_trylock(&tegra->devfreq->lock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) old = tegra_actmon_cpufreq_contribution(tegra, freqs->old);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) new = tegra_actmon_cpufreq_contribution(tegra, freqs->new);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) mutex_unlock(&tegra->devfreq->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) * If CPU's frequency shouldn't be taken into account at
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) * the moment, then there is no need to update the devfreq's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) * state because ISR will re-check CPU's frequency on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) * next interrupt.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) if (old == new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * CPUFreq driver should support CPUFREQ_ASYNC_NOTIFICATION in order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) * to allow asynchronous notifications. This means we can't block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) * here for too long, otherwise CPUFreq's core will complain with a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) * warning splat.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) delay = msecs_to_jiffies(ACTMON_SAMPLING_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) schedule_delayed_work(&tegra->cpufreq_update_work, delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) static void tegra_actmon_configure_device(struct tegra_devfreq *tegra,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct tegra_devfreq_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) u32 val = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* reset boosting on governor's restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev->boost_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) dev->target_freq = tegra->cur_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev->avg_count = tegra->cur_freq * tegra->devfreq->profile->polling_ms;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) device_writel(dev, dev->avg_count, ACTMON_DEV_INIT_AVG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) tegra_devfreq_update_avg_wmark(tegra, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) tegra_devfreq_update_wmark(tegra, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) device_writel(dev, ACTMON_COUNT_WEIGHT, ACTMON_DEV_COUNT_WEIGHT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) device_writel(dev, ACTMON_INTR_STATUS_CLEAR, ACTMON_DEV_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) val |= ACTMON_DEV_CTRL_ENB_PERIODIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) val |= (ACTMON_AVERAGE_WINDOW_LOG2 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) << ACTMON_DEV_CTRL_K_VAL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) val |= (ACTMON_BELOW_WMARK_WINDOW - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) << ACTMON_DEV_CTRL_CONSECUTIVE_BELOW_WMARK_NUM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) val |= (ACTMON_ABOVE_WMARK_WINDOW - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) << ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_NUM_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) val |= ACTMON_DEV_CTRL_AVG_ABOVE_WMARK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) val |= ACTMON_DEV_CTRL_AVG_BELOW_WMARK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) val |= ACTMON_DEV_CTRL_CONSECUTIVE_ABOVE_WMARK_EN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) val |= ACTMON_DEV_CTRL_ENB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) device_writel(dev, val, ACTMON_DEV_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) static void tegra_actmon_stop_devices(struct tegra_devfreq *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) struct tegra_devfreq_device *dev = tegra->devices;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) for (i = 0; i < ARRAY_SIZE(tegra->devices); i++, dev++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) device_writel(dev, ACTMON_DEV_CTRL_STOP, ACTMON_DEV_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) device_writel(dev, ACTMON_INTR_STATUS_CLEAR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) ACTMON_DEV_INTR_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) static int tegra_actmon_resume(struct tegra_devfreq *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) if (!tegra->devfreq->profile->polling_ms || !tegra->started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) actmon_writel(tegra, tegra->devfreq->profile->polling_ms - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) ACTMON_GLB_PERIOD_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) * CLK notifications are needed in order to reconfigure the upper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) * consecutive watermark in accordance to the actual clock rate
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) * to avoid unnecessary upper interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) err = clk_notifier_register(tegra->emc_clock,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) &tegra->clk_rate_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) dev_err(tegra->devfreq->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) "Failed to register rate change notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) tegra->cur_freq = clk_get_rate(tegra->emc_clock) / KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) for (i = 0; i < ARRAY_SIZE(tegra->devices); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) tegra_actmon_configure_device(tegra, &tegra->devices[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * We are estimating CPU's memory bandwidth requirement based on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * amount of memory accesses and system's load, judging by CPU's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * frequency. We also don't want to receive events about CPU's
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * frequency transaction when governor is stopped, hence notifier
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) * is registered dynamically.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) err = cpufreq_register_notifier(&tegra->cpu_rate_change_nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) CPUFREQ_TRANSITION_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) dev_err(tegra->devfreq->dev.parent,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) "Failed to register rate change notifier: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) goto err_stop;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) enable_irq(tegra->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) err_stop:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) tegra_actmon_stop_devices(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) clk_notifier_unregister(tegra->emc_clock, &tegra->clk_rate_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static int tegra_actmon_start(struct tegra_devfreq *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (!tegra->started) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) tegra->started = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) ret = tegra_actmon_resume(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) tegra->started = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static void tegra_actmon_pause(struct tegra_devfreq *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (!tegra->devfreq->profile->polling_ms || !tegra->started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) disable_irq(tegra->irq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) cpufreq_unregister_notifier(&tegra->cpu_rate_change_nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) CPUFREQ_TRANSITION_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) cancel_delayed_work_sync(&tegra->cpufreq_update_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) tegra_actmon_stop_devices(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) clk_notifier_unregister(tegra->emc_clock, &tegra->clk_rate_change_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) static void tegra_actmon_stop(struct tegra_devfreq *tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) tegra_actmon_pause(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) tegra->started = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int tegra_devfreq_target(struct device *dev, unsigned long *freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) struct tegra_devfreq *tegra = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct devfreq *devfreq = tegra->devfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) struct dev_pm_opp *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) unsigned long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) opp = devfreq_recommended_opp(dev, freq, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (IS_ERR(opp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_err(dev, "Failed to find opp for %lu Hz\n", *freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return PTR_ERR(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) rate = dev_pm_opp_get_freq(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) err = clk_set_min_rate(tegra->emc_clock, rate * KHZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) err = clk_set_rate(tegra->emc_clock, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) goto restore_min_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) restore_min_rate:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) clk_set_min_rate(tegra->emc_clock, devfreq->previous_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int tegra_devfreq_get_dev_status(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) struct devfreq_dev_status *stat)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct tegra_devfreq *tegra = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct tegra_devfreq_device *actmon_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) unsigned long cur_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) cur_freq = READ_ONCE(tegra->cur_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) /* To be used by the tegra governor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) stat->private_data = tegra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /* The below are to be used by the other governors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) stat->current_frequency = cur_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) actmon_dev = &tegra->devices[MCALL];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) /* Number of cycles spent on memory access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) stat->busy_time = device_readl(actmon_dev, ACTMON_DEV_AVG_COUNT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /* The bus can be considered to be saturated way before 100% */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) stat->busy_time *= 100 / BUS_SATURATION_RATIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) /* Number of cycles in a sampling period */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) stat->total_time = tegra->devfreq->profile->polling_ms * cur_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) stat->busy_time = min(stat->busy_time, stat->total_time);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static struct devfreq_dev_profile tegra_devfreq_profile = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) .polling_ms = ACTMON_SAMPLING_PERIOD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) .target = tegra_devfreq_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .get_dev_status = tegra_devfreq_get_dev_status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) static int tegra_governor_get_target(struct devfreq *devfreq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) unsigned long *freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) struct devfreq_dev_status *stat;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) struct tegra_devfreq *tegra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct tegra_devfreq_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) unsigned long target_freq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) err = devfreq_update_stats(devfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) stat = &devfreq->last_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) tegra = stat->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) for (i = 0; i < ARRAY_SIZE(tegra->devices); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) dev = &tegra->devices[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) actmon_update_target(tegra, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) target_freq = max(target_freq, dev->target_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) *freq = target_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int tegra_governor_event_handler(struct devfreq *devfreq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) unsigned int event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct tegra_devfreq *tegra = dev_get_drvdata(devfreq->dev.parent);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) unsigned int *new_delay = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) * Couple devfreq-device with the governor early because it is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) * needed at the moment of governor's start (used by ISR).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) tegra->devfreq = devfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) case DEVFREQ_GOV_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) devfreq_monitor_start(devfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) ret = tegra_actmon_start(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) case DEVFREQ_GOV_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) tegra_actmon_stop(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) devfreq_monitor_stop(devfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) case DEVFREQ_GOV_UPDATE_INTERVAL:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) * ACTMON hardware supports up to 256 milliseconds for the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) * sampling period.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) if (*new_delay > 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) tegra_actmon_pause(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) devfreq_update_interval(devfreq, new_delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) ret = tegra_actmon_resume(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) case DEVFREQ_GOV_SUSPEND:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) tegra_actmon_stop(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) devfreq_monitor_suspend(devfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) case DEVFREQ_GOV_RESUME:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) devfreq_monitor_resume(devfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) ret = tegra_actmon_start(tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) static struct devfreq_governor tegra_devfreq_governor = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .name = "tegra_actmon",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .get_target_freq = tegra_governor_get_target,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .event_handler = tegra_governor_event_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) .immutable = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .interrupt_driven = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int tegra_devfreq_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) struct tegra_devfreq_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) struct tegra_devfreq *tegra;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) struct devfreq *devfreq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) long rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) tegra = devm_kzalloc(&pdev->dev, sizeof(*tegra), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (!tegra)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) tegra->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) if (IS_ERR(tegra->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) return PTR_ERR(tegra->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) tegra->reset = devm_reset_control_get(&pdev->dev, "actmon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (IS_ERR(tegra->reset)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dev_err(&pdev->dev, "Failed to get reset\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return PTR_ERR(tegra->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) tegra->clock = devm_clk_get(&pdev->dev, "actmon");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) if (IS_ERR(tegra->clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) dev_err(&pdev->dev, "Failed to get actmon clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return PTR_ERR(tegra->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) tegra->emc_clock = devm_clk_get(&pdev->dev, "emc");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (IS_ERR(tegra->emc_clock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) dev_err(&pdev->dev, "Failed to get emc clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) return PTR_ERR(tegra->emc_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) err = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) tegra->irq = err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) irq_set_status_flags(tegra->irq, IRQ_NOAUTOEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) err = devm_request_threaded_irq(&pdev->dev, tegra->irq, NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) actmon_thread_isr, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) "tegra-devfreq", tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) dev_err(&pdev->dev, "Interrupt request failed: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) err = clk_prepare_enable(tegra->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "Failed to prepare and enable ACTMON clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) err = reset_control_reset(tegra->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev_err(&pdev->dev, "Failed to reset hardware: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) rate = clk_round_rate(tegra->emc_clock, ULONG_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (rate < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) dev_err(&pdev->dev, "Failed to round clock rate: %ld\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) err = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) goto disable_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) tegra->max_freq = rate / KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) for (i = 0; i < ARRAY_SIZE(actmon_device_configs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) dev = tegra->devices + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) dev->config = actmon_device_configs + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) dev->regs = tegra->regs + dev->config->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) for (rate = 0; rate <= tegra->max_freq * KHZ; rate++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) rate = clk_round_rate(tegra->emc_clock, rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (rate < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dev_err(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) "Failed to round clock rate: %ld\n", rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) err = rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) goto remove_opps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) err = dev_pm_opp_add(&pdev->dev, rate / KHZ, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) dev_err(&pdev->dev, "Failed to add OPP: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) goto remove_opps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) platform_set_drvdata(pdev, tegra);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) tegra->clk_rate_change_nb.notifier_call = tegra_actmon_clk_notify_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) tegra->cpu_rate_change_nb.notifier_call = tegra_actmon_cpu_notify_cb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) INIT_DELAYED_WORK(&tegra->cpufreq_update_work,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) tegra_actmon_delayed_update);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) err = devfreq_add_governor(&tegra_devfreq_governor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) dev_err(&pdev->dev, "Failed to add governor: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) goto remove_opps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) tegra_devfreq_profile.initial_freq = clk_get_rate(tegra->emc_clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) tegra_devfreq_profile.initial_freq /= KHZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) devfreq = devfreq_add_device(&pdev->dev, &tegra_devfreq_profile,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) "tegra_actmon", NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (IS_ERR(devfreq)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) err = PTR_ERR(devfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) goto remove_governor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) remove_governor:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) devfreq_remove_governor(&tegra_devfreq_governor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) remove_opps:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dev_pm_opp_remove_all_dynamic(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) reset_control_reset(tegra->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) disable_clk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) clk_disable_unprepare(tegra->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) static int tegra_devfreq_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) struct tegra_devfreq *tegra = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) devfreq_remove_device(tegra->devfreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) devfreq_remove_governor(&tegra_devfreq_governor);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) dev_pm_opp_remove_all_dynamic(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) reset_control_reset(tegra->reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) clk_disable_unprepare(tegra->clock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) static const struct of_device_id tegra_devfreq_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) { .compatible = "nvidia,tegra30-actmon" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) { .compatible = "nvidia,tegra124-actmon" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) MODULE_DEVICE_TABLE(of, tegra_devfreq_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) static struct platform_driver tegra_devfreq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) .probe = tegra_devfreq_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) .remove = tegra_devfreq_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) .name = "tegra-devfreq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) .of_match_table = tegra_devfreq_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) module_platform_driver(tegra_devfreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) MODULE_DESCRIPTION("Tegra devfreq driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) MODULE_AUTHOR("Tomeu Vizoso <tomeu.vizoso@collabora.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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