^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020, Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef __ROCKCHIP_DMC_TIMING_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define __ROCKCHIP_DMC_TIMING_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) /* hope this define can adapt all future platfor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) static const char * const px30_dts_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) "ddr2_speed_bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) "ddr3_speed_bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) "ddr4_speed_bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) "pd_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) "sr_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) "sr_mc_gate_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) "srpd_lite_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) "standby_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) "auto_pd_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) "auto_sr_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) "ddr2_dll_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) "ddr3_dll_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) "ddr4_dll_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) "phy_dll_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) "ddr2_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) "phy_ddr2_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) "ddr2_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "ddr2_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) "phy_ddr2_ca_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) "phy_ddr2_ck_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) "phy_ddr2_dq_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) "phy_ddr2_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) "ddr3_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) "phy_ddr3_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) "ddr3_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) "ddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) "phy_ddr3_ca_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) "phy_ddr3_ck_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) "phy_ddr3_dq_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) "phy_ddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) "phy_lpddr2_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) "lpddr2_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) "phy_lpddr2_ca_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) "phy_lpddr2_ck_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) "phy_lpddr2_dq_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) "phy_lpddr2_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) "lpddr3_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) "phy_lpddr3_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) "lpddr3_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) "lpddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) "phy_lpddr3_ca_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) "phy_lpddr3_ck_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) "phy_lpddr3_dq_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) "phy_lpddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) "lpddr4_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) "phy_lpddr4_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) "lpddr4_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) "lpddr4_dq_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) "lpddr4_ca_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) "phy_lpddr4_ca_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) "phy_lpddr4_ck_cs_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) "phy_lpddr4_dq_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) "phy_lpddr4_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) "ddr4_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) "phy_ddr4_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) "ddr4_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) "ddr4_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) "phy_ddr4_ca_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) "phy_ddr4_ck_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) "phy_ddr4_dq_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) "phy_ddr4_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct px30_ddr_dts_config_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) unsigned int ddr2_speed_bin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) unsigned int ddr3_speed_bin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) unsigned int ddr4_speed_bin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) unsigned int pd_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) unsigned int sr_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) unsigned int sr_mc_gate_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) unsigned int srpd_lite_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) unsigned int standby_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int auto_pd_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) unsigned int auto_sr_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /* for ddr2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) unsigned int ddr2_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* for ddr3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int ddr3_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) /* for ddr4 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned int ddr4_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) unsigned int phy_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) unsigned int ddr2_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) unsigned int phy_ddr2_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int ddr2_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int ddr2_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) unsigned int phy_ddr2_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) unsigned int phy_ddr2_ck_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) unsigned int phy_ddr2_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) unsigned int phy_ddr2_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) unsigned int ddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) unsigned int phy_ddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) unsigned int ddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) unsigned int ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) unsigned int phy_ddr3_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) unsigned int phy_ddr3_ck_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) unsigned int phy_ddr3_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int phy_ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned int phy_lpddr2_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned int lpddr2_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) unsigned int phy_lpddr2_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) unsigned int phy_lpddr2_ck_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned int phy_lpddr2_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) unsigned int phy_lpddr2_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) unsigned int lpddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int phy_lpddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int lpddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int lpddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int phy_lpddr3_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned int phy_lpddr3_ck_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) unsigned int phy_lpddr3_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned int phy_lpddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) unsigned int lpddr4_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) unsigned int phy_lpddr4_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) unsigned int lpddr4_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned int lpddr4_dq_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) unsigned int lpddr4_ca_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int phy_lpddr4_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int phy_lpddr4_ck_cs_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) unsigned int phy_lpddr4_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) unsigned int phy_lpddr4_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) unsigned int ddr4_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned int phy_ddr4_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) unsigned int ddr4_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) unsigned int ddr4_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) unsigned int phy_ddr4_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) unsigned int phy_ddr4_ck_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) unsigned int phy_ddr4_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) unsigned int phy_ddr4_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) unsigned int ca_skew[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) unsigned int cs0_skew[44];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) unsigned int cs1_skew[44];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) unsigned int available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) static const char * const rk1808_dts_ca_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) "a0_ddr3a9_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) "a1_ddr3a14_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) "a2_ddr3a13_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) "a3_ddr3a11_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) "a4_ddr3a2_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) "a5_ddr3a4_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) "a6_ddr3a3_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) "a7_ddr3a6_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) "a8_ddr3a5_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) "a9_ddr3a1_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) "a10_ddr3a0_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) "a11_ddr3a7_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) "a12_ddr3casb_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) "a13_ddr3a8_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) "a14_ddr3odt0_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) "a15_ddr3ba1_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) "a16_ddr3rasb_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) "a17_ddr3null_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) "ba0_ddr3ba2_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) "ba1_ddr3a12_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) "bg0_ddr3ba0_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) "bg1_ddr3web_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) "cke_ddr3cke_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) "ck_ddr3ck_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) "ckb_ddr3ckb_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) "csb0_ddr3a10_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) "odt0_ddr3a15_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) "resetn_ddr3resetn_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) "actn_ddr3csb0_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) "csb1_ddr3csb1_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) "odt1_ddr3odt1_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) static const char * const rk1808_dts_cs0_a_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) "cs0_dm0_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) "cs0_dm0_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) "cs0_dq0_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) "cs0_dq0_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) "cs0_dq1_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) "cs0_dq1_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) "cs0_dq2_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) "cs0_dq2_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) "cs0_dq3_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) "cs0_dq3_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) "cs0_dq4_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) "cs0_dq4_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) "cs0_dq5_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) "cs0_dq5_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) "cs0_dq6_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) "cs0_dq6_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) "cs0_dq7_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) "cs0_dq7_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) "cs0_dqs0p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) "cs0_dqs0p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) "cs0_dqs0n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) "cs0_dm1_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) "cs0_dm1_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) "cs0_dq8_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) "cs0_dq8_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) "cs0_dq9_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) "cs0_dq9_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) "cs0_dq10_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) "cs0_dq10_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) "cs0_dq11_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) "cs0_dq11_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) "cs0_dq12_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) "cs0_dq12_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) "cs0_dq13_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) "cs0_dq13_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) "cs0_dq14_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) "cs0_dq14_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) "cs0_dq15_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) "cs0_dq15_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) "cs0_dqs1p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) "cs0_dqs1p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) "cs0_dqs1n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) "cs0_dqs0n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) "cs0_dqs1n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static const char * const rk1808_dts_cs0_b_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) "cs0_dm2_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) "cs0_dm2_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) "cs0_dq16_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) "cs0_dq16_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) "cs0_dq17_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) "cs0_dq17_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) "cs0_dq18_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) "cs0_dq18_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) "cs0_dq19_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) "cs0_dq19_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) "cs0_dq20_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) "cs0_dq20_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) "cs0_dq21_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) "cs0_dq21_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) "cs0_dq22_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) "cs0_dq22_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) "cs0_dq23_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) "cs0_dq23_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) "cs0_dqs2p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) "cs0_dqs2p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) "cs0_dqs2n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) "cs0_dm3_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) "cs0_dm3_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) "cs0_dq24_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) "cs0_dq24_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "cs0_dq25_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "cs0_dq25_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "cs0_dq26_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "cs0_dq26_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "cs0_dq27_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "cs0_dq27_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "cs0_dq28_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "cs0_dq28_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "cs0_dq29_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "cs0_dq29_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "cs0_dq30_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "cs0_dq30_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "cs0_dq31_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "cs0_dq31_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "cs0_dqs3p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "cs0_dqs3p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) "cs0_dqs3n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) "cs0_dqs2n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) "cs0_dqs3n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) static const char * const rk1808_dts_cs1_a_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "cs1_dm0_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) "cs1_dm0_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) "cs1_dq0_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) "cs1_dq0_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "cs1_dq1_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "cs1_dq1_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "cs1_dq2_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "cs1_dq2_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "cs1_dq3_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "cs1_dq3_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "cs1_dq4_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "cs1_dq4_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) "cs1_dq5_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) "cs1_dq5_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) "cs1_dq6_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "cs1_dq6_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "cs1_dq7_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "cs1_dq7_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "cs1_dqs0p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "cs1_dqs0p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "cs1_dqs0n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "cs1_dm1_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "cs1_dm1_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "cs1_dq8_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "cs1_dq8_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "cs1_dq9_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "cs1_dq9_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) "cs1_dq10_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) "cs1_dq10_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) "cs1_dq11_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) "cs1_dq11_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) "cs1_dq12_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) "cs1_dq12_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) "cs1_dq13_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) "cs1_dq13_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) "cs1_dq14_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) "cs1_dq14_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) "cs1_dq15_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) "cs1_dq15_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) "cs1_dqs1p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) "cs1_dqs1p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) "cs1_dqs1n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) "cs1_dqs0n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) "cs1_dqs1n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) static const char * const rk1808_dts_cs1_b_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) "cs1_dm2_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) "cs1_dm2_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) "cs1_dq16_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) "cs1_dq16_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) "cs1_dq17_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) "cs1_dq17_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) "cs1_dq18_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) "cs1_dq18_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) "cs1_dq19_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) "cs1_dq19_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) "cs1_dq20_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) "cs1_dq20_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) "cs1_dq21_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) "cs1_dq21_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) "cs1_dq22_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) "cs1_dq22_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) "cs1_dq23_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) "cs1_dq23_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) "cs1_dqs2p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) "cs1_dqs2p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) "cs1_dqs2n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) "cs1_dm3_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) "cs1_dm3_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) "cs1_dq24_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) "cs1_dq24_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) "cs1_dq25_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) "cs1_dq25_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) "cs1_dq26_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) "cs1_dq26_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) "cs1_dq27_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) "cs1_dq27_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) "cs1_dq28_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) "cs1_dq28_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) "cs1_dq29_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) "cs1_dq29_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) "cs1_dq30_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) "cs1_dq30_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) "cs1_dq31_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "cs1_dq31_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) "cs1_dqs3p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) "cs1_dqs3p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) "cs1_dqs3n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "cs1_dqs2n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) "cs1_dqs3n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct rk1808_ddr_dts_config_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) unsigned int ddr2_speed_bin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) unsigned int ddr3_speed_bin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) unsigned int ddr4_speed_bin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) unsigned int pd_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) unsigned int sr_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) unsigned int sr_mc_gate_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) unsigned int srpd_lite_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) unsigned int standby_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) unsigned int auto_pd_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) unsigned int auto_sr_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) /* for ddr2 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) unsigned int ddr2_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* for ddr3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) unsigned int ddr3_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* for ddr4 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) unsigned int ddr4_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) unsigned int phy_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) unsigned int ddr2_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) unsigned int phy_ddr2_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) unsigned int ddr2_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) unsigned int ddr2_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) unsigned int phy_ddr2_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) unsigned int phy_ddr2_ck_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned int phy_ddr2_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) unsigned int phy_ddr2_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) unsigned int ddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) unsigned int phy_ddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) unsigned int ddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) unsigned int ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) unsigned int phy_ddr3_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) unsigned int phy_ddr3_ck_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) unsigned int phy_ddr3_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) unsigned int phy_ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned int phy_lpddr2_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned int lpddr2_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) unsigned int phy_lpddr2_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) unsigned int phy_lpddr2_ck_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) unsigned int phy_lpddr2_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) unsigned int phy_lpddr2_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) unsigned int lpddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int phy_lpddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) unsigned int lpddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int lpddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) unsigned int phy_lpddr3_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) unsigned int phy_lpddr3_ck_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned int phy_lpddr3_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) unsigned int phy_lpddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) unsigned int lpddr4_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) unsigned int phy_lpddr4_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) unsigned int lpddr4_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) unsigned int lpddr4_dq_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) unsigned int lpddr4_ca_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) unsigned int phy_lpddr4_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) unsigned int phy_lpddr4_ck_cs_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) unsigned int phy_lpddr4_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) unsigned int phy_lpddr4_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) unsigned int ddr4_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) unsigned int phy_ddr4_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) unsigned int ddr4_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) unsigned int ddr4_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) unsigned int phy_ddr4_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) unsigned int phy_ddr4_ck_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) unsigned int phy_ddr4_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) unsigned int phy_ddr4_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) unsigned int ca_de_skew[31];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) unsigned int cs0_a_de_skew[44];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) unsigned int cs0_b_de_skew[44];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) unsigned int cs1_a_de_skew[44];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) unsigned int cs1_b_de_skew[44];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) unsigned int available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static const char * const rk3128_dts_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) "ddr3_speed_bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) "pd_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) "sr_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) "auto_pd_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) "auto_sr_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) "ddr3_dll_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) "lpddr2_dll_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) "phy_dll_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) "ddr3_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) "phy_ddr3_odt_disb_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) "ddr3_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) "ddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) "phy_ddr3_clk_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) "phy_ddr3_cmd_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) "phy_ddr3_dqs_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) "phy_ddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) "lpddr2_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) "phy_lpddr2_clk_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) "phy_lpddr2_cmd_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) "phy_lpddr2_dqs_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) "ddr_2t",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct rk3128_ddr_dts_config_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) u32 ddr3_speed_bin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) u32 pd_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) u32 sr_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) u32 auto_pd_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) u32 auto_sr_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) u32 ddr3_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 lpddr2_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 phy_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) u32 ddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 phy_ddr3_odt_disb_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u32 ddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u32 ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u32 phy_ddr3_clk_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u32 phy_ddr3_cmd_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u32 phy_ddr3_dqs_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u32 phy_ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u32 lpddr2_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u32 phy_lpddr2_clk_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) u32 phy_lpddr2_cmd_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u32 phy_lpddr2_dqs_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u32 ddr_2t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) u32 available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) static const char * const rk3228_dts_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) "dram_spd_bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) "sr_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) "pd_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) "dram_dll_disb_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) "phy_dll_disb_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) "dram_odt_disb_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) "phy_odt_disb_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) "ddr3_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) "ddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) "lpddr3_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) "lpddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) "lpddr2_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) "phy_ddr3_clk_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) "phy_ddr3_cmd_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) "phy_ddr3_dqs_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) "phy_ddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) "phy_lp23_clk_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) "phy_lp23_cmd_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) "phy_lp23_dqs_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) "phy_lp3_odt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct rk3228_ddr_dts_config_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) u32 dram_spd_bin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) u32 sr_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) u32 pd_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) u32 dram_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u32 phy_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u32 dram_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u32 phy_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u32 ddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) u32 ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) u32 lpddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) u32 lpddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) u32 lpddr2_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) u32 phy_ddr3_clk_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) u32 phy_ddr3_cmd_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) u32 phy_ddr3_dqs_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) u32 phy_ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) u32 phy_lp23_clk_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u32 phy_lp23_cmd_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u32 phy_lp23_dqs_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u32 phy_lp3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) static const char * const rk3288_dts_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "ddr3_speed_bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) "pd_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) "sr_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) "auto_pd_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) "auto_sr_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /* for ddr3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) "ddr3_dll_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) "phy_dll_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) "ddr3_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) "phy_ddr3_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) "ddr3_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) "ddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) "phy_ddr3_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) "phy_ddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) "lpddr2_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) "phy_lpddr2_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) "lpddr3_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) "phy_lpddr3_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) "lpddr3_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) "lpddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) "phy_lpddr3_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) "phy_lpddr3_odt"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct rk3288_ddr_dts_config_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) unsigned int ddr3_speed_bin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) unsigned int pd_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) unsigned int sr_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) unsigned int auto_pd_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) unsigned int auto_sr_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) /* for ddr3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) unsigned int ddr3_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) unsigned int phy_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) unsigned int ddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) unsigned int phy_ddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned int ddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) unsigned int ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) unsigned int phy_ddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) unsigned int phy_ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) unsigned int lpddr2_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) unsigned int phy_lpddr2_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) unsigned int lpddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) unsigned int phy_lpddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) unsigned int lpddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned int lpddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) unsigned int phy_lpddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) unsigned int phy_lpddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned int available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* hope this define can adapt all future platfor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) static const char * const rk3328_dts_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) "ddr3_speed_bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) "ddr4_speed_bin",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) "pd_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) "sr_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) "sr_mc_gate_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) "srpd_lite_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) "standby_idle",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) "auto_pd_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) "auto_sr_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) "ddr3_dll_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) "ddr4_dll_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) "phy_dll_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) "ddr3_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) "phy_ddr3_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) "ddr3_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) "ddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) "phy_ddr3_ca_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) "phy_ddr3_ck_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) "phy_ddr3_dq_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) "phy_ddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) "lpddr3_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) "phy_lpddr3_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) "lpddr3_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) "lpddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) "phy_lpddr3_ca_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) "phy_lpddr3_ck_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) "phy_lpddr3_dq_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) "phy_lpddr3_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) "lpddr4_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) "phy_lpddr4_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) "lpddr4_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) "lpddr4_dq_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) "lpddr4_ca_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) "phy_lpddr4_ca_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) "phy_lpddr4_ck_cs_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) "phy_lpddr4_dq_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) "phy_lpddr4_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) "ddr4_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) "phy_ddr4_odt_dis_freq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) "ddr4_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) "ddr4_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) "phy_ddr4_ca_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) "phy_ddr4_ck_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) "phy_ddr4_dq_drv",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) "phy_ddr4_odt",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) static const char * const rk3328_dts_ca_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) "ddr3a1_ddr4a9_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) "ddr3a0_ddr4a10_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) "ddr3a3_ddr4a6_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) "ddr3a2_ddr4a4_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) "ddr3a5_ddr4a8_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) "ddr3a4_ddr4a5_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) "ddr3a7_ddr4a11_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) "ddr3a6_ddr4a7_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) "ddr3a9_ddr4a0_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) "ddr3a8_ddr4a13_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) "ddr3a11_ddr4a3_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) "ddr3a10_ddr4cs0_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) "ddr3a13_ddr4a2_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) "ddr3a12_ddr4ba1_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) "ddr3a15_ddr4odt0_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) "ddr3a14_ddr4a1_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) "ddr3ba1_ddr4a15_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) "ddr3ba0_ddr4bg0_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) "ddr3ras_ddr4cke_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) "ddr3ba2_ddr4ba0_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) "ddr3we_ddr4bg1_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) "ddr3cas_ddr4a12_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) "ddr3ckn_ddr4ckn_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) "ddr3ckp_ddr4ckp_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) "ddr3cke_ddr4a16_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) "ddr3odt0_ddr4a14_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) "ddr3cs0_ddr4act_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) "ddr3reset_ddr4reset_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) "ddr3cs1_ddr4cs1_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) "ddr3odt1_ddr4odt1_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) static const char * const rk3328_dts_cs0_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) "cs0_dm0_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) "cs0_dm0_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) "cs0_dq0_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) "cs0_dq0_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) "cs0_dq1_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) "cs0_dq1_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) "cs0_dq2_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) "cs0_dq2_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) "cs0_dq3_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) "cs0_dq3_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) "cs0_dq4_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) "cs0_dq4_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) "cs0_dq5_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) "cs0_dq5_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) "cs0_dq6_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) "cs0_dq6_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) "cs0_dq7_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) "cs0_dq7_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) "cs0_dqs0_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) "cs0_dqs0p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) "cs0_dqs0n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) "cs0_dm1_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) "cs0_dm1_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) "cs0_dq8_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) "cs0_dq8_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) "cs0_dq9_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) "cs0_dq9_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) "cs0_dq10_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) "cs0_dq10_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) "cs0_dq11_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) "cs0_dq11_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "cs0_dq12_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "cs0_dq12_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "cs0_dq13_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) "cs0_dq13_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) "cs0_dq14_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) "cs0_dq14_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) "cs0_dq15_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) "cs0_dq15_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) "cs0_dqs1_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) "cs0_dqs1p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) "cs0_dqs1n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) "cs0_dm2_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) "cs0_dm2_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) "cs0_dq16_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) "cs0_dq16_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) "cs0_dq17_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) "cs0_dq17_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) "cs0_dq18_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) "cs0_dq18_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) "cs0_dq19_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) "cs0_dq19_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) "cs0_dq20_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) "cs0_dq20_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) "cs0_dq21_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) "cs0_dq21_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) "cs0_dq22_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) "cs0_dq22_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) "cs0_dq23_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) "cs0_dq23_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) "cs0_dqs2_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) "cs0_dqs2p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) "cs0_dqs2n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) "cs0_dm3_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) "cs0_dm3_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) "cs0_dq24_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) "cs0_dq24_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) "cs0_dq25_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) "cs0_dq25_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) "cs0_dq26_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) "cs0_dq26_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) "cs0_dq27_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) "cs0_dq27_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) "cs0_dq28_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) "cs0_dq28_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) "cs0_dq29_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) "cs0_dq29_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) "cs0_dq30_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) "cs0_dq30_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) "cs0_dq31_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) "cs0_dq31_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) "cs0_dqs3_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) "cs0_dqs3p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) "cs0_dqs3n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) static const char * const rk3328_dts_cs1_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) "cs1_dm0_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) "cs1_dm0_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) "cs1_dq0_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) "cs1_dq0_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) "cs1_dq1_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) "cs1_dq1_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) "cs1_dq2_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) "cs1_dq2_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) "cs1_dq3_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) "cs1_dq3_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) "cs1_dq4_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) "cs1_dq4_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) "cs1_dq5_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) "cs1_dq5_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) "cs1_dq6_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) "cs1_dq6_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) "cs1_dq7_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) "cs1_dq7_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) "cs1_dqs0_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) "cs1_dqs0p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) "cs1_dqs0n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) "cs1_dm1_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) "cs1_dm1_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) "cs1_dq8_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) "cs1_dq8_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) "cs1_dq9_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) "cs1_dq9_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) "cs1_dq10_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) "cs1_dq10_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) "cs1_dq11_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) "cs1_dq11_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) "cs1_dq12_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) "cs1_dq12_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) "cs1_dq13_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) "cs1_dq13_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) "cs1_dq14_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) "cs1_dq14_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) "cs1_dq15_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) "cs1_dq15_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) "cs1_dqs1_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) "cs1_dqs1p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) "cs1_dqs1n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) "cs1_dm2_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) "cs1_dm2_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) "cs1_dq16_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) "cs1_dq16_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) "cs1_dq17_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) "cs1_dq17_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) "cs1_dq18_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) "cs1_dq18_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) "cs1_dq19_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) "cs1_dq19_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) "cs1_dq20_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) "cs1_dq20_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) "cs1_dq21_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) "cs1_dq21_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) "cs1_dq22_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) "cs1_dq22_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) "cs1_dq23_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) "cs1_dq23_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) "cs1_dqs2_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) "cs1_dqs2p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) "cs1_dqs2n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) "cs1_dm3_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) "cs1_dm3_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) "cs1_dq24_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) "cs1_dq24_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) "cs1_dq25_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) "cs1_dq25_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) "cs1_dq26_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) "cs1_dq26_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) "cs1_dq27_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) "cs1_dq27_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) "cs1_dq28_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) "cs1_dq28_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) "cs1_dq29_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) "cs1_dq29_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) "cs1_dq30_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) "cs1_dq30_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) "cs1_dq31_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) "cs1_dq31_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) "cs1_dqs3_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) "cs1_dqs3p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) "cs1_dqs3n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) struct rk3328_ddr_dts_config_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) unsigned int ddr3_speed_bin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) unsigned int ddr4_speed_bin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) unsigned int pd_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) unsigned int sr_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) unsigned int sr_mc_gate_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) unsigned int srpd_lite_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) unsigned int standby_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) unsigned int auto_pd_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) unsigned int auto_sr_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /* for ddr3 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) unsigned int ddr3_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /* for ddr4 only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) unsigned int ddr4_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) unsigned int phy_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) unsigned int ddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) unsigned int phy_ddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) unsigned int ddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) unsigned int ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) unsigned int phy_ddr3_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) unsigned int phy_ddr3_ck_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) unsigned int phy_ddr3_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) unsigned int phy_ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) unsigned int lpddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) unsigned int phy_lpddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) unsigned int lpddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) unsigned int lpddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) unsigned int phy_lpddr3_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) unsigned int phy_lpddr3_ck_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) unsigned int phy_lpddr3_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) unsigned int phy_lpddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) unsigned int lpddr4_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) unsigned int phy_lpddr4_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) unsigned int lpddr4_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) unsigned int lpddr4_dq_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) unsigned int lpddr4_ca_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) unsigned int phy_lpddr4_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) unsigned int phy_lpddr4_ck_cs_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) unsigned int phy_lpddr4_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) unsigned int phy_lpddr4_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) unsigned int ddr4_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) unsigned int phy_ddr4_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) unsigned int ddr4_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) unsigned int ddr4_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) unsigned int phy_ddr4_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) unsigned int phy_ddr4_ck_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) unsigned int phy_ddr4_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) unsigned int phy_ddr4_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) unsigned int ca_skew[15];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) unsigned int cs0_skew[44];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) unsigned int cs1_skew[44];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) unsigned int available;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) struct rk3328_ddr_de_skew_setting {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) unsigned int ca_de_skew[30];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) unsigned int cs0_de_skew[84];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) unsigned int cs1_de_skew[84];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) struct rk3368_dram_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) u32 dram_spd_bin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) u32 sr_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) u32 pd_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) u32 dram_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) u32 phy_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) u32 dram_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) u32 phy_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) u32 ddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) u32 ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) u32 lpddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u32 lpddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) u32 lpddr2_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) u32 phy_clk_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) u32 phy_cmd_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) u32 phy_dqs_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) u32 phy_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) u32 ddr_2t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) struct rk3399_dram_timing {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) unsigned int ddr3_speed_bin;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) unsigned int pd_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) unsigned int sr_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) unsigned int sr_mc_gate_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) unsigned int srpd_lite_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) unsigned int standby_idle;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) unsigned int auto_lp_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) unsigned int ddr3_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) unsigned int phy_dll_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) unsigned int ddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) unsigned int ddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) unsigned int ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) unsigned int phy_ddr3_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) unsigned int phy_ddr3_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) unsigned int phy_ddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) unsigned int lpddr3_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) unsigned int lpddr3_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) unsigned int lpddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) unsigned int phy_lpddr3_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) unsigned int phy_lpddr3_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) unsigned int phy_lpddr3_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) unsigned int lpddr4_odt_dis_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) unsigned int lpddr4_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) unsigned int lpddr4_dq_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) unsigned int lpddr4_ca_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) unsigned int phy_lpddr4_ca_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) unsigned int phy_lpddr4_ck_cs_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) unsigned int phy_lpddr4_dq_drv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) unsigned int phy_lpddr4_odt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) /* name rule: ddr4(pad_name)_ddr3_lpddr3_lpddr4_de-skew */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) static const char * const rv1126_dts_ca_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) "a0_a3_a3_cke1-a_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) "a1_ba1_null_cke0-b_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) "a2_a9_a9_a4-a_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) "a3_a15_null_a5-b_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) "a4_a6_a6_ck-a_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) "a5_a12_null_odt0-b_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) "a6_ba2_null_a0-a_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) "a7_a4_a4_odt0-a_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) "a8_a1_a1_cke0-a_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) "a9_a5_a5_a5-a_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) "a10_a8_a8_clkb-a_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) "a11_a7_a7_ca2-a_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) "a12_rasn_null_ca1-a_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) "a13_a13_null_ca3-a_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) "a14_a14_null_csb1-b_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) "a15_a10_null_ca0-b_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) "a16_a11_null_csb0-b_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) "a17_null_null_null_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) "ba0_csb1_csb1_csb0-a_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) "ba1_wen_null_cke1-b_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) "bg0_odt1_odt1_csb1-a_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) "bg1_a2_a2_odt1-a_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) "cke0_casb_null_ca1-b_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) "ck_ck_ck_ck-b_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) "ckb_ckb_ckb_ckb-b_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) "csb0_odt0_odt0_ca2-b_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) "odt0_csb0_csb0_ca4-b_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) "resetn_resetn_null-resetn_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) "actn_cke_cke_ca3-b_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) "cke1_null_null_null_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) "csb1_ba0_null_null_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) "odt1_a0_a0_odt1-b_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) static const char * const rv1126_dts_cs0_a_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) "cs0_dm0_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) "cs0_dq0_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) "cs0_dq1_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) "cs0_dq2_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) "cs0_dq3_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) "cs0_dq4_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) "cs0_dq5_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) "cs0_dq6_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) "cs0_dq7_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) "cs0_dqs0p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) "cs0_dqs0n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) "cs0_dm1_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) "cs0_dq8_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) "cs0_dq9_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) "cs0_dq10_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) "cs0_dq11_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) "cs0_dq12_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) "cs0_dq13_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) "cs0_dq14_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) "cs0_dq15_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) "cs0_dqs1p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) "cs0_dqs1n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) "cs0_dm0_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) "cs0_dq0_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) "cs0_dq1_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) "cs0_dq2_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) "cs0_dq3_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) "cs0_dq4_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) "cs0_dq5_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) "cs0_dq6_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) "cs0_dq7_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) "cs0_dqs0p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) "cs0_dqs0n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) "cs0_dm1_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) "cs0_dq8_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) "cs0_dq9_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) "cs0_dq10_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) "cs0_dq11_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) "cs0_dq12_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) "cs0_dq13_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) "cs0_dq14_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) "cs0_dq15_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) "cs0_dqs1p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) "cs0_dqs1n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) static const char * const rv1126_dts_cs0_b_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) "cs0_dm2_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) "cs0_dq16_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) "cs0_dq17_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) "cs0_dq18_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) "cs0_dq19_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) "cs0_dq20_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) "cs0_dq21_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) "cs0_dq22_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) "cs0_dq23_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) "cs0_dqs2p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) "cs0_dqs2n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) "cs0_dm3_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) "cs0_dq24_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) "cs0_dq25_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) "cs0_dq26_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) "cs0_dq27_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) "cs0_dq28_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) "cs0_dq29_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) "cs0_dq30_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) "cs0_dq31_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) "cs0_dqs3p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) "cs0_dqs3n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) "cs0_dm2_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) "cs0_dq16_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) "cs0_dq17_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) "cs0_dq18_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) "cs0_dq19_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) "cs0_dq20_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) "cs0_dq21_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) "cs0_dq22_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) "cs0_dq23_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) "cs0_dqs2p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) "cs0_dqs2n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) "cs0_dm3_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) "cs0_dq24_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) "cs0_dq25_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) "cs0_dq26_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) "cs0_dq27_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) "cs0_dq28_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) "cs0_dq29_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) "cs0_dq30_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) "cs0_dq31_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) "cs0_dqs3p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) "cs0_dqs3n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) static const char * const rv1126_dts_cs1_a_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) "cs1_dm0_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) "cs1_dq0_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) "cs1_dq1_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) "cs1_dq2_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) "cs1_dq3_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) "cs1_dq4_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) "cs1_dq5_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) "cs1_dq6_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) "cs1_dq7_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) "cs1_dqs0p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) "cs1_dqs0n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) "cs1_dm1_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) "cs1_dq8_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) "cs1_dq9_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) "cs1_dq10_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) "cs1_dq11_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) "cs1_dq12_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) "cs1_dq13_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) "cs1_dq14_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) "cs1_dq15_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) "cs1_dqs1p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) "cs1_dqs1n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) "cs1_dm0_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) "cs1_dq0_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) "cs1_dq1_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) "cs1_dq2_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) "cs1_dq3_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) "cs1_dq4_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) "cs1_dq5_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) "cs1_dq6_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) "cs1_dq7_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) "cs1_dqs0p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) "cs1_dqs0n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) "cs1_dm1_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) "cs1_dq8_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) "cs1_dq9_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) "cs1_dq10_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) "cs1_dq11_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) "cs1_dq12_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) "cs1_dq13_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) "cs1_dq14_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) "cs1_dq15_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) "cs1_dqs1p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) "cs1_dqs1n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) static const char * const rv1126_dts_cs1_b_timing[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) "cs1_dm2_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) "cs1_dq16_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) "cs1_dq17_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) "cs1_dq18_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) "cs1_dq19_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) "cs1_dq20_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) "cs1_dq21_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) "cs1_dq22_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) "cs1_dq23_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) "cs1_dqs2p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) "cs1_dqs2n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) "cs1_dm3_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) "cs1_dq24_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) "cs1_dq25_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) "cs1_dq26_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) "cs1_dq27_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) "cs1_dq28_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) "cs1_dq29_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) "cs1_dq30_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) "cs1_dq31_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) "cs1_dqs3p_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) "cs1_dqs3n_rx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) "cs1_dm2_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) "cs1_dq16_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) "cs1_dq17_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) "cs1_dq18_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) "cs1_dq19_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) "cs1_dq20_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) "cs1_dq21_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) "cs1_dq22_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) "cs1_dq23_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) "cs1_dqs2p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) "cs1_dqs2n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) "cs1_dm3_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) "cs1_dq24_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) "cs1_dq25_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) "cs1_dq26_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) "cs1_dq27_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) "cs1_dq28_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) "cs1_dq29_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) "cs1_dq30_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) "cs1_dq31_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) "cs1_dqs3p_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) "cs1_dqs3n_tx_de-skew",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) #endif /* __ROCKCHIP_DMC_TIMING_H__ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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