^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2018, Fuzhou Rockchip Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Tony Xie <tony.xie@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/arm-smccc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/cpufreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/devfreq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_opp.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/regulator/consumer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/rockchip/rockchip_sip.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/string.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <soc/rockchip/rockchip_opp_select.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLUSTER0 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLUSTER1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MAX_CLUSTERS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define to_rockchip_bus_clk_nb(nb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) container_of(nb, struct rockchip_bus, clk_nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define to_rockchip_bus_cpufreq_nb(nb) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) container_of(nb, struct rockchip_bus, cpufreq_nb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct busfreq_table {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) unsigned long volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) struct rockchip_bus {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct regulator *regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) struct notifier_block clk_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) struct notifier_block cpufreq_nb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) struct busfreq_table *freq_table;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) unsigned int max_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned long cur_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) unsigned long cur_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * Busfreq-policy-cpufreq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * If the cpu frequency of two clusters are both less than or equal to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * cpu_high_freq, change bus rate to low_rate, otherwise change it to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * high_rate.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) unsigned long high_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) unsigned long low_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) unsigned int cpu_high_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) unsigned int cpu_freq[MAX_CLUSTERS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) static int rockchip_sip_bus_smc_config(u32 bus_id, u32 cfg, u32 enable_msk)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct arm_smccc_res res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) res = sip_smc_bus_config(bus_id, cfg, enable_msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) return res.a0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) static int rockchip_bus_smc_config(struct rockchip_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) struct device *dev = bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct device_node *child;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) unsigned int enable_msk, bus_id, cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) for_each_available_child_of_node(np, child) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) ret = of_property_read_u32_index(child, "bus-id", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) &bus_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) ret = of_property_read_u32_index(child, "cfg-val", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) dev_info(dev, "get cfg-val error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) if (!cfg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) dev_info(dev, "cfg-val invalid\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) ret = of_property_read_u32_index(child, "enable-msk", 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) &enable_msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) dev_info(dev, "get enable_msk error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) ret = rockchip_sip_bus_smc_config(bus_id, cfg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) enable_msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) dev_info(dev, "bus smc config error: %x!\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) static int rockchip_bus_set_freq_table(struct rockchip_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct device *dev = bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct dev_pm_opp *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) unsigned long freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) int i, count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) count = dev_pm_opp_get_opp_count(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) if (count <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) bus->max_state = count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) bus->freq_table = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) bus->max_state,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) sizeof(*bus->freq_table),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (!bus->freq_table) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) bus->max_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) for (i = 0, freq = 0; i < bus->max_state; i++, freq++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) opp = dev_pm_opp_find_freq_ceil(dev, &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (IS_ERR(opp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) devm_kfree(dev, bus->freq_table);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) bus->max_state = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return PTR_ERR(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bus->freq_table[i].volt = dev_pm_opp_get_voltage(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) bus->freq_table[i].freq = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) static int rockchip_bus_power_control_init(struct rockchip_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct device *dev = bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bus->clk = devm_clk_get(dev, "bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) if (IS_ERR(bus->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) dev_err(dev, "failed to get bus clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) return PTR_ERR(bus->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) bus->regulator = devm_regulator_get(dev, "bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (IS_ERR(bus->regulator)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) dev_err(dev, "failed to get bus regulator\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) return PTR_ERR(bus->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) ret = rockchip_init_opp_table(dev, NULL, "leakage", "pvtm");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) dev_err(dev, "failed to get OPP table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) ret = rockchip_bus_set_freq_table(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) dev_err(dev, "failed to set bus freq table\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static int rockchip_bus_clkfreq_target(struct device *dev, unsigned long freq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct rockchip_bus *bus = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned long target_volt = bus->freq_table[bus->max_state - 1].volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) for (i = 0; i < bus->max_state; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) if (freq <= bus->freq_table[i].freq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) target_volt = bus->freq_table[i].volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) if (bus->cur_volt != target_volt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) dev_dbg(bus->dev, "target_volt: %lu\n", target_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (regulator_set_voltage(bus->regulator, target_volt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) INT_MAX)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) dev_err(dev, "failed to set voltage %lu uV\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) target_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) bus->cur_volt = target_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) static int rockchip_bus_clk_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct clk_notifier_data *ndata = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) struct rockchip_bus *bus = to_rockchip_bus_clk_nb(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dev_dbg(bus->dev, "event %lu, old_rate %lu, new_rate: %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) event, ndata->old_rate, ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) case PRE_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) if (ndata->new_rate > ndata->old_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) ret = rockchip_bus_clkfreq_target(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) case POST_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (ndata->new_rate < ndata->old_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) ret = rockchip_bus_clkfreq_target(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) ndata->new_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) case ABORT_RATE_CHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) if (ndata->new_rate > ndata->old_rate)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ret = rockchip_bus_clkfreq_target(bus->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) ndata->old_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return notifier_from_errno(ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int rockchip_bus_clkfreq(struct rockchip_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct device *dev = bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) unsigned long init_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) ret = rockchip_bus_power_control_init(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) dev_err(dev, "failed to init power control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) init_rate = clk_get_rate(bus->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) ret = rockchip_bus_clkfreq_target(dev, init_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) bus->clk_nb.notifier_call = rockchip_bus_clk_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) ret = clk_notifier_register(bus->clk, &bus->clk_nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) dev_err(dev, "failed to register clock notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static int rockchip_bus_cpufreq_target(struct device *dev, unsigned long freq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) u32 flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct rockchip_bus *bus = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct dev_pm_opp *opp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) unsigned long target_volt, target_rate = freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) if (!bus->regulator) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) dev_dbg(dev, "%luHz -> %luHz\n", bus->cur_rate, target_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) ret = clk_set_rate(bus->clk, target_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) dev_err(bus->dev, "failed to set bus rate %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) target_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) bus->cur_rate = target_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) opp = devfreq_recommended_opp(dev, &target_rate, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) if (IS_ERR(opp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) dev_err(dev, "failed to recommended opp %lu\n", target_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) return PTR_ERR(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) target_volt = dev_pm_opp_get_voltage(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) dev_pm_opp_put(opp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) if (bus->cur_rate == target_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) if (bus->cur_volt == target_volt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = regulator_set_voltage(bus->regulator, target_volt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) INT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) dev_err(dev, "failed to set voltage %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) target_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) bus->cur_volt = target_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) } else if (!bus->cur_volt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) bus->cur_volt = regulator_get_voltage(bus->regulator);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) if (bus->cur_rate < target_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) ret = regulator_set_voltage(bus->regulator, target_volt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) INT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) dev_err(dev, "failed to set voltage %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) target_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ret = clk_set_rate(bus->clk, target_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) dev_err(dev, "failed to set bus rate %lu\n", target_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) if (bus->cur_rate > target_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) ret = regulator_set_voltage(bus->regulator, target_volt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) INT_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_err(dev, "failed to set voltage %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) target_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_dbg(dev, "%luHz %luuV -> %luHz %luuV\n", bus->cur_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) bus->cur_volt, target_rate, target_volt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) bus->cur_rate = target_rate;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) bus->cur_volt = target_volt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) static int rockchip_bus_cpufreq_notifier(struct notifier_block *nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) unsigned long event, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) struct rockchip_bus *bus = to_rockchip_bus_cpufreq_nb(nb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) struct cpufreq_freqs *freqs = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) int id = topology_physical_package_id(freqs->policy->cpu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (id < 0 || id >= MAX_CLUSTERS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) bus->cpu_freq[id] = freqs->new;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) if (!bus->cpu_freq[CLUSTER0] || !bus->cpu_freq[CLUSTER1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return NOTIFY_DONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) switch (event) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) case CPUFREQ_PRECHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if ((bus->cpu_freq[CLUSTER0] > bus->cpu_high_freq ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) bus->cpu_freq[CLUSTER1] > bus->cpu_high_freq) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) bus->cur_rate != bus->high_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) dev_dbg(bus->dev, "cpu%d freq=%d %d, up cci rate to %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) freqs->policy->cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) bus->cpu_freq[CLUSTER0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) bus->cpu_freq[CLUSTER1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) bus->high_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) rockchip_bus_cpufreq_target(bus->dev, bus->high_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) case CPUFREQ_POSTCHANGE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (bus->cpu_freq[CLUSTER0] <= bus->cpu_high_freq &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) bus->cpu_freq[CLUSTER1] <= bus->cpu_high_freq &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) bus->cur_rate != bus->low_rate) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_dbg(bus->dev, "cpu%d freq=%d %d, down cci rate to %lu\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) freqs->policy->cpu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) bus->cpu_freq[CLUSTER0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) bus->cpu_freq[CLUSTER1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) bus->low_rate);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) rockchip_bus_cpufreq_target(bus->dev, bus->low_rate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) return NOTIFY_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) static int rockchip_bus_cpufreq(struct rockchip_bus *bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) struct device *dev = bus->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) if (of_parse_phandle(dev->of_node, "operating-points-v2", 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) ret = rockchip_bus_power_control_init(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) dev_err(dev, "failed to init power control\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) bus->clk = devm_clk_get(dev, "bus");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (IS_ERR(bus->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dev_err(dev, "failed to get bus clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) return PTR_ERR(bus->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) bus->regulator = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) ret = of_property_read_u32(np, "cpu-high-freq", &bus->cpu_high_freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_err(dev, "failed to get cpu-high-freq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) ret = of_property_read_u32(np, "cci-high-freq", &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) dev_err(dev, "failed to get cci-high-freq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) bus->high_rate = freq * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = of_property_read_u32(np, "cci-low-freq", &freq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_err(dev, "failed to get cci-low-freq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) bus->low_rate = freq * 1000;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) bus->cpufreq_nb.notifier_call = rockchip_bus_cpufreq_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) ret = cpufreq_register_notifier(&bus->cpufreq_nb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) CPUFREQ_TRANSITION_NOTIFIER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev_err(dev, "failed to register cpufreq notifier\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static const struct of_device_id rockchip_busfreq_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) { .compatible = "rockchip,px30-bus", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) { .compatible = "rockchip,rk1808-bus", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) { .compatible = "rockchip,rk3288-bus", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) { .compatible = "rockchip,rk3368-bus", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) { .compatible = "rockchip,rk3399-bus", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) { .compatible = "rockchip,rk3568-bus", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) { .compatible = "rockchip,rv1126-bus", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) { },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) MODULE_DEVICE_TABLE(of, rockchip_busfreq_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static int rockchip_busfreq_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct device_node *np = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) struct rockchip_bus *bus;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) const char *policy_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) bus = devm_kzalloc(dev, sizeof(*bus), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (!bus)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) bus->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) platform_set_drvdata(pdev, bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) ret = of_property_read_string(np, "rockchip,busfreq-policy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) &policy_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) dev_info(dev, "failed to get busfreq policy\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) if (!strcmp(policy_name, "smc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) ret = rockchip_bus_smc_config(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) else if (!strcmp(policy_name, "clkfreq"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) ret = rockchip_bus_clkfreq(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) else if (!strcmp(policy_name, "cpufreq"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) ret = rockchip_bus_cpufreq(bus);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) static struct platform_driver rockchip_busfreq_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) .probe = rockchip_busfreq_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) .name = "rockchip,bus",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) .of_match_table = rockchip_busfreq_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) module_platform_driver(rockchip_busfreq_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) MODULE_AUTHOR("Tony Xie <tony.xie@rock-chips.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) MODULE_DESCRIPTION("rockchip busfreq driver with devfreq framework");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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