^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * exynos_ppmu.h - Exynos PPMU header file
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2015 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author : Chanwoo Choi <cw00.choi@samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef __EXYNOS_PPMU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define __EXYNOS_PPMU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) enum ppmu_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) PPMU_DISABLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) PPMU_ENABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) enum ppmu_counter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) PPMU_PMNCNT0 = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) PPMU_PMNCNT1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) PPMU_PMNCNT2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) PPMU_PMNCNT3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) PPMU_PMNCNT_MAX,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /***
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * PPMUv1.1 Definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) enum ppmu_event_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) PPMU_RO_BUSY_CYCLE_CNT = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) PPMU_WO_BUSY_CYCLE_CNT = 0x1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) PPMU_RW_BUSY_CYCLE_CNT = 0x2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) PPMU_RO_REQUEST_CNT = 0x3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) PPMU_WO_REQUEST_CNT = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) PPMU_RO_DATA_CNT = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) PPMU_WO_DATA_CNT = 0x6,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) PPMU_RO_LATENCY = 0x12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) PPMU_WO_LATENCY = 0x16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) enum ppmu_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* PPC control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) PPMU_PMNC = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) PPMU_CNTENS = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) PPMU_CNTENC = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) PPMU_INTENS = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) PPMU_INTENC = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) PPMU_FLAG = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* Cycle Counter and Performance Event Counter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) PPMU_CCNT = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) PPMU_PMCNT0 = 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) PPMU_PMCNT1 = 0x120,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) PPMU_PMCNT2 = 0x130,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) PPMU_PMCNT3_HIGH = 0x140,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) PPMU_PMCNT3_LOW = 0x150,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) /* Bus Event Generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) PPMU_BEVT0SEL = 0x1000,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) PPMU_BEVT1SEL = 0x1100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) PPMU_BEVT2SEL = 0x1200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) PPMU_BEVT3SEL = 0x1300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) PPMU_COUNTER_RESET = 0x1810,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) PPMU_READ_OVERFLOW_CNT = 0x1810,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) PPMU_READ_UNDERFLOW_CNT = 0x1814,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) PPMU_WRITE_OVERFLOW_CNT = 0x1850,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) PPMU_WRITE_UNDERFLOW_CNT = 0x1854,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) PPMU_READ_PENDING_CNT = 0x1880,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) PPMU_WRITE_PENDING_CNT = 0x1884
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /* PMNC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PPMU_PMNC_CC_RESET_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PPMU_PMNC_COUNTER_RESET_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PPMU_PMNC_ENABLE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PPMU_PMNC_START_MODE_MASK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PPMU_PMNC_CC_DIVIDER_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PPMU_PMNC_CC_RESET_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PPMU_PMNC_COUNTER_RESET_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PPMU_PMNC_ENABLE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) /* CNTENS/CNTENC/INTENS/INTENC/FLAG register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PPMU_CCNT_MASK BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PPMU_PMCNT3_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PPMU_PMCNT2_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PPMU_PMCNT1_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PPMU_PMCNT0_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* PPMU_PMNCTx/PPMU_BETxSEL registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define PPMU_PMNCT(x) (PPMU_PMCNT0 + (0x10 * x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define PPMU_BEVTxSEL(x) (PPMU_BEVT0SEL + (0x100 * x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) /***
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * PPMU_V2.0 definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) enum ppmu_v2_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) PPMU_V2_MODE_MANUAL = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) PPMU_V2_MODE_AUTO = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) PPMU_V2_MODE_CIG = 2, /* CIG (Conditional Interrupt Generation) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) enum ppmu_v2_event_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) PPMU_V2_RO_DATA_CNT = 0x4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) PPMU_V2_WO_DATA_CNT = 0x5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) PPMU_V2_EVT3_RW_DATA_CNT = 0x22, /* Only for Event3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) enum ppmu_V2_reg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* PPC control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) PPMU_V2_PMNC = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) PPMU_V2_CNTENS = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) PPMU_V2_CNTENC = 0x0c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) PPMU_V2_INTENS = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) PPMU_V2_INTENC = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) PPMU_V2_FLAG = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Cycle Counter and Performance Event Counter Register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) PPMU_V2_CCNT = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) PPMU_V2_PMCNT0 = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) PPMU_V2_PMCNT1 = 0x38,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) PPMU_V2_PMCNT2 = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) PPMU_V2_PMCNT3_LOW = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) PPMU_V2_PMCNT3_HIGH = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* Bus Event Generator */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) PPMU_V2_CIG_CFG0 = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) PPMU_V2_CIG_CFG1 = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) PPMU_V2_CIG_CFG2 = 0x24,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) PPMU_V2_CIG_RESULT = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) PPMU_V2_CNT_RESET = 0x2c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) PPMU_V2_CNT_AUTO = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) PPMU_V2_CH_EV0_TYPE = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) PPMU_V2_CH_EV1_TYPE = 0x204,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) PPMU_V2_CH_EV2_TYPE = 0x208,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) PPMU_V2_CH_EV3_TYPE = 0x20c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) PPMU_V2_SM_ID_V = 0x220,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) PPMU_V2_SM_ID_A = 0x224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) PPMU_V2_SM_OTHERS_V = 0x228,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) PPMU_V2_SM_OTHERS_A = 0x22c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) PPMU_V2_INTERRUPT_RESET = 0x260,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* PMNC register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PPMU_V2_PMNC_START_MODE_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define PPMU_V2_PMNC_START_MODE_MASK (0x3 << PPMU_V2_PMNC_START_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PPMU_PMNC_CC_RESET_SHIFT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PPMU_PMNC_COUNTER_RESET_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PPMU_PMNC_ENABLE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PPMU_PMNC_START_MODE_MASK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PPMU_PMNC_CC_DIVIDER_MASK BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PPMU_PMNC_CC_RESET_MASK BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PPMU_PMNC_COUNTER_RESET_MASK BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PPMU_PMNC_ENABLE_MASK BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PPMU_V2_PMNCT(x) (PPMU_V2_PMCNT0 + (0x4 * x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define PPMU_V2_CH_EVx_TYPE(x) (PPMU_V2_CH_EV0_TYPE + (0x4 * x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #endif /* __EXYNOS_PPMU_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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