^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) # SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) menuconfig PM_DEVFREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) bool "Generic Dynamic Voltage and Frequency Scaling (DVFS) support"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) select SRCU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) select PM_OPP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) A device may have a list of frequencies and voltages available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) devfreq, a generic DVFS framework can be registered for a device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) in order to let the governor provided to devfreq choose an
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) operating frequency based on the device driver's policy.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) Each device may have its own governor and policy. Devfreq can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) reevaluate the device state periodically and/or based on the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) notification to "nb", a notifier block, of devfreq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) Like some CPUs with CPUfreq, a device may have multiple clocks.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) However, because the clock frequencies of a single device are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) determined by the single device's state, an instance of devfreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) is attached to a single device and returns a "representative"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) clock frequency of the device, which is also attached
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) to a device by 1-to-1. The device registering devfreq takes the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) responsibility to "interpret" the representative frequency and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) to set its every clock accordingly with the "target" callback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) given to devfreq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) When OPP is used with the devfreq device, it is recommended to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) register devfreq's nb to the OPP's notifier head. If OPP is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) used with the devfreq device, you may use OPP helper
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) functions defined in devfreq.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) if PM_DEVFREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) comment "DEVFREQ Governors"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) config DEVFREQ_GOV_SIMPLE_ONDEMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) tristate "Simple Ondemand"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) Chooses frequency based on the recent load on the device. Works
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) similar as ONDEMAND governor of CPUFREQ does. A device with
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) Simple-Ondemand should be able to provide busy/total counter
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) values that imply the usage rate. A device may provide tuned
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) values to the governor with data field at devfreq_add_device().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) config DEVFREQ_GOV_PERFORMANCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) tristate "Performance"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) Sets the frequency at the maximum available frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) This governor always returns UINT_MAX as frequency so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) the DEVFREQ framework returns the highest frequency available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) at any time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) config DEVFREQ_GOV_POWERSAVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) tristate "Powersave"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) Sets the frequency at the minimum available frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) This governor always returns 0 as frequency so that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) the DEVFREQ framework returns the lowest frequency available
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) at any time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) config DEVFREQ_GOV_USERSPACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) tristate "Userspace"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) Sets the frequency at the user specified one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) This governor returns the user configured frequency if there
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) has been an input to /sys/devices/.../power/devfreq_set_freq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) Otherwise, the governor does not change the frequency
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) given at the initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) config DEVFREQ_GOV_PASSIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) tristate "Passive"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) Sets the frequency based on the frequency of its parent devfreq
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) device. This governor does not change the frequency by itself
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) through sysfs entries. The passive governor recommends that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) devfreq device uses the OPP table to get the frequency/voltage.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) comment "DEVFREQ Drivers"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) config ARM_EXYNOS_BUS_DEVFREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) tristate "ARM Exynos Generic Memory Bus DEVFREQ Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) depends on ARCH_EXYNOS || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) select DEVFREQ_GOV_SIMPLE_ONDEMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) select DEVFREQ_GOV_PASSIVE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) select DEVFREQ_EVENT_EXYNOS_PPMU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) select PM_DEVFREQ_EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) This adds the common DEVFREQ driver for Exynos Memory bus. Exynos
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) Memory bus has one more group of memory bus (e.g, MIF and INT block).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) Each memory bus group could contain many memoby bus block. It reads
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) PPMU counters of memory controllers by using DEVFREQ-event device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) and adjusts the operating frequencies and voltages with OPP support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) This does not yet operate with optimal voltages.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) config ARM_IMX_BUS_DEVFREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) tristate "i.MX Generic Bus DEVFREQ Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) depends on ARCH_MXC || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) select DEVFREQ_GOV_USERSPACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) This adds the generic DEVFREQ driver for i.MX interconnects. It
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) allows adjusting NIC/NOC frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) config ARM_IMX8M_DDRC_DEVFREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) tristate "i.MX8M DDRC DEVFREQ Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) depends on (ARCH_MXC && HAVE_ARM_SMCCC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) (COMPILE_TEST && HAVE_ARM_SMCCC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) select DEVFREQ_GOV_SIMPLE_ONDEMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) select DEVFREQ_GOV_USERSPACE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) This adds the DEVFREQ driver for the i.MX8M DDR Controller. It allows
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) adjusting DRAM frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) config ARM_TEGRA_DEVFREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) tristate "NVIDIA Tegra30/114/124/210 DEVFREQ Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) depends on ARCH_TEGRA_3x_SOC || ARCH_TEGRA_114_SOC || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) ARCH_TEGRA_132_SOC || ARCH_TEGRA_124_SOC || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) ARCH_TEGRA_210_SOC || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) depends on COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) This adds the DEVFREQ driver for the Tegra family of SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) It reads ACTMON counters of memory controllers and adjusts the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) operating frequencies and voltages with OPP support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) config ARM_TEGRA20_DEVFREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) tristate "NVIDIA Tegra20 DEVFREQ Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) depends on (TEGRA_MC && TEGRA20_EMC) || COMPILE_TEST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) depends on COMMON_CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) select DEVFREQ_GOV_SIMPLE_ONDEMAND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) This adds the DEVFREQ driver for the Tegra20 family of SoCs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) It reads Memory Controller counters and adjusts the operating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) frequencies and voltages with OPP support.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) config ARM_ROCKCHIP_BUS_DEVFREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) tristate "ARM ROCKCHIP BUS DEVFREQ Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) depends on ARCH_ROCKCHIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) This adds the DEVFREQ driver for the ROCKCHIP BUS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) config ARM_ROCKCHIP_DMC_DEVFREQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) tristate "ARM ROCKCHIP DMC DEVFREQ Driver"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) (COMPILE_TEST && HAVE_ARM_SMCCC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) select DEVFREQ_EVENT_ROCKCHIP_DFI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) select PM_DEVFREQ_EVENT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) help
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) This adds the DEVFREQ driver for the ROCKCHIP DMC(Dynamic Memory Controller).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) It sets the frequency for the memory controller and reads the usage counts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) from hardware.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) source "drivers/devfreq/event/Kconfig"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) endif # PM_DEVFREQ