^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) ST-Ericsson SA 2010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Shujuan Chen <shujuan.chen@stericsson.com> for ST-Ericsson.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Author: Jonas Linde <jonas.linde@stericsson.com> for ST-Ericsson.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Joakim Bech <joakim.xx.bech@stericsson.com> for ST-Ericsson.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Author: Berne Hebark <berne.herbark@stericsson.com> for ST-Ericsson.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Niklas Hernaeus <niklas.hernaeus@stericsson.com> for ST-Ericsson.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifndef _CRYP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define _CRYP_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/completion.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/klist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DEV_DBG_NAME "crypX crypX:"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* CRYP enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) enum cryp_crypen {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) CRYP_CRYPEN_DISABLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) CRYP_CRYPEN_ENABLE = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* CRYP Start Computation enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) enum cryp_start {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) CRYP_START_DISABLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) CRYP_START_ENABLE = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* CRYP Init Signal enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) enum cryp_init {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) CRYP_INIT_DISABLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) CRYP_INIT_ENABLE = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Cryp State enable/disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) enum cryp_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) CRYP_STATE_DISABLE = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) CRYP_STATE_ENABLE = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Key preparation bit enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) enum cryp_key_prep {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) KSE_DISABLED = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) KSE_ENABLED = 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* Key size for AES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CRYP_KEY_SIZE_128 (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CRYP_KEY_SIZE_192 (1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CRYP_KEY_SIZE_256 (2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* AES modes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) enum cryp_algo_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) CRYP_ALGO_TDES_ECB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) CRYP_ALGO_TDES_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) CRYP_ALGO_DES_ECB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) CRYP_ALGO_DES_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) CRYP_ALGO_AES_ECB,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) CRYP_ALGO_AES_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) CRYP_ALGO_AES_CTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) CRYP_ALGO_AES_XTS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Cryp Encryption or Decryption */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) enum cryp_algorithm_dir {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) CRYP_ALGORITHM_ENCRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) CRYP_ALGORITHM_DECRYPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* Hardware access method */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) enum cryp_mode {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) CRYP_MODE_POLLING,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) CRYP_MODE_INTERRUPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) CRYP_MODE_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * struct cryp_config -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @keysize: Key size for AES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @algomode: AES modes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @algodir: Cryp Encryption or Decryption
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * CRYP configuration structure to be passed to set configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct cryp_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) int keysize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) enum cryp_algo_mode algomode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) enum cryp_algorithm_dir algodir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * struct cryp_protection_config -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @privilege_access: Privileged cryp state enable/disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @secure_access: Secure cryp state enable/disable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * Protection configuration structure for setting privilage access
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct cryp_protection_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) enum cryp_state privilege_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) enum cryp_state secure_access;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* Cryp status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) enum cryp_status_id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) CRYP_STATUS_BUSY = 0x10,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) CRYP_STATUS_OUTPUT_FIFO_FULL = 0x08,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) CRYP_STATUS_OUTPUT_FIFO_NOT_EMPTY = 0x04,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) CRYP_STATUS_INPUT_FIFO_NOT_FULL = 0x02,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) CRYP_STATUS_INPUT_FIFO_EMPTY = 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* Cryp DMA interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CRYP_DMA_TX_FIFO 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CRYP_DMA_RX_FIFO 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) enum cryp_dma_req_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) CRYP_DMA_DISABLE_BOTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) CRYP_DMA_ENABLE_IN_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) CRYP_DMA_ENABLE_OUT_DATA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) CRYP_DMA_ENABLE_BOTH_DIRECTIONS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) enum cryp_dma_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) CRYP_DMA_RX = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) CRYP_DMA_TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* Key registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) enum cryp_key_reg_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) CRYP_KEY_REG_1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) CRYP_KEY_REG_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) CRYP_KEY_REG_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) CRYP_KEY_REG_4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* Key register left and right */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct cryp_key_value {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) u32 key_value_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) u32 key_value_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* Cryp Initialization structure */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) enum cryp_init_vector_index {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) CRYP_INIT_VECTOR_INDEX_0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) CRYP_INIT_VECTOR_INDEX_1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) /* struct cryp_init_vector_value -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @init_value_left
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @init_value_right
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct cryp_init_vector_value {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) u32 init_value_left;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) u32 init_value_right;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * struct cryp_device_context - structure for a cryp context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @cr: control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @dmacr: DMA control register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @imsc: Interrupt mask set/clear register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @key_1_l: Key 1l register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @key_1_r: Key 1r register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @key_2_l: Key 2l register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @key_2_r: Key 2r register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @key_3_l: Key 3l register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @key_3_r: Key 3r register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @key_4_l: Key 4l register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @key_4_r: Key 4r register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @init_vect_0_l: Initialization vector 0l register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @init_vect_0_r: Initialization vector 0r register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @init_vect_1_l: Initialization vector 1l register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @init_vect_1_r: Initialization vector 0r register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @din: Data in register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @dout: Data out register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * CRYP power management specifc structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct cryp_device_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) u32 dmacr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 imsc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) u32 key_1_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) u32 key_1_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) u32 key_2_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) u32 key_2_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) u32 key_3_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) u32 key_3_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) u32 key_4_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) u32 key_4_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) u32 init_vect_0_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) u32 init_vect_0_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 init_vect_1_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) u32 init_vect_1_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 din;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 dout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct cryp_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) struct completion cryp_dma_complete;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct dma_chan *chan_cryp2mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) struct dma_chan *chan_mem2cryp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct stedma40_chan_cfg *cfg_cryp2mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct stedma40_chan_cfg *cfg_mem2cryp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int sg_src_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) int sg_dst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) struct scatterlist *sg_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) struct scatterlist *sg_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) int nents_src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) int nents_dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * struct cryp_device_data - structure for a cryp device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @base: Pointer to virtual base address of the cryp device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @phybase: Pointer to physical memory location of the cryp device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @dev: Pointer to the devices dev structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @clk: Pointer to the device's clock control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @pwr_regulator: Pointer to the device's power control.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @power_status: Current status of the power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @ctx_lock: Lock for current_ctx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @current_ctx: Pointer to the currently allocated context.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @list_node: For inclusion into a klist.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @dma: The dma structure holding channel configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @power_state: TRUE = power state on, FALSE = power state off.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @power_state_spinlock: Spinlock for power_state.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @restore_dev_ctx: TRUE = saved ctx, FALSE = no saved ctx.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) struct cryp_device_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct cryp_register __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) phys_addr_t phybase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) struct regulator *pwr_regulator;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) int power_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) spinlock_t ctx_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct cryp_ctx *current_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) struct klist_node list_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) struct cryp_dma dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) bool power_state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) spinlock_t power_state_spinlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) bool restore_dev_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) void cryp_wait_until_done(struct cryp_device_data *device_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* Initialization functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) int cryp_check(struct cryp_device_data *device_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) void cryp_activity(struct cryp_device_data *device_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) enum cryp_crypen cryp_crypen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) void cryp_flush_inoutfifo(struct cryp_device_data *device_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) int cryp_set_configuration(struct cryp_device_data *device_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) struct cryp_config *cryp_config,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 *control_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) void cryp_configure_for_dma(struct cryp_device_data *device_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) enum cryp_dma_req_type dma_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) int cryp_configure_key_values(struct cryp_device_data *device_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) enum cryp_key_reg_index key_reg_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct cryp_key_value key_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) int cryp_configure_init_vector(struct cryp_device_data *device_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) enum cryp_init_vector_index
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) init_vector_index,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) struct cryp_init_vector_value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) init_vector_value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) int cryp_configure_protection(struct cryp_device_data *device_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct cryp_protection_config *p_protect_config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) /* Power management funtions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) void cryp_save_device_context(struct cryp_device_data *device_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) struct cryp_device_context *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) int cryp_mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) void cryp_restore_device_context(struct cryp_device_data *device_data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct cryp_device_context *ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Data transfer and status bits. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) int cryp_is_logic_busy(struct cryp_device_data *device_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) int cryp_get_status(struct cryp_device_data *device_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * cryp_write_indata - This routine writes 32 bit data into the data input
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * register of the cryptography IP.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * @device_data: Pointer to the device data struct for base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * @write_data: Data to write.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) int cryp_write_indata(struct cryp_device_data *device_data, u32 write_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * cryp_read_outdata - This routine reads the data from the data output
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * register of the CRYP logic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @device_data: Pointer to the device data struct for base address.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) * @read_data: Read the data from the output FIFO.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) int cryp_read_outdata(struct cryp_device_data *device_data, u32 *read_data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #endif /* _CRYP_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags