^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: BSD-3-Clause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Freescale SEC (talitos) device register and descriptor header defines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define TALITOS_TIMEOUT 100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define TALITOS1_MAX_DATA_LEN 32768
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define TALITOS2_MAX_DATA_LEN 65535
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* descriptor pointer entry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) struct talitos_ptr {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) struct { /* SEC2 format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) __be16 len; /* length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) u8 j_extent; /* jump to sg link table and/or extent*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) u8 eptr; /* extended address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) struct { /* SEC1 format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) __be16 res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) __be16 len1; /* length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) __be32 ptr; /* address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct talitos_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) __be32 hdr; /* header high bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) __be32 hdr_lo; /* header low bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) __be32 hdr1; /* header for SEC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) struct talitos_ptr ptr[7]; /* ptr/len pair array */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) __be32 next_desc; /* next descriptor (SEC1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TALITOS_DESC_SIZE (sizeof(struct talitos_desc) - sizeof(__be32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * talitos_edesc - s/w-extended descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @src_nents: number of segments in input scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @dst_nents: number of segments in output scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @iv_dma: dma address of iv for checking continuity and link table
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @dma_len: length of dma mapped link_tbl space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @dma_link_tbl: bus physical address of link_tbl/buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @desc: h/w descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @link_tbl: input and output h/w link tables (if {src,dst}_nents > 1) (SEC2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @buf: input and output buffeur (if {src,dst}_nents > 1) (SEC1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * if decrypting (with authcheck), or either one of src_nents or dst_nents
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * is greater than 1, an integrity check value is concatenated to the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * of link_tbl data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) struct talitos_edesc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) int src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) int dst_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) dma_addr_t iv_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) int dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dma_addr_t dma_link_tbl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct talitos_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct talitos_ptr link_tbl[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u8 buf[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * talitos_request - descriptor submission request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @desc: descriptor pointer (kernel virtual)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @dma_desc: descriptor's physical bus address
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @callback: whom to call when descriptor processing is done
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @context: caller context (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) struct talitos_request {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) struct talitos_desc *desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) dma_addr_t dma_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) void (*callback) (struct device *dev, struct talitos_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) void *context, int error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) void *context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* per-channel fifo management */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) struct talitos_channel {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* request fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct talitos_request *fifo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* number of requests pending in channel h/w fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) atomic_t submit_count ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) /* request submission (head) lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) spinlock_t head_lock ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* index to next free descriptor request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) int head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* request release (tail) lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) spinlock_t tail_lock ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* index to next in-progress/done descriptor request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) int tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct talitos_private {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) struct platform_device *ofdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) void __iomem *reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) void __iomem *reg_deu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) void __iomem *reg_aesu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void __iomem *reg_mdeu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) void __iomem *reg_afeu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) void __iomem *reg_rngu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) void __iomem *reg_pkeu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) void __iomem *reg_keu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) void __iomem *reg_crcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) int irq[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* SEC global registers lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) spinlock_t reg_lock ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* SEC version geometry (from device tree node) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) unsigned int num_channels;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) unsigned int chfifo_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) unsigned int exec_units;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) unsigned int desc_types;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* SEC Compatibility info */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) unsigned long features;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * length of the request fifo
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * fifo_len is chfifo_len rounded up to next power of 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * so we can use bitwise ops to wrap
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) unsigned int fifo_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct talitos_channel *chan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) /* next channel to be assigned next incoming descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) atomic_t last_chan ____cacheline_aligned;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* request callback tasklet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct tasklet_struct done_task[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* list of registered algorithms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct list_head alg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* hwrng device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct hwrng rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) bool rng_registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* .features flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TALITOS_FTR_SHA224_HWINIT 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TALITOS_FTR_HMAC_OK 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TALITOS_FTR_SEC1 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * If both CONFIG_CRYPTO_DEV_TALITOS1 and CONFIG_CRYPTO_DEV_TALITOS2 are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * defined, we check the features which are set according to the device tree.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * Otherwise, we answer true or false directly
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) static inline bool has_ftr_sec1(struct talitos_private *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) if (IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS2))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return priv->features & TALITOS_FTR_SEC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) return IS_ENABLED(CONFIG_CRYPTO_DEV_TALITOS1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) * TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ISR1_FORMAT(x) (((x) << 28) | ((x) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ISR2_FORMAT(x) (((x) << 4) | (x))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* global register offset addresses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TALITOS_MCR 0x1030 /* master control register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TALITOS_MCR_RCA0 (1 << 15) /* remap channel 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TALITOS_MCR_RCA1 (1 << 14) /* remap channel 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TALITOS_MCR_RCA2 (1 << 13) /* remap channel 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TALITOS_MCR_RCA3 (1 << 12) /* remap channel 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TALITOS1_MCR_SWR 0x1000000 /* s/w reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TALITOS2_MCR_SWR 0x1 /* s/w reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TALITOS_MCR_LO 0x1034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TALITOS_IMR 0x1008 /* interrupt mask register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* enable channel IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TALITOS1_IMR_INIT ISR1_FORMAT(0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TALITOS1_IMR_DONE ISR1_FORMAT(0x5) /* done IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* enable channel IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TALITOS2_IMR_INIT (ISR2_FORMAT(0xf) | 0x10000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TALITOS2_IMR_DONE ISR1_FORMAT(0x5) /* done IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TALITOS_IMR_LO 0x100C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TALITOS1_IMR_LO_INIT 0x2000000 /* allow RNGU error IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TALITOS2_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TALITOS_ISR 0x1010 /* interrupt status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TALITOS1_ISR_4CHERR ISR1_FORMAT(0xa) /* 4 ch errors mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TALITOS1_ISR_4CHDONE ISR1_FORMAT(0x5) /* 4 ch done mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TALITOS1_ISR_CH_0_ERR (2 << 28) /* ch 0 errors mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TALITOS1_ISR_CH_0_DONE (1 << 28) /* ch 0 done mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TALITOS1_ISR_TEA_ERR 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TALITOS2_ISR_4CHERR ISR2_FORMAT(0xa) /* 4 ch errors mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TALITOS2_ISR_4CHDONE ISR2_FORMAT(0x5) /* 4 ch done mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TALITOS2_ISR_CH_0_ERR 2 /* ch 0 errors mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TALITOS2_ISR_CH_0_DONE 1 /* ch 0 done mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TALITOS2_ISR_CH_0_2_ERR ISR2_FORMAT(0x2) /* ch 0, 2 err mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TALITOS2_ISR_CH_0_2_DONE ISR2_FORMAT(0x1) /* ch 0, 2 done mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TALITOS2_ISR_CH_1_3_ERR ISR2_FORMAT(0x8) /* ch 1, 3 err mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TALITOS2_ISR_CH_1_3_DONE ISR2_FORMAT(0x4) /* ch 1, 3 done mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TALITOS_ISR_LO 0x1014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TALITOS_ICR 0x1018 /* interrupt clear register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TALITOS_ICR_LO 0x101C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* channel register address stride */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TALITOS_CH_BASE_OFFSET 0x1000 /* default channel map base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TALITOS1_CH_STRIDE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TALITOS2_CH_STRIDE 0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* channel configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TALITOS_CCCR 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TALITOS2_CCCR_CONT 0x2 /* channel continue on SEC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TALITOS2_CCCR_RESET 0x1 /* channel reset on SEC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TALITOS_CCCR_LO 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TALITOS_CCCR_LO_NE 0x8 /* fetch next descriptor enab. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TALITOS_CCCR_LO_NT 0x4 /* notification type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TALITOS1_CCCR_LO_RESET 0x1 /* channel reset on SEC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* CCPSR: channel pointer status register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TALITOS_CCPSR 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TALITOS_CCPSR_LO 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* channel fetch fifo register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TALITOS_FF 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TALITOS_FF_LO 0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* current descriptor pointer register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TALITOS_CDPR 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TALITOS_CDPR_LO 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* descriptor buffer register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TALITOS_DESCBUF 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TALITOS_DESCBUF_LO 0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /* gather link table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TALITOS_GATHER 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TALITOS_GATHER_LO 0xc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) /* scatter link table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TALITOS_SCATTER 0xe0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define TALITOS_SCATTER_LO 0xe4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* execution unit registers base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define TALITOS2_DEU 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define TALITOS2_AESU 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define TALITOS2_MDEU 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define TALITOS2_AFEU 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TALITOS2_RNGU 0xa000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TALITOS2_PKEU 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define TALITOS2_KEU 0xe000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TALITOS2_CRCU 0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define TALITOS12_AESU 0x4000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TALITOS12_DEU 0x5000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define TALITOS12_MDEU 0x6000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TALITOS10_AFEU 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define TALITOS10_DEU 0xa000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TALITOS10_MDEU 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TALITOS10_RNGU 0xe000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TALITOS10_PKEU 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define TALITOS10_AESU 0x12000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* execution unit interrupt status registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define TALITOS_EUDSR 0x10 /* data size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define TALITOS_EUDSR_LO 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define TALITOS_EURCR 0x18 /* reset control*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define TALITOS_EURCR_LO 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define TALITOS_EUSR 0x28 /* rng status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define TALITOS_EUSR_LO 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define TALITOS_EUISR 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define TALITOS_EUISR_LO 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define TALITOS_EUICR 0x38 /* int. control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define TALITOS_EUICR_LO 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define TALITOS_EU_FIFO 0x800 /* output FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define TALITOS_EU_FIFO_LO 0x804 /* output FIFO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* DES unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define TALITOS1_DEUICR_KPE 0x00200000 /* Key Parity Error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* message digest unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* random number unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * talitos descriptor header (hdr) bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* written back when done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define DESC_HDR_DONE cpu_to_be32(0xff000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) /* primary execution unit select */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) /* primary execution unit mode (MODE0) and derivatives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define DESC_HDR_MODE0_AESU_MASK cpu_to_be32(0x00600000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define DESC_HDR_MODE0_AESU_CTR cpu_to_be32(0x00600000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) DESC_HDR_MODE0_MDEU_HMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) DESC_HDR_MODE0_MDEU_HMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) DESC_HDR_MODE0_MDEU_HMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* secondary execution unit select (SEL1) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* secondary execution unit mode (MODE1) and derivatives */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) DESC_HDR_MODE1_MDEU_HMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) DESC_HDR_MODE1_MDEU_HMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) DESC_HDR_MODE1_MDEU_HMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) DESC_HDR_MODE1_MDEU_HMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define DESC_HDR_MODE1_MDEUB_SHA384_HMAC (DESC_HDR_MODE1_MDEUB_SHA384 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) DESC_HDR_MODE1_MDEU_HMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define DESC_HDR_MODE1_MDEUB_SHA512_HMAC (DESC_HDR_MODE1_MDEUB_SHA512 | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) DESC_HDR_MODE1_MDEU_HMAC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* direction of overall data flow (DIR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* request done notification (DN) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /* descriptor types */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* link table extent field bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define DESC_PTR_LNKTBL_JUMP 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define DESC_PTR_LNKTBL_RET 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define DESC_PTR_LNKTBL_NEXT 0x01
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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