^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * talitos - Freescale Integrated Security Engine (SEC) device driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2008-2011 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Scatterlist Crypto API glue code copied from files with the following:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2006-2007 Herbert Xu <herbert@gondor.apana.org.au>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * Crypto algorithm registration code copied from hifn driver:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/crypto.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/of_platform.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/spinlock.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/rtnetlink.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <crypto/algapi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <crypto/aes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <crypto/internal/des.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <crypto/sha.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <crypto/md5.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <crypto/internal/aead.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <crypto/authenc.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <crypto/internal/skcipher.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <crypto/hash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <crypto/internal/hash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <crypto/scatterwalk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #include "talitos.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) static void to_talitos_ptr(struct talitos_ptr *ptr, dma_addr_t dma_addr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) unsigned int len, bool is_sec1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) ptr->ptr = cpu_to_be32(lower_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) if (is_sec1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ptr->len1 = cpu_to_be16(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) ptr->len = cpu_to_be16(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) ptr->eptr = upper_32_bits(dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) static void copy_talitos_ptr(struct talitos_ptr *dst_ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) struct talitos_ptr *src_ptr, bool is_sec1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) dst_ptr->ptr = src_ptr->ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if (is_sec1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) dst_ptr->len1 = src_ptr->len1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) dst_ptr->len = src_ptr->len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) dst_ptr->eptr = src_ptr->eptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) static unsigned short from_talitos_ptr_len(struct talitos_ptr *ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) bool is_sec1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) if (is_sec1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) return be16_to_cpu(ptr->len1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) return be16_to_cpu(ptr->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) static void to_talitos_ptr_ext_set(struct talitos_ptr *ptr, u8 val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) bool is_sec1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) if (!is_sec1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ptr->j_extent = val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) static void to_talitos_ptr_ext_or(struct talitos_ptr *ptr, u8 val, bool is_sec1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) if (!is_sec1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ptr->j_extent |= val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * map virtual single (contiguous) pointer to h/w descriptor pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) static void __map_single_talitos_ptr(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) struct talitos_ptr *ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) unsigned int len, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) enum dma_data_direction dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) unsigned long attrs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) dma_addr_t dma_addr = dma_map_single_attrs(dev, data, len, dir, attrs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) to_talitos_ptr(ptr, dma_addr, len, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) static void map_single_talitos_ptr(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct talitos_ptr *ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int len, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) enum dma_data_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) __map_single_talitos_ptr(dev, ptr, len, data, dir, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static void map_single_talitos_ptr_nosync(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct talitos_ptr *ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) unsigned int len, void *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) enum dma_data_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) __map_single_talitos_ptr(dev, ptr, len, data, dir,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) DMA_ATTR_SKIP_CPU_SYNC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * unmap bus single (contiguous) h/w descriptor pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void unmap_single_talitos_ptr(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct talitos_ptr *ptr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) enum dma_data_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) dma_unmap_single(dev, be32_to_cpu(ptr->ptr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) from_talitos_ptr_len(ptr, is_sec1), dir);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) static int reset_channel(struct device *dev, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) unsigned int timeout = TALITOS_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) if (is_sec1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) TALITOS1_CCCR_LO_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR_LO) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) TALITOS1_CCCR_LO_RESET) && --timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) setbits32(priv->chan[ch].reg + TALITOS_CCCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) TALITOS2_CCCR_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) TALITOS2_CCCR_RESET) && --timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) dev_err(dev, "failed to reset channel %d\n", ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* set 36-bit addressing, done writeback enable and done IRQ enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, TALITOS_CCCR_LO_EAE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) TALITOS_CCCR_LO_CDWE | TALITOS_CCCR_LO_CDIE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* enable chaining descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (is_sec1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) TALITOS_CCCR_LO_NE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* and ICCR writeback, if available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) TALITOS_CCCR_LO_IWSE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) static int reset_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int timeout = TALITOS_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) u32 mcr = is_sec1 ? TALITOS1_MCR_SWR : TALITOS2_MCR_SWR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) setbits32(priv->reg + TALITOS_MCR, mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) while ((in_be32(priv->reg + TALITOS_MCR) & mcr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) && --timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) if (priv->irq[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) mcr = TALITOS_MCR_RCA1 | TALITOS_MCR_RCA3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) setbits32(priv->reg + TALITOS_MCR, mcr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) dev_err(dev, "failed to reset device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * Reset and initialize the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) static int init_device(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) int ch, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * Master reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * errata documentation: warning: certain SEC interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * are not fully cleared by writing the MCR:SWR bit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * set bit twice to completely reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) err = reset_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) err = reset_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* reset channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) for (ch = 0; ch < priv->num_channels; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) err = reset_channel(dev, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* enable channel done and error interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (is_sec1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) clrbits32(priv->reg + TALITOS_IMR, TALITOS1_IMR_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* disable parity error check in DEU (erroneous? test vect.) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) setbits32(priv->reg_deu + TALITOS_EUICR, TALITOS1_DEUICR_KPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) setbits32(priv->reg + TALITOS_IMR, TALITOS2_IMR_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* disable integrity check error interrupts (use writeback instead) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) if (priv->features & TALITOS_FTR_HW_AUTH_CHECK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) setbits32(priv->reg_mdeu + TALITOS_EUICR_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) TALITOS_MDEUICR_LO_ICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * talitos_submit - submits a descriptor to the device for processing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @dev: the SEC device to be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @ch: the SEC device channel to be used
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * @desc: the descriptor to be processed by the device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @callback: whom to call when processing is complete
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * @context: a handle for use by caller (optional)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * desc must contain valid dma-mapped (bus physical) address pointers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * callback must check err and feedback in descriptor header
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * for device processing status.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) void (*callback)(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) struct talitos_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) void *context, int error),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) void *context)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) struct talitos_request *request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) int head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) spin_lock_irqsave(&priv->chan[ch].head_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (!atomic_inc_not_zero(&priv->chan[ch].submit_count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /* h/w fifo is full */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) head = priv->chan[ch].head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) request = &priv->chan[ch].fifo[head];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) /* map descriptor and save caller data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (is_sec1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) desc->hdr1 = desc->hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) request->dma_desc = dma_map_single(dev, &desc->hdr1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) TALITOS_DESC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) request->dma_desc = dma_map_single(dev, desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) TALITOS_DESC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) request->callback = callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) request->context = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* increment fifo head */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) priv->chan[ch].head = (priv->chan[ch].head + 1) & (priv->fifo_len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) request->desc = desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* GO! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) out_be32(priv->chan[ch].reg + TALITOS_FF,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) upper_32_bits(request->dma_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) out_be32(priv->chan[ch].reg + TALITOS_FF_LO,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) lower_32_bits(request->dma_desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) spin_unlock_irqrestore(&priv->chan[ch].head_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) static __be32 get_request_hdr(struct talitos_request *request, bool is_sec1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) struct talitos_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) if (!is_sec1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) return request->desc->hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (!request->desc->next_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return request->desc->hdr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) edesc = container_of(request->desc, struct talitos_edesc, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) return ((struct talitos_desc *)(edesc->buf + edesc->dma_len))->hdr1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * process what was done, notify callback of error if not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) static void flush_channel(struct device *dev, int ch, int error, int reset_ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) struct talitos_request *request, saved_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) int tail, status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) tail = priv->chan[ch].tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) while (priv->chan[ch].fifo[tail].desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) __be32 hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) request = &priv->chan[ch].fifo[tail];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) /* descriptors with their done bits set don't get the error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) hdr = get_request_hdr(request, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) if ((hdr & DESC_HDR_DONE) == DESC_HDR_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) status = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (!error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) status = error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) dma_unmap_single(dev, request->dma_desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) TALITOS_DESC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* copy entries so we can call callback outside lock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) saved_req.desc = request->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) saved_req.callback = request->callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) saved_req.context = request->context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* release request entry in fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) smp_wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) request->desc = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* increment fifo tail */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) priv->chan[ch].tail = (tail + 1) & (priv->fifo_len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) atomic_dec(&priv->chan[ch].submit_count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) saved_req.callback(dev, saved_req.desc, saved_req.context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* channel may resume processing in single desc error case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) if (error && !reset_ch && status == error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) spin_lock_irqsave(&priv->chan[ch].tail_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) tail = priv->chan[ch].tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) spin_unlock_irqrestore(&priv->chan[ch].tail_lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * process completed requests for channels that have done status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define DEF_TALITOS1_DONE(name, ch_done_mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) static void talitos1_done_##name(unsigned long data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) struct device *dev = (struct device *)data; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) struct talitos_private *priv = dev_get_drvdata(dev); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) unsigned long flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) if (ch_done_mask & 0x10000000) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) flush_channel(dev, 0, 0, 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ch_done_mask & 0x40000000) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) flush_channel(dev, 1, 0, 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (ch_done_mask & 0x00010000) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) flush_channel(dev, 2, 0, 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) if (ch_done_mask & 0x00040000) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) flush_channel(dev, 3, 0, 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) /* At this point, all completed channels have been processed */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) /* Unmask done interrupts for channels completed later on. */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) spin_lock_irqsave(&priv->reg_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) clrbits32(priv->reg + TALITOS_IMR_LO, TALITOS1_IMR_LO_INIT); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) spin_unlock_irqrestore(&priv->reg_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) DEF_TALITOS1_DONE(4ch, TALITOS1_ISR_4CHDONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) DEF_TALITOS1_DONE(ch0, TALITOS1_ISR_CH_0_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define DEF_TALITOS2_DONE(name, ch_done_mask) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) static void talitos2_done_##name(unsigned long data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) struct device *dev = (struct device *)data; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct talitos_private *priv = dev_get_drvdata(dev); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) unsigned long flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (ch_done_mask & 1) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) flush_channel(dev, 0, 0, 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (ch_done_mask & (1 << 2)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) flush_channel(dev, 1, 0, 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) if (ch_done_mask & (1 << 4)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) flush_channel(dev, 2, 0, 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) if (ch_done_mask & (1 << 6)) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) flush_channel(dev, 3, 0, 0); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /* At this point, all completed channels have been processed */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) /* Unmask done interrupts for channels completed later on. */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) spin_lock_irqsave(&priv->reg_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) setbits32(priv->reg + TALITOS_IMR_LO, TALITOS2_IMR_LO_INIT); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) spin_unlock_irqrestore(&priv->reg_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) DEF_TALITOS2_DONE(4ch, TALITOS2_ISR_4CHDONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) DEF_TALITOS2_DONE(ch0, TALITOS2_ISR_CH_0_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) DEF_TALITOS2_DONE(ch0_2, TALITOS2_ISR_CH_0_2_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) DEF_TALITOS2_DONE(ch1_3, TALITOS2_ISR_CH_1_3_DONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) * locate current (offending) descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static __be32 current_desc_hdr(struct device *dev, int ch)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) int tail, iter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dma_addr_t cur_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) cur_desc = ((u64)in_be32(priv->chan[ch].reg + TALITOS_CDPR)) << 32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) cur_desc |= in_be32(priv->chan[ch].reg + TALITOS_CDPR_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (!cur_desc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev_err(dev, "CDPR is NULL, giving up search for offending descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) tail = priv->chan[ch].tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) iter = tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) while (priv->chan[ch].fifo[iter].dma_desc != cur_desc &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) priv->chan[ch].fifo[iter].desc->next_desc != cpu_to_be32(cur_desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) iter = (iter + 1) & (priv->fifo_len - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (iter == tail) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) dev_err(dev, "couldn't locate current descriptor\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (priv->chan[ch].fifo[iter].desc->next_desc == cpu_to_be32(cur_desc)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct talitos_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) edesc = container_of(priv->chan[ch].fifo[iter].desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) struct talitos_edesc, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return ((struct talitos_desc *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) (edesc->buf + edesc->dma_len))->hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) return priv->chan[ch].fifo[iter].desc->hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) * user diagnostics; report root cause of error based on execution unit status
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) static void report_eu_error(struct device *dev, int ch, __be32 desc_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (!desc_hdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) desc_hdr = cpu_to_be32(in_be32(priv->chan[ch].reg + TALITOS_DESCBUF));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) switch (desc_hdr & DESC_HDR_SEL0_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) case DESC_HDR_SEL0_AFEU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dev_err(dev, "AFEUISR 0x%08x_%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) in_be32(priv->reg_afeu + TALITOS_EUISR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) in_be32(priv->reg_afeu + TALITOS_EUISR_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) case DESC_HDR_SEL0_DEU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev_err(dev, "DEUISR 0x%08x_%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) in_be32(priv->reg_deu + TALITOS_EUISR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) in_be32(priv->reg_deu + TALITOS_EUISR_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) case DESC_HDR_SEL0_MDEUA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) case DESC_HDR_SEL0_MDEUB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) dev_err(dev, "MDEUISR 0x%08x_%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) in_be32(priv->reg_mdeu + TALITOS_EUISR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) in_be32(priv->reg_mdeu + TALITOS_EUISR_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) case DESC_HDR_SEL0_RNG:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_err(dev, "RNGUISR 0x%08x_%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) in_be32(priv->reg_rngu + TALITOS_ISR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) in_be32(priv->reg_rngu + TALITOS_ISR_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) case DESC_HDR_SEL0_PKEU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dev_err(dev, "PKEUISR 0x%08x_%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) in_be32(priv->reg_pkeu + TALITOS_EUISR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) in_be32(priv->reg_pkeu + TALITOS_EUISR_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) case DESC_HDR_SEL0_AESU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) dev_err(dev, "AESUISR 0x%08x_%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) in_be32(priv->reg_aesu + TALITOS_EUISR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) in_be32(priv->reg_aesu + TALITOS_EUISR_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) case DESC_HDR_SEL0_CRCU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dev_err(dev, "CRCUISR 0x%08x_%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) in_be32(priv->reg_crcu + TALITOS_EUISR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) in_be32(priv->reg_crcu + TALITOS_EUISR_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case DESC_HDR_SEL0_KEU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) dev_err(dev, "KEUISR 0x%08x_%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) in_be32(priv->reg_pkeu + TALITOS_EUISR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) in_be32(priv->reg_pkeu + TALITOS_EUISR_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) switch (desc_hdr & DESC_HDR_SEL1_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) case DESC_HDR_SEL1_MDEUA:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) case DESC_HDR_SEL1_MDEUB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) dev_err(dev, "MDEUISR 0x%08x_%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) in_be32(priv->reg_mdeu + TALITOS_EUISR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) in_be32(priv->reg_mdeu + TALITOS_EUISR_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) case DESC_HDR_SEL1_CRCU:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dev_err(dev, "CRCUISR 0x%08x_%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) in_be32(priv->reg_crcu + TALITOS_EUISR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) in_be32(priv->reg_crcu + TALITOS_EUISR_LO));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) for (i = 0; i < 8; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev_err(dev, "DESCBUF 0x%08x_%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) in_be32(priv->chan[ch].reg + TALITOS_DESCBUF + 8*i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) in_be32(priv->chan[ch].reg + TALITOS_DESCBUF_LO + 8*i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) * recover from error interrupts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) static void talitos_error(struct device *dev, u32 isr, u32 isr_lo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) unsigned int timeout = TALITOS_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) int ch, error, reset_dev = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) u32 v_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) int reset_ch = is_sec1 ? 1 : 0; /* only SEC2 supports continuation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) for (ch = 0; ch < priv->num_channels; ch++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /* skip channels without errors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) if (is_sec1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /* bits 29, 31, 17, 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) if (!(isr & (1 << (29 + (ch & 1) * 2 - (ch & 2) * 6))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) if (!(isr & (1 << (ch * 2 + 1))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) v_lo = in_be32(priv->chan[ch].reg + TALITOS_CCPSR_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) if (v_lo & TALITOS_CCPSR_LO_DOF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) dev_err(dev, "double fetch fifo overflow error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) error = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) reset_ch = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) if (v_lo & TALITOS_CCPSR_LO_SOF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* h/w dropped descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) dev_err(dev, "single fetch fifo overflow error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) error = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (v_lo & TALITOS_CCPSR_LO_MDTE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) dev_err(dev, "master data transfer error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (v_lo & TALITOS_CCPSR_LO_SGDLZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) dev_err(dev, is_sec1 ? "pointer not complete error\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) : "s/g data length zero error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) if (v_lo & TALITOS_CCPSR_LO_FPZ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) dev_err(dev, is_sec1 ? "parity error\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) : "fetch pointer zero error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (v_lo & TALITOS_CCPSR_LO_IDH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) dev_err(dev, "illegal descriptor header error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (v_lo & TALITOS_CCPSR_LO_IEU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) dev_err(dev, is_sec1 ? "static assignment error\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) : "invalid exec unit error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (v_lo & TALITOS_CCPSR_LO_EU)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) report_eu_error(dev, ch, current_desc_hdr(dev, ch));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) if (!is_sec1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (v_lo & TALITOS_CCPSR_LO_GB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dev_err(dev, "gather boundary error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) if (v_lo & TALITOS_CCPSR_LO_GRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) dev_err(dev, "gather return/length error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) if (v_lo & TALITOS_CCPSR_LO_SB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) dev_err(dev, "scatter boundary error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (v_lo & TALITOS_CCPSR_LO_SRL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) dev_err(dev, "scatter return/length error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) flush_channel(dev, ch, error, reset_ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (reset_ch) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) reset_channel(dev, ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) setbits32(priv->chan[ch].reg + TALITOS_CCCR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) TALITOS2_CCCR_CONT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) setbits32(priv->chan[ch].reg + TALITOS_CCCR_LO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) while ((in_be32(priv->chan[ch].reg + TALITOS_CCCR) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) TALITOS2_CCCR_CONT) && --timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) dev_err(dev, "failed to restart channel %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) reset_dev = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (reset_dev || (is_sec1 && isr & ~TALITOS1_ISR_4CHERR) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) (!is_sec1 && isr & ~TALITOS2_ISR_4CHERR) || isr_lo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (is_sec1 && (isr_lo & TALITOS1_ISR_TEA_ERR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) dev_err(dev, "TEA error: ISR 0x%08x_%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) isr, isr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dev_err(dev, "done overflow, internal time out, or "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) "rngu error: ISR 0x%08x_%08x\n", isr, isr_lo);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) /* purge request queues */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) for (ch = 0; ch < priv->num_channels; ch++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) flush_channel(dev, ch, -EIO, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) /* reset and reinitialize the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) init_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) #define DEF_TALITOS1_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static irqreturn_t talitos1_interrupt_##name(int irq, void *data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct device *dev = data; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct talitos_private *priv = dev_get_drvdata(dev); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u32 isr, isr_lo; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) unsigned long flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) spin_lock_irqsave(&priv->reg_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) isr = in_be32(priv->reg + TALITOS_ISR); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) /* Acknowledge interrupt */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) if (unlikely(isr & ch_err_mask || isr_lo & TALITOS1_IMR_LO_INIT)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) spin_unlock_irqrestore(&priv->reg_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) talitos_error(dev, isr & ch_err_mask, isr_lo); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (likely(isr & ch_done_mask)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) /* mask further done interrupts. */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) setbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) /* done_task will unmask done interrupts at exit */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) tasklet_schedule(&priv->done_task[tlet]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) spin_unlock_irqrestore(&priv->reg_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) IRQ_NONE; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) DEF_TALITOS1_INTERRUPT(4ch, TALITOS1_ISR_4CHDONE, TALITOS1_ISR_4CHERR, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define DEF_TALITOS2_INTERRUPT(name, ch_done_mask, ch_err_mask, tlet) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) static irqreturn_t talitos2_interrupt_##name(int irq, void *data) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) struct device *dev = data; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) struct talitos_private *priv = dev_get_drvdata(dev); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) u32 isr, isr_lo; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) unsigned long flags; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) spin_lock_irqsave(&priv->reg_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) isr = in_be32(priv->reg + TALITOS_ISR); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) isr_lo = in_be32(priv->reg + TALITOS_ISR_LO); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /* Acknowledge interrupt */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) out_be32(priv->reg + TALITOS_ICR, isr & (ch_done_mask | ch_err_mask)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) out_be32(priv->reg + TALITOS_ICR_LO, isr_lo); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) if (unlikely(isr & ch_err_mask || isr_lo)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) spin_unlock_irqrestore(&priv->reg_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) talitos_error(dev, isr & ch_err_mask, isr_lo); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) else { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) if (likely(isr & ch_done_mask)) { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /* mask further done interrupts. */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) clrbits32(priv->reg + TALITOS_IMR, ch_done_mask); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* done_task will unmask done interrupts at exit */ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) tasklet_schedule(&priv->done_task[tlet]); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) spin_unlock_irqrestore(&priv->reg_lock, flags); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) } \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) return (isr & (ch_done_mask | ch_err_mask) || isr_lo) ? IRQ_HANDLED : \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) IRQ_NONE; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) DEF_TALITOS2_INTERRUPT(4ch, TALITOS2_ISR_4CHDONE, TALITOS2_ISR_4CHERR, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) DEF_TALITOS2_INTERRUPT(ch0_2, TALITOS2_ISR_CH_0_2_DONE, TALITOS2_ISR_CH_0_2_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) DEF_TALITOS2_INTERRUPT(ch1_3, TALITOS2_ISR_CH_1_3_DONE, TALITOS2_ISR_CH_1_3_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) * hwrng
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) static int talitos_rng_data_present(struct hwrng *rng, int wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) struct device *dev = (struct device *)rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) u32 ofl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) for (i = 0; i < 20; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) ofl = in_be32(priv->reg_rngu + TALITOS_EUSR_LO) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) TALITOS_RNGUSR_LO_OFL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) if (ofl || !wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) udelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return !!ofl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) static int talitos_rng_data_read(struct hwrng *rng, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) struct device *dev = (struct device *)rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /* rng fifo requires 64-bit accesses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) *data = in_be32(priv->reg_rngu + TALITOS_EU_FIFO_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) return sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) static int talitos_rng_init(struct hwrng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) struct device *dev = (struct device *)rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) unsigned int timeout = TALITOS_TIMEOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) setbits32(priv->reg_rngu + TALITOS_EURCR_LO, TALITOS_RNGURCR_LO_SR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) while (!(in_be32(priv->reg_rngu + TALITOS_EUSR_LO)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) & TALITOS_RNGUSR_LO_RD)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) && --timeout)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) cpu_relax();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) if (timeout == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) dev_err(dev, "failed to reset rng hw\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) /* start generating */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) setbits32(priv->reg_rngu + TALITOS_EUDSR_LO, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) static int talitos_register_rng(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) priv->rng.name = dev_driver_string(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) priv->rng.init = talitos_rng_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) priv->rng.data_present = talitos_rng_data_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) priv->rng.data_read = talitos_rng_data_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) priv->rng.priv = (unsigned long)dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) err = hwrng_register(&priv->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) priv->rng_registered = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static void talitos_unregister_rng(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) if (!priv->rng_registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) hwrng_unregister(&priv->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) priv->rng_registered = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) * crypto alg
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define TALITOS_CRA_PRIORITY 3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) * Defines a priority for doing AEAD with descriptors type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) * HMAC_SNOOP_NO_AFEA (HSNA) instead of type IPSEC_ESP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) #define TALITOS_CRA_PRIORITY_AEAD_HSNA (TALITOS_CRA_PRIORITY - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) #ifdef CONFIG_CRYPTO_DEV_TALITOS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) #define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA512_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define TALITOS_MAX_KEY_SIZE (AES_MAX_KEY_SIZE + SHA256_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define TALITOS_MAX_IV_LENGTH 16 /* max of AES_BLOCK_SIZE, DES3_EDE_BLOCK_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) struct talitos_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) int ch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) __be32 desc_hdr_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) u8 key[TALITOS_MAX_KEY_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) u8 iv[TALITOS_MAX_IV_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) dma_addr_t dma_key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) unsigned int keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) unsigned int enckeylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) unsigned int authkeylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define HASH_MAX_BLOCK_SIZE SHA512_BLOCK_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) #define TALITOS_MDEU_MAX_CONTEXT_SIZE TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct talitos_ahash_req_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) unsigned int hw_context_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) u8 buf[2][HASH_MAX_BLOCK_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) int buf_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) unsigned int swinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) unsigned int first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) unsigned int last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) unsigned int to_hash_later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) unsigned int nbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct scatterlist bufsl[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct scatterlist *psrc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) struct talitos_export_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) u32 hw_context[TALITOS_MDEU_MAX_CONTEXT_SIZE / sizeof(u32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) u8 buf[HASH_MAX_BLOCK_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) unsigned int swinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) unsigned int first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) unsigned int last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) unsigned int to_hash_later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) unsigned int nbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) static int aead_setkey(struct crypto_aead *authenc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct crypto_authenc_keys keys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (crypto_authenc_extractkeys(&keys, key, keylen) != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) goto badkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) goto badkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) if (ctx->keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) memcpy(ctx->key, keys.authkey, keys.authkeylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ctx->keylen = keys.authkeylen + keys.enckeylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) ctx->enckeylen = keys.enckeylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) ctx->authkeylen = keys.authkeylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) ctx->dma_key = dma_map_single(dev, ctx->key, ctx->keylen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) memzero_explicit(&keys, sizeof(keys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) badkey:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) memzero_explicit(&keys, sizeof(keys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static int aead_des3_setkey(struct crypto_aead *authenc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) struct crypto_authenc_keys keys;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) err = crypto_authenc_extractkeys(&keys, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (unlikely(err))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (keys.authkeylen + keys.enckeylen > TALITOS_MAX_KEY_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) err = verify_aead_des3_key(authenc, keys.enckey, keys.enckeylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) goto out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (ctx->keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) memcpy(ctx->key, keys.authkey, keys.authkeylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) memcpy(&ctx->key[keys.authkeylen], keys.enckey, keys.enckeylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) ctx->keylen = keys.authkeylen + keys.enckeylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) ctx->enckeylen = keys.enckeylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) ctx->authkeylen = keys.authkeylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) ctx->dma_key = dma_map_single(dev, ctx->key, ctx->keylen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) memzero_explicit(&keys, sizeof(keys));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static void talitos_sg_unmap(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) struct talitos_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct scatterlist *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct scatterlist *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) unsigned int len, unsigned int offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) unsigned int src_nents = edesc->src_nents ? : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) unsigned int dst_nents = edesc->dst_nents ? : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (is_sec1 && dst && dst_nents > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dma_sync_single_for_device(dev, edesc->dma_link_tbl + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) len, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) sg_pcopy_from_buffer(dst, dst_nents, edesc->buf + offset, len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (src != dst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (src_nents == 1 || !is_sec1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dma_unmap_sg(dev, src, src_nents, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) if (dst && (dst_nents == 1 || !is_sec1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) dma_unmap_sg(dev, dst, dst_nents, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) } else if (src_nents == 1 || !is_sec1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) dma_unmap_sg(dev, src, src_nents, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) static void ipsec_esp_unmap(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct talitos_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct aead_request *areq, bool encrypt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct crypto_aead *aead = crypto_aead_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) struct talitos_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) unsigned int ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) unsigned int authsize = crypto_aead_authsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) bool is_ipsec_esp = edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) struct talitos_ptr *civ_ptr = &edesc->desc.ptr[is_ipsec_esp ? 2 : 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (is_ipsec_esp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) unmap_single_talitos_ptr(dev, &edesc->desc.ptr[6],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) unmap_single_talitos_ptr(dev, civ_ptr, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) talitos_sg_unmap(dev, edesc, areq->src, areq->dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) cryptlen + authsize, areq->assoclen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) if (edesc->dma_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) if (!is_ipsec_esp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) unsigned int dst_nents = edesc->dst_nents ? : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) sg_pcopy_to_buffer(areq->dst, dst_nents, ctx->iv, ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) areq->assoclen + cryptlen - ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) * ipsec_esp descriptor callbacks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) static void ipsec_esp_encrypt_done(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) struct talitos_desc *desc, void *context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) struct aead_request *areq = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) unsigned int ivsize = crypto_aead_ivsize(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) struct talitos_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) edesc = container_of(desc, struct talitos_edesc, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) ipsec_esp_unmap(dev, edesc, areq, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) dma_unmap_single(dev, edesc->iv_dma, ivsize, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) kfree(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) aead_request_complete(areq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) static void ipsec_esp_decrypt_swauth_done(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) struct talitos_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) void *context, int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) struct aead_request *req = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) struct crypto_aead *authenc = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) unsigned int authsize = crypto_aead_authsize(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) struct talitos_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) char *oicv, *icv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) edesc = container_of(desc, struct talitos_edesc, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) ipsec_esp_unmap(dev, edesc, req, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) /* auth check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) oicv = edesc->buf + edesc->dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) icv = oicv - authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) err = crypto_memneq(oicv, icv, authsize) ? -EBADMSG : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) kfree(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) aead_request_complete(req, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static void ipsec_esp_decrypt_hwauth_done(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct talitos_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) void *context, int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct aead_request *req = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) struct talitos_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) edesc = container_of(desc, struct talitos_edesc, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) ipsec_esp_unmap(dev, edesc, req, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) /* check ICV auth status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) if (!err && ((desc->hdr_lo & DESC_HDR_LO_ICCR1_MASK) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) DESC_HDR_LO_ICCR1_PASS))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) err = -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) kfree(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) aead_request_complete(req, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) * convert scatterlist to SEC h/w link table format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) * stop at cryptlen bytes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static int sg_to_link_tbl_offset(struct scatterlist *sg, int sg_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) unsigned int offset, int datalen, int elen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct talitos_ptr *link_tbl_ptr, int align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) int n_sg = elen ? sg_count + 1 : sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) int count = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) int cryptlen = datalen + elen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) int padding = ALIGN(cryptlen, align) - cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) while (cryptlen && sg && n_sg--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) unsigned int len = sg_dma_len(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) if (offset >= len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) offset -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) goto next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) len -= offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) if (len > cryptlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) len = cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) if (datalen > 0 && len > datalen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) to_talitos_ptr(link_tbl_ptr + count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) sg_dma_address(sg) + offset, datalen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) to_talitos_ptr_ext_set(link_tbl_ptr + count, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) len -= datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) offset += datalen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) to_talitos_ptr(link_tbl_ptr + count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) sg_dma_address(sg) + offset, sg_next(sg) ? len : len + padding, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) to_talitos_ptr_ext_set(link_tbl_ptr + count, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) count++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) cryptlen -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) datalen -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) next:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) sg = sg_next(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) /* tag end of link table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (count > 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) to_talitos_ptr_ext_set(link_tbl_ptr + count - 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) DESC_PTR_LNKTBL_RET, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) static int talitos_sg_map_ext(struct device *dev, struct scatterlist *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) unsigned int len, struct talitos_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) struct talitos_ptr *ptr, int sg_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) unsigned int offset, int tbl_off, int elen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) bool force, int align)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) int aligned_len = ALIGN(len, align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (!src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) to_talitos_ptr(ptr, 0, 0, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) to_talitos_ptr_ext_set(ptr, elen, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (sg_count == 1 && !force) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) to_talitos_ptr(ptr, sg_dma_address(src) + offset, aligned_len, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) return sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (is_sec1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) to_talitos_ptr(ptr, edesc->dma_link_tbl + offset, aligned_len, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) return sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) sg_count = sg_to_link_tbl_offset(src, sg_count, offset, len, elen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) &edesc->link_tbl[tbl_off], align);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) if (sg_count == 1 && !force) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) /* Only one segment now, so no link tbl needed*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) copy_talitos_ptr(ptr, &edesc->link_tbl[tbl_off], is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) return sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) to_talitos_ptr(ptr, edesc->dma_link_tbl +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) tbl_off * sizeof(struct talitos_ptr), aligned_len, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) to_talitos_ptr_ext_or(ptr, DESC_PTR_LNKTBL_JUMP, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) return sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) static int talitos_sg_map(struct device *dev, struct scatterlist *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) unsigned int len, struct talitos_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) struct talitos_ptr *ptr, int sg_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) unsigned int offset, int tbl_off)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) return talitos_sg_map_ext(dev, src, len, edesc, ptr, sg_count, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) tbl_off, 0, false, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) * fill in and submit ipsec_esp descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) static int ipsec_esp(struct talitos_edesc *edesc, struct aead_request *areq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) bool encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) void (*callback)(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct talitos_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) void *context, int error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) struct crypto_aead *aead = crypto_aead_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) unsigned int authsize = crypto_aead_authsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) struct talitos_ctx *ctx = crypto_aead_ctx(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct talitos_desc *desc = &edesc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) unsigned int ivsize = crypto_aead_ivsize(aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) int tbl_off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) int sg_count, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) int elen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) bool sync_needed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) bool is_ipsec_esp = desc->hdr & DESC_HDR_TYPE_IPSEC_ESP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct talitos_ptr *civ_ptr = &desc->ptr[is_ipsec_esp ? 2 : 3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct talitos_ptr *ckey_ptr = &desc->ptr[is_ipsec_esp ? 3 : 2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) dma_addr_t dma_icv = edesc->dma_link_tbl + edesc->dma_len - authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) /* hmac key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) to_talitos_ptr(&desc->ptr[0], ctx->dma_key, ctx->authkeylen, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) sg_count = edesc->src_nents ?: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) if (is_sec1 && sg_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) sg_copy_to_buffer(areq->src, sg_count, edesc->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) areq->assoclen + cryptlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) sg_count = dma_map_sg(dev, areq->src, sg_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) (areq->src == areq->dst) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) /* hmac data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) ret = talitos_sg_map(dev, areq->src, areq->assoclen, edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) &desc->ptr[1], sg_count, 0, tbl_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) if (ret > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) tbl_off += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) sync_needed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /* cipher iv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) to_talitos_ptr(civ_ptr, edesc->iv_dma, ivsize, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) /* cipher key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) to_talitos_ptr(ckey_ptr, ctx->dma_key + ctx->authkeylen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) ctx->enckeylen, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) * cipher in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) * map and adjust cipher len to aead request cryptlen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) * extent is bytes of HMAC postpended to ciphertext,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) * typically 12 for ipsec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (is_ipsec_esp && (desc->hdr & DESC_HDR_MODE1_MDEU_CICV))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) elen = authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ret = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) sg_count, areq->assoclen, tbl_off, elen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) false, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (ret > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) tbl_off += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) sync_needed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) /* cipher out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) if (areq->src != areq->dst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) sg_count = edesc->dst_nents ? : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) if (!is_sec1 || sg_count == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) if (is_ipsec_esp && encrypt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) elen = authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) elen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) ret = talitos_sg_map_ext(dev, areq->dst, cryptlen, edesc, &desc->ptr[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) sg_count, areq->assoclen, tbl_off, elen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) is_ipsec_esp && !encrypt, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) tbl_off += ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) if (!encrypt && is_ipsec_esp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) struct talitos_ptr *tbl_ptr = &edesc->link_tbl[tbl_off];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* Add an entry to the link table for ICV data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) to_talitos_ptr_ext_set(tbl_ptr - 1, 0, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) to_talitos_ptr_ext_set(tbl_ptr, DESC_PTR_LNKTBL_RET, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* icv data follows link tables */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) to_talitos_ptr(tbl_ptr, dma_icv, authsize, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) to_talitos_ptr_ext_or(&desc->ptr[5], authsize, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) sync_needed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) } else if (!encrypt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) to_talitos_ptr(&desc->ptr[6], dma_icv, authsize, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) sync_needed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) } else if (!is_ipsec_esp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) talitos_sg_map(dev, areq->dst, authsize, edesc, &desc->ptr[6],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) sg_count, areq->assoclen + cryptlen, tbl_off);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) /* iv out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) if (is_ipsec_esp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) map_single_talitos_ptr(dev, &desc->ptr[6], ivsize, ctx->iv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) if (sync_needed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) dma_sync_single_for_device(dev, edesc->dma_link_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) edesc->dma_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) if (ret != -EINPROGRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) ipsec_esp_unmap(dev, edesc, areq, encrypt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) kfree(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) * allocate and map the extended descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) static struct talitos_edesc *talitos_edesc_alloc(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) struct scatterlist *src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) struct scatterlist *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) u8 *iv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) unsigned int assoclen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) unsigned int cryptlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) unsigned int authsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) unsigned int ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) int icv_stashing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) u32 cryptoflags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) bool encrypt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) struct talitos_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) int src_nents, dst_nents, alloc_len, dma_len, src_len, dst_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) dma_addr_t iv_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) gfp_t flags = cryptoflags & CRYPTO_TFM_REQ_MAY_SLEEP ? GFP_KERNEL :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) GFP_ATOMIC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) int max_len = is_sec1 ? TALITOS1_MAX_DATA_LEN : TALITOS2_MAX_DATA_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) if (cryptlen + authsize > max_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) dev_err(dev, "length exceeds h/w max limit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (!dst || dst == src) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) src_len = assoclen + cryptlen + authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) src_nents = sg_nents_for_len(src, src_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (src_nents < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) dev_err(dev, "Invalid number of src SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) src_nents = (src_nents == 1) ? 0 : src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) dst_nents = dst ? src_nents : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) dst_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) } else { /* dst && dst != src*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) src_len = assoclen + cryptlen + (encrypt ? 0 : authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) src_nents = sg_nents_for_len(src, src_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) if (src_nents < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) dev_err(dev, "Invalid number of src SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) src_nents = (src_nents == 1) ? 0 : src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) dst_len = assoclen + cryptlen + (encrypt ? authsize : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) dst_nents = sg_nents_for_len(dst, dst_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) if (dst_nents < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) dev_err(dev, "Invalid number of dst SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) dst_nents = (dst_nents == 1) ? 0 : dst_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) * allocate space for base edesc plus the link tables,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) * allowing for two separate entries for AD and generated ICV (+ 2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) * and space for two sets of ICVs (stashed and generated)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) alloc_len = sizeof(struct talitos_edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) if (src_nents || dst_nents || !encrypt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) if (is_sec1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) dma_len = (src_nents ? src_len : 0) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) (dst_nents ? dst_len : 0) + authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) dma_len = (src_nents + dst_nents + 2) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) sizeof(struct talitos_ptr) + authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) alloc_len += dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) dma_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) alloc_len += icv_stashing ? authsize : 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) /* if its a ahash, add space for a second desc next to the first one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) if (is_sec1 && !dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) alloc_len += sizeof(struct talitos_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) alloc_len += ivsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) edesc = kmalloc(alloc_len, GFP_DMA | flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) if (!edesc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) if (ivsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) iv = memcpy(((u8 *)edesc) + alloc_len - ivsize, iv, ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) iv_dma = dma_map_single(dev, iv, ivsize, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) memset(&edesc->desc, 0, sizeof(edesc->desc));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) edesc->src_nents = src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) edesc->dst_nents = dst_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) edesc->iv_dma = iv_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) edesc->dma_len = dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) if (dma_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) edesc->dma_link_tbl = dma_map_single(dev, &edesc->link_tbl[0],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) edesc->dma_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) return edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) static struct talitos_edesc *aead_edesc_alloc(struct aead_request *areq, u8 *iv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) int icv_stashing, bool encrypt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) struct crypto_aead *authenc = crypto_aead_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) unsigned int authsize = crypto_aead_authsize(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) unsigned int ivsize = crypto_aead_ivsize(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) unsigned int cryptlen = areq->cryptlen - (encrypt ? 0 : authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) iv, areq->assoclen, cryptlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) authsize, ivsize, icv_stashing,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) areq->base.flags, encrypt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static int aead_encrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct crypto_aead *authenc = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) struct talitos_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) /* allocate extended descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) edesc = aead_edesc_alloc(req, req->iv, 0, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) if (IS_ERR(edesc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return PTR_ERR(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) /* set encrypt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) return ipsec_esp(edesc, req, true, ipsec_esp_encrypt_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) static int aead_decrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) struct crypto_aead *authenc = crypto_aead_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) unsigned int authsize = crypto_aead_authsize(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) struct talitos_ctx *ctx = crypto_aead_ctx(authenc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) struct talitos_private *priv = dev_get_drvdata(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) struct talitos_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) void *icvdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) /* allocate extended descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) edesc = aead_edesc_alloc(req, req->iv, 1, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (IS_ERR(edesc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) return PTR_ERR(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if ((edesc->desc.hdr & DESC_HDR_TYPE_IPSEC_ESP) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) (priv->features & TALITOS_FTR_HW_AUTH_CHECK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) ((!edesc->src_nents && !edesc->dst_nents) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) priv->features & TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* decrypt and check the ICV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) edesc->desc.hdr = ctx->desc_hdr_template |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) DESC_HDR_DIR_INBOUND |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) DESC_HDR_MODE1_MDEU_CICV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) /* reset integrity check result bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) return ipsec_esp(edesc, req, false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) ipsec_esp_decrypt_hwauth_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) /* Have to check the ICV with software */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) /* stash incoming ICV for later cmp with ICV generated by the h/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) icvdata = edesc->buf + edesc->dma_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) sg_pcopy_to_buffer(req->src, edesc->src_nents ? : 1, icvdata, authsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) req->assoclen + req->cryptlen - authsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return ipsec_esp(edesc, req, false, ipsec_esp_decrypt_swauth_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) static int skcipher_setkey(struct crypto_skcipher *cipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) if (ctx->keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) memcpy(&ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) ctx->keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) ctx->dma_key = dma_map_single(dev, ctx->key, keylen, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) static int skcipher_des_setkey(struct crypto_skcipher *cipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) return verify_skcipher_des_key(cipher, key) ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) skcipher_setkey(cipher, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) static int skcipher_des3_setkey(struct crypto_skcipher *cipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) return verify_skcipher_des3_key(cipher, key) ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) skcipher_setkey(cipher, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) static int skcipher_aes_setkey(struct crypto_skcipher *cipher,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) const u8 *key, unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (keylen == AES_KEYSIZE_128 || keylen == AES_KEYSIZE_192 ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) keylen == AES_KEYSIZE_256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) return skcipher_setkey(cipher, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) static void common_nonsnoop_unmap(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) struct talitos_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) struct skcipher_request *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) talitos_sg_unmap(dev, edesc, areq->src, areq->dst, areq->cryptlen, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1], DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) if (edesc->dma_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) static void skcipher_done(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) struct talitos_desc *desc, void *context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) struct skcipher_request *areq = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) unsigned int ivsize = crypto_skcipher_ivsize(cipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) struct talitos_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) edesc = container_of(desc, struct talitos_edesc, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) common_nonsnoop_unmap(dev, edesc, areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) memcpy(areq->iv, ctx->iv, ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) kfree(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) areq->base.complete(&areq->base, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) static int common_nonsnoop(struct talitos_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) struct skcipher_request *areq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) void (*callback) (struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) struct talitos_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) void *context, int error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) struct talitos_desc *desc = &edesc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) unsigned int cryptlen = areq->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) unsigned int ivsize = crypto_skcipher_ivsize(cipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) int sg_count, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) bool sync_needed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) bool is_ctr = (desc->hdr & DESC_HDR_SEL0_MASK) == DESC_HDR_SEL0_AESU &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) (desc->hdr & DESC_HDR_MODE0_AESU_MASK) == DESC_HDR_MODE0_AESU_CTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) /* first DWORD empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) /* cipher iv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) to_talitos_ptr(&desc->ptr[1], edesc->iv_dma, ivsize, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) /* cipher key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen, is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) sg_count = edesc->src_nents ?: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) if (is_sec1 && sg_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) sg_copy_to_buffer(areq->src, sg_count, edesc->buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) cryptlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) sg_count = dma_map_sg(dev, areq->src, sg_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) (areq->src == areq->dst) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) DMA_BIDIRECTIONAL : DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) * cipher in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) sg_count = talitos_sg_map_ext(dev, areq->src, cryptlen, edesc, &desc->ptr[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) sg_count, 0, 0, 0, false, is_ctr ? 16 : 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) if (sg_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) sync_needed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) /* cipher out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) if (areq->src != areq->dst) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) sg_count = edesc->dst_nents ? : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (!is_sec1 || sg_count == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) dma_map_sg(dev, areq->dst, sg_count, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) ret = talitos_sg_map(dev, areq->dst, cryptlen, edesc, &desc->ptr[4],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) sg_count, 0, (edesc->src_nents + 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) if (ret > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) sync_needed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) /* iv out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) map_single_talitos_ptr(dev, &desc->ptr[5], ivsize, ctx->iv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) /* last DWORD empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) if (sync_needed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) dma_sync_single_for_device(dev, edesc->dma_link_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) edesc->dma_len, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) if (ret != -EINPROGRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) common_nonsnoop_unmap(dev, edesc, areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) kfree(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) static struct talitos_edesc *skcipher_edesc_alloc(struct skcipher_request *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) areq, bool encrypt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) unsigned int ivsize = crypto_skcipher_ivsize(cipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) return talitos_edesc_alloc(ctx->dev, areq->src, areq->dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) areq->iv, 0, areq->cryptlen, 0, ivsize, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) areq->base.flags, encrypt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) static int skcipher_encrypt(struct skcipher_request *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) struct talitos_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) unsigned int blocksize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) crypto_tfm_alg_blocksize(crypto_skcipher_tfm(cipher));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) if (!areq->cryptlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) if (areq->cryptlen % blocksize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) /* allocate extended descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) edesc = skcipher_edesc_alloc(areq, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) if (IS_ERR(edesc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) return PTR_ERR(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) /* set encrypt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_MODE0_ENCRYPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) return common_nonsnoop(edesc, areq, skcipher_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) static int skcipher_decrypt(struct skcipher_request *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) struct crypto_skcipher *cipher = crypto_skcipher_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) struct talitos_ctx *ctx = crypto_skcipher_ctx(cipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) struct talitos_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) unsigned int blocksize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) crypto_tfm_alg_blocksize(crypto_skcipher_tfm(cipher));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) if (!areq->cryptlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) if (areq->cryptlen % blocksize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) /* allocate extended descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) edesc = skcipher_edesc_alloc(areq, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) if (IS_ERR(edesc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) return PTR_ERR(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) edesc->desc.hdr = ctx->desc_hdr_template | DESC_HDR_DIR_INBOUND;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) return common_nonsnoop(edesc, areq, skcipher_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) static void common_nonsnoop_hash_unmap(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct talitos_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) struct ahash_request *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) struct talitos_desc *desc = &edesc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) struct talitos_desc *desc2 = (struct talitos_desc *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) (edesc->buf + edesc->dma_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) unmap_single_talitos_ptr(dev, &edesc->desc.ptr[5], DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) if (desc->next_desc &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) desc->ptr[5].ptr != desc2->ptr[5].ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) unmap_single_talitos_ptr(dev, &desc2->ptr[5], DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) if (req_ctx->last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) memcpy(areq->result, req_ctx->hw_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) crypto_ahash_digestsize(tfm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) if (req_ctx->psrc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) talitos_sg_unmap(dev, edesc, req_ctx->psrc, NULL, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) /* When using hashctx-in, must unmap it. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) if (from_talitos_ptr_len(&edesc->desc.ptr[1], is_sec1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) unmap_single_talitos_ptr(dev, &edesc->desc.ptr[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) else if (desc->next_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) unmap_single_talitos_ptr(dev, &desc2->ptr[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) if (is_sec1 && req_ctx->nbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) unmap_single_talitos_ptr(dev, &desc->ptr[3],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (edesc->dma_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) dma_unmap_single(dev, edesc->dma_link_tbl, edesc->dma_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) if (edesc->desc.next_desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) dma_unmap_single(dev, be32_to_cpu(edesc->desc.next_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) TALITOS_DESC_SIZE, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) static void ahash_done(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) struct talitos_desc *desc, void *context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) struct ahash_request *areq = context;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) struct talitos_edesc *edesc =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) container_of(desc, struct talitos_edesc, desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (!req_ctx->last && req_ctx->to_hash_later) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) /* Position any partial block for next update/final/finup */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) req_ctx->buf_idx = (req_ctx->buf_idx + 1) & 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) req_ctx->nbuf = req_ctx->to_hash_later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) common_nonsnoop_hash_unmap(dev, edesc, areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) kfree(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) areq->base.complete(&areq->base, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) * SEC1 doesn't like hashing of 0 sized message, so we do the padding
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) * ourself and submit a padded block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) static void talitos_handle_buggy_hash(struct talitos_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) struct talitos_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) struct talitos_ptr *ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) static u8 padded_hash[64] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) 0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) pr_err_once("Bug in SEC1, padding ourself\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) edesc->desc.hdr &= ~DESC_HDR_MODE0_MDEU_PAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) map_single_talitos_ptr(ctx->dev, ptr, sizeof(padded_hash),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) (char *)padded_hash, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) static int common_nonsnoop_hash(struct talitos_edesc *edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) struct ahash_request *areq, unsigned int length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) void (*callback) (struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) struct talitos_desc *desc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) void *context, int error))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) struct talitos_desc *desc = &edesc->desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) bool sync_needed = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) int sg_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) /* first DWORD empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) /* hash context in */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) if (!req_ctx->first || req_ctx->swinit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) map_single_talitos_ptr_nosync(dev, &desc->ptr[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) req_ctx->hw_context_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) req_ctx->hw_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) req_ctx->swinit = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) /* Indicate next op is not the first. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) req_ctx->first = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) /* HMAC key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (ctx->keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) to_talitos_ptr(&desc->ptr[2], ctx->dma_key, ctx->keylen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) if (is_sec1 && req_ctx->nbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) length -= req_ctx->nbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) sg_count = edesc->src_nents ?: 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) if (is_sec1 && sg_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) sg_copy_to_buffer(req_ctx->psrc, sg_count, edesc->buf, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) else if (length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) sg_count = dma_map_sg(dev, req_ctx->psrc, sg_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) * data in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) if (is_sec1 && req_ctx->nbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) map_single_talitos_ptr(dev, &desc->ptr[3], req_ctx->nbuf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) req_ctx->buf[req_ctx->buf_idx],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) sg_count = talitos_sg_map(dev, req_ctx->psrc, length, edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) &desc->ptr[3], sg_count, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) if (sg_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) sync_needed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) /* fifth DWORD empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) /* hash/HMAC out -or- hash context out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) if (req_ctx->last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) map_single_talitos_ptr(dev, &desc->ptr[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) crypto_ahash_digestsize(tfm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) req_ctx->hw_context, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) map_single_talitos_ptr_nosync(dev, &desc->ptr[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) req_ctx->hw_context_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) req_ctx->hw_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) /* last DWORD empty */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) if (is_sec1 && from_talitos_ptr_len(&desc->ptr[3], true) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) talitos_handle_buggy_hash(ctx, edesc, &desc->ptr[3]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) if (is_sec1 && req_ctx->nbuf && length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) struct talitos_desc *desc2 = (struct talitos_desc *)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) (edesc->buf + edesc->dma_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) dma_addr_t next_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) memset(desc2, 0, sizeof(*desc2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) desc2->hdr = desc->hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) desc2->hdr &= ~DESC_HDR_MODE0_MDEU_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) desc2->hdr1 = desc2->hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) desc->hdr &= ~DESC_HDR_MODE0_MDEU_PAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) desc->hdr |= DESC_HDR_MODE0_MDEU_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) desc->hdr &= ~DESC_HDR_DONE_NOTIFY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) if (desc->ptr[1].ptr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) copy_talitos_ptr(&desc2->ptr[1], &desc->ptr[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) map_single_talitos_ptr_nosync(dev, &desc2->ptr[1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) req_ctx->hw_context_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) req_ctx->hw_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) copy_talitos_ptr(&desc2->ptr[2], &desc->ptr[2], is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) sg_count = talitos_sg_map(dev, req_ctx->psrc, length, edesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) &desc2->ptr[3], sg_count, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) if (sg_count > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) sync_needed = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) copy_talitos_ptr(&desc2->ptr[5], &desc->ptr[5], is_sec1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) if (req_ctx->last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) map_single_talitos_ptr_nosync(dev, &desc->ptr[5],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) req_ctx->hw_context_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) req_ctx->hw_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) next_desc = dma_map_single(dev, &desc2->hdr1, TALITOS_DESC_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) desc->next_desc = cpu_to_be32(next_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) if (sync_needed)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) dma_sync_single_for_device(dev, edesc->dma_link_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) edesc->dma_len, DMA_BIDIRECTIONAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) ret = talitos_submit(dev, ctx->ch, desc, callback, areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) if (ret != -EINPROGRESS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) common_nonsnoop_hash_unmap(dev, edesc, areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) kfree(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) static struct talitos_edesc *ahash_edesc_alloc(struct ahash_request *areq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) unsigned int nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) struct talitos_private *priv = dev_get_drvdata(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) if (is_sec1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) nbytes -= req_ctx->nbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) return talitos_edesc_alloc(ctx->dev, req_ctx->psrc, NULL, NULL, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) nbytes, 0, 0, 0, areq->base.flags, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) static int ahash_init(struct ahash_request *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) /* Initialize the context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) req_ctx->buf_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) req_ctx->nbuf = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) req_ctx->first = 1; /* first indicates h/w must init its context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) req_ctx->swinit = 0; /* assume h/w init of context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) req_ctx->hw_context_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) * on h/w without explicit sha224 support, we initialize h/w context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) * manually with sha224 constants, and tell it to run sha256.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) static int ahash_init_sha224_swinit(struct ahash_request *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) req_ctx->hw_context[0] = SHA224_H0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) req_ctx->hw_context[1] = SHA224_H1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) req_ctx->hw_context[2] = SHA224_H2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) req_ctx->hw_context[3] = SHA224_H3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) req_ctx->hw_context[4] = SHA224_H4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) req_ctx->hw_context[5] = SHA224_H5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) req_ctx->hw_context[6] = SHA224_H6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) req_ctx->hw_context[7] = SHA224_H7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) /* init 64-bit count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) req_ctx->hw_context[8] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) req_ctx->hw_context[9] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) ahash_init(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) req_ctx->swinit = 1;/* prevent h/w initting context with sha256 values*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static int ahash_process_req(struct ahash_request *areq, unsigned int nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) struct talitos_edesc *edesc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) unsigned int blocksize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) unsigned int nbytes_to_hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) unsigned int to_hash_later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) unsigned int nsg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) int nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) u8 *ctx_buf = req_ctx->buf[req_ctx->buf_idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) if (!req_ctx->last && (nbytes + req_ctx->nbuf <= blocksize)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) /* Buffer up to one whole block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) nents = sg_nents_for_len(areq->src, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) if (nents < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) dev_err(ctx->dev, "Invalid number of src SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) return nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) sg_copy_to_buffer(areq->src, nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) ctx_buf + req_ctx->nbuf, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) req_ctx->nbuf += nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) /* At least (blocksize + 1) bytes are available to hash */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) nbytes_to_hash = nbytes + req_ctx->nbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) to_hash_later = nbytes_to_hash & (blocksize - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) if (req_ctx->last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) to_hash_later = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) else if (to_hash_later)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) /* There is a partial block. Hash the full block(s) now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) nbytes_to_hash -= to_hash_later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) /* Keep one block buffered */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) nbytes_to_hash -= blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) to_hash_later = blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) /* Chain in any previously buffered data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) if (!is_sec1 && req_ctx->nbuf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) nsg = (req_ctx->nbuf < nbytes_to_hash) ? 2 : 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) sg_init_table(req_ctx->bufsl, nsg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) sg_set_buf(req_ctx->bufsl, ctx_buf, req_ctx->nbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) if (nsg > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) sg_chain(req_ctx->bufsl, 2, areq->src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) req_ctx->psrc = req_ctx->bufsl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) } else if (is_sec1 && req_ctx->nbuf && req_ctx->nbuf < blocksize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036) if (nbytes_to_hash > blocksize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) offset = blocksize - req_ctx->nbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) offset = nbytes_to_hash - req_ctx->nbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) nents = sg_nents_for_len(areq->src, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) if (nents < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) dev_err(ctx->dev, "Invalid number of src SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) return nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) sg_copy_to_buffer(areq->src, nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) ctx_buf + req_ctx->nbuf, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) req_ctx->nbuf += offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) req_ctx->psrc = scatterwalk_ffwd(req_ctx->bufsl, areq->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) req_ctx->psrc = areq->src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) if (to_hash_later) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) nents = sg_nents_for_len(areq->src, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) if (nents < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) dev_err(ctx->dev, "Invalid number of src SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) return nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) sg_pcopy_to_buffer(areq->src, nents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) req_ctx->buf[(req_ctx->buf_idx + 1) & 1],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) to_hash_later,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) nbytes - to_hash_later);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) req_ctx->to_hash_later = to_hash_later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) /* Allocate extended descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) edesc = ahash_edesc_alloc(areq, nbytes_to_hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) if (IS_ERR(edesc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) return PTR_ERR(edesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) edesc->desc.hdr = ctx->desc_hdr_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) /* On last one, request SEC to pad; otherwise continue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) if (req_ctx->last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_PAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_CONT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) /* request SEC to INIT hash. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) if (req_ctx->first && !req_ctx->swinit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) /* When the tfm context has a keylen, it's an HMAC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) * A first or last (ie. not middle) descriptor must request HMAC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) if (ctx->keylen && (req_ctx->first || req_ctx->last))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) edesc->desc.hdr |= DESC_HDR_MODE0_MDEU_HMAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) return common_nonsnoop_hash(edesc, areq, nbytes_to_hash, ahash_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) static int ahash_update(struct ahash_request *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) req_ctx->last = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) return ahash_process_req(areq, areq->nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) static int ahash_final(struct ahash_request *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) req_ctx->last = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) return ahash_process_req(areq, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) static int ahash_finup(struct ahash_request *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) req_ctx->last = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) return ahash_process_req(areq, areq->nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) static int ahash_digest(struct ahash_request *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) struct crypto_ahash *ahash = crypto_ahash_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) ahash->init(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) req_ctx->last = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) return ahash_process_req(areq, areq->nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) static int ahash_export(struct ahash_request *areq, void *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) struct talitos_export_state *export = out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) memcpy(export->hw_context, req_ctx->hw_context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) req_ctx->hw_context_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) memcpy(export->buf, req_ctx->buf[req_ctx->buf_idx], req_ctx->nbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) export->swinit = req_ctx->swinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) export->first = req_ctx->first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) export->last = req_ctx->last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) export->to_hash_later = req_ctx->to_hash_later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) export->nbuf = req_ctx->nbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) static int ahash_import(struct ahash_request *areq, const void *in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) struct talitos_ahash_req_ctx *req_ctx = ahash_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) struct crypto_ahash *tfm = crypto_ahash_reqtfm(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) struct talitos_ctx *ctx = crypto_ahash_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) const struct talitos_export_state *export = in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) dma_addr_t dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) memset(req_ctx, 0, sizeof(*req_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) size = (crypto_ahash_digestsize(tfm) <= SHA256_DIGEST_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) ? TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) : TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) req_ctx->hw_context_size = size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) memcpy(req_ctx->hw_context, export->hw_context, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) memcpy(req_ctx->buf[0], export->buf, export->nbuf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) req_ctx->swinit = export->swinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) req_ctx->first = export->first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) req_ctx->last = export->last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) req_ctx->to_hash_later = export->to_hash_later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) req_ctx->nbuf = export->nbuf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) dma = dma_map_single(dev, req_ctx->hw_context, req_ctx->hw_context_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) dma_unmap_single(dev, dma, req_ctx->hw_context_size, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) static int keyhash(struct crypto_ahash *tfm, const u8 *key, unsigned int keylen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) u8 *hash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) struct scatterlist sg[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) struct ahash_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) struct crypto_wait wait;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) crypto_init_wait(&wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) req = ahash_request_alloc(tfm, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if (!req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) /* Keep tfm keylen == 0 during hash of the long key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) ctx->keylen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) ahash_request_set_callback(req, CRYPTO_TFM_REQ_MAY_BACKLOG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) crypto_req_done, &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) sg_init_one(&sg[0], key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) ahash_request_set_crypt(req, sg, hash, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) ret = crypto_wait_req(crypto_ahash_digest(req), &wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) ahash_request_free(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) static int ahash_setkey(struct crypto_ahash *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) struct talitos_ctx *ctx = crypto_tfm_ctx(crypto_ahash_tfm(tfm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) unsigned int blocksize =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) unsigned int digestsize = crypto_ahash_digestsize(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) unsigned int keysize = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) u8 hash[SHA512_DIGEST_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) if (keylen <= blocksize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) memcpy(ctx->key, key, keysize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) /* Must get the hash of the long key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) ret = keyhash(tfm, key, keylen, hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) keysize = digestsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) memcpy(ctx->key, hash, digestsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) if (ctx->keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) ctx->keylen = keysize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) ctx->dma_key = dma_map_single(dev, ctx->key, keysize, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) struct talitos_alg_template {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) u32 priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) struct skcipher_alg skcipher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) struct ahash_alg hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) struct aead_alg aead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) } alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) __be32 desc_hdr_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) static struct talitos_alg_template driver_algs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) /* AEAD algorithms. These use a single-pass ipsec_esp descriptor */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .cra_name = "authenc(hmac(sha1),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) .cra_driver_name = "authenc-hmac-sha1-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) "cbc-aes-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) DESC_HDR_SEL0_AESU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) DESC_HDR_MODE0_AESU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) DESC_HDR_MODE1_MDEU_SHA1_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .cra_name = "authenc(hmac(sha1),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .cra_driver_name = "authenc-hmac-sha1-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) "cbc-aes-talitos-hsna",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) DESC_HDR_SEL0_AESU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) DESC_HDR_MODE0_AESU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) DESC_HDR_MODE1_MDEU_SHA1_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .cra_name = "authenc(hmac(sha1),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .cra_driver_name = "authenc-hmac-sha1-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) "cbc-3des-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .setkey = aead_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) DESC_HDR_SEL0_DEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) DESC_HDR_MODE0_DEU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325) DESC_HDR_MODE0_DEU_3DES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) DESC_HDR_MODE1_MDEU_SHA1_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .cra_name = "authenc(hmac(sha1),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) .cra_driver_name = "authenc-hmac-sha1-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) "cbc-3des-talitos-hsna",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .maxauthsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .setkey = aead_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) DESC_HDR_SEL0_DEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) DESC_HDR_MODE0_DEU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) DESC_HDR_MODE0_DEU_3DES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) DESC_HDR_MODE1_MDEU_SHA1_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) .cra_name = "authenc(hmac(sha224),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) .cra_driver_name = "authenc-hmac-sha224-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) "cbc-aes-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) DESC_HDR_SEL0_AESU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371) DESC_HDR_MODE0_AESU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) DESC_HDR_MODE1_MDEU_SHA224_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) .cra_name = "authenc(hmac(sha224),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) .cra_driver_name = "authenc-hmac-sha224-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) "cbc-aes-talitos-hsna",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) DESC_HDR_SEL0_AESU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) DESC_HDR_MODE0_AESU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) DESC_HDR_MODE1_MDEU_SHA224_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) .cra_name = "authenc(hmac(sha224),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) .cra_driver_name = "authenc-hmac-sha224-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) "cbc-3des-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) .setkey = aead_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) DESC_HDR_SEL0_DEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) DESC_HDR_MODE0_DEU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) DESC_HDR_MODE0_DEU_3DES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) DESC_HDR_MODE1_MDEU_SHA224_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) .cra_name = "authenc(hmac(sha224),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) .cra_driver_name = "authenc-hmac-sha224-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) "cbc-3des-talitos-hsna",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) .maxauthsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) .setkey = aead_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) DESC_HDR_SEL0_DEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) DESC_HDR_MODE0_DEU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) DESC_HDR_MODE0_DEU_3DES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) DESC_HDR_MODE1_MDEU_SHA224_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451) .cra_name = "authenc(hmac(sha256),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) .cra_driver_name = "authenc-hmac-sha256-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) "cbc-aes-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) DESC_HDR_SEL0_AESU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) DESC_HDR_MODE0_AESU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) DESC_HDR_MODE1_MDEU_SHA256_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) .cra_name = "authenc(hmac(sha256),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) .cra_driver_name = "authenc-hmac-sha256-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) "cbc-aes-talitos-hsna",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) DESC_HDR_SEL0_AESU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) DESC_HDR_MODE0_AESU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) DESC_HDR_MODE1_MDEU_SHA256_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) .cra_name = "authenc(hmac(sha256),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) .cra_driver_name = "authenc-hmac-sha256-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) "cbc-3des-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) .setkey = aead_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) DESC_HDR_SEL0_DEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) DESC_HDR_MODE0_DEU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) DESC_HDR_MODE0_DEU_3DES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) DESC_HDR_MODE1_MDEU_SHA256_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) .cra_name = "authenc(hmac(sha256),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) .cra_driver_name = "authenc-hmac-sha256-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) "cbc-3des-talitos-hsna",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) .maxauthsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) .setkey = aead_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) DESC_HDR_SEL0_DEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) DESC_HDR_MODE0_DEU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) DESC_HDR_MODE0_DEU_3DES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) DESC_HDR_MODE1_MDEU_SHA256_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) .cra_name = "authenc(hmac(sha384),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) .cra_driver_name = "authenc-hmac-sha384-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) "cbc-aes-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) DESC_HDR_SEL0_AESU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) DESC_HDR_MODE0_AESU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) DESC_HDR_SEL1_MDEUB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559) DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) .cra_name = "authenc(hmac(sha384),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) .cra_driver_name = "authenc-hmac-sha384-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) "cbc-3des-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) .maxauthsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) .setkey = aead_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) DESC_HDR_SEL0_DEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) DESC_HDR_MODE0_DEU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) DESC_HDR_MODE0_DEU_3DES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) DESC_HDR_SEL1_MDEUB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) DESC_HDR_MODE1_MDEUB_SHA384_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) .cra_name = "authenc(hmac(sha512),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) .cra_driver_name = "authenc-hmac-sha512-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) "cbc-aes-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) DESC_HDR_SEL0_AESU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) DESC_HDR_MODE0_AESU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) DESC_HDR_SEL1_MDEUB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) .cra_name = "authenc(hmac(sha512),"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) "cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) .cra_driver_name = "authenc-hmac-sha512-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) "cbc-3des-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) .maxauthsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) .setkey = aead_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) DESC_HDR_SEL0_DEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) DESC_HDR_MODE0_DEU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624) DESC_HDR_MODE0_DEU_3DES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) DESC_HDR_SEL1_MDEUB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) DESC_HDR_MODE1_MDEUB_SHA512_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) .cra_name = "authenc(hmac(md5),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) .cra_driver_name = "authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) "cbc-aes-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) DESC_HDR_SEL0_AESU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) DESC_HDR_MODE0_AESU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) DESC_HDR_MODE1_MDEU_MD5_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) .cra_name = "authenc(hmac(md5),cbc(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) .cra_driver_name = "authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) "cbc-aes-talitos-hsna",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) .cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) DESC_HDR_SEL0_AESU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667) DESC_HDR_MODE0_AESU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) DESC_HDR_MODE1_MDEU_MD5_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677) .cra_driver_name = "authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) "cbc-3des-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) .setkey = aead_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) .desc_hdr_template = DESC_HDR_TYPE_IPSEC_ESP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) DESC_HDR_SEL0_DEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) DESC_HDR_MODE0_DEU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) DESC_HDR_MODE0_DEU_3DES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) DESC_HDR_MODE1_MDEU_MD5_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) { .type = CRYPTO_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) .priority = TALITOS_CRA_PRIORITY_AEAD_HSNA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) .alg.aead = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) .cra_name = "authenc(hmac(md5),cbc(des3_ede))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701) .cra_driver_name = "authenc-hmac-md5-"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) "cbc-3des-talitos-hsna",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) .cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) .maxauthsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) .setkey = aead_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) .desc_hdr_template = DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) DESC_HDR_SEL0_DEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) DESC_HDR_MODE0_DEU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) DESC_HDR_MODE0_DEU_3DES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) DESC_HDR_SEL1_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) DESC_HDR_MODE1_MDEU_INIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) DESC_HDR_MODE1_MDEU_PAD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) DESC_HDR_MODE1_MDEU_MD5_HMAC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) /* SKCIPHER algorithms. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) { .type = CRYPTO_ALG_TYPE_SKCIPHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) .alg.skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) .base.cra_name = "ecb(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724) .base.cra_driver_name = "ecb-aes-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) .base.cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726) .base.cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) .setkey = skcipher_aes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) DESC_HDR_SEL0_AESU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) { .type = CRYPTO_ALG_TYPE_SKCIPHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) .alg.skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) .base.cra_name = "cbc(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) .base.cra_driver_name = "cbc-aes-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) .base.cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) .base.cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745) .setkey = skcipher_aes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) DESC_HDR_SEL0_AESU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) DESC_HDR_MODE0_AESU_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) { .type = CRYPTO_ALG_TYPE_SKCIPHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) .alg.skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) .base.cra_name = "ctr(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754) .base.cra_driver_name = "ctr-aes-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) .base.cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) .base.cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) .setkey = skcipher_aes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763) .desc_hdr_template = DESC_HDR_TYPE_AESU_CTR_NONSNOOP |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) DESC_HDR_SEL0_AESU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) DESC_HDR_MODE0_AESU_CTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) { .type = CRYPTO_ALG_TYPE_SKCIPHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) .alg.skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) .base.cra_name = "ctr(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770) .base.cra_driver_name = "ctr-aes-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) .base.cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) .base.cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) .setkey = skcipher_aes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) DESC_HDR_SEL0_AESU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) DESC_HDR_MODE0_AESU_CTR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) { .type = CRYPTO_ALG_TYPE_SKCIPHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) .alg.skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) .base.cra_name = "ecb(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) .base.cra_driver_name = "ecb-des-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) .base.cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792) .setkey = skcipher_des_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) DESC_HDR_SEL0_DEU,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) { .type = CRYPTO_ALG_TYPE_SKCIPHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) .alg.skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799) .base.cra_name = "cbc(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) .base.cra_driver_name = "cbc-des-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802) .base.cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) .setkey = skcipher_des_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) DESC_HDR_SEL0_DEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) DESC_HDR_MODE0_DEU_CBC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) { .type = CRYPTO_ALG_TYPE_SKCIPHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) .alg.skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815) .base.cra_name = "ecb(des3_ede)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) .base.cra_driver_name = "ecb-3des-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818) .base.cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) .min_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) .max_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) .setkey = skcipher_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) DESC_HDR_SEL0_DEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826) DESC_HDR_MODE0_DEU_3DES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828) { .type = CRYPTO_ALG_TYPE_SKCIPHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) .alg.skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830) .base.cra_name = "cbc(des3_ede)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) .base.cra_driver_name = "cbc-3des-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) .base.cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) .min_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) .max_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) .setkey = skcipher_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841) DESC_HDR_SEL0_DEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) DESC_HDR_MODE0_DEU_CBC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843) DESC_HDR_MODE0_DEU_3DES,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) /* AHASH algorithms. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) { .type = CRYPTO_ALG_TYPE_AHASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) .alg.hash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) .halg.digestsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849) .halg.statesize = sizeof(struct talitos_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) .cra_name = "md5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) .cra_driver_name = "md5-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) DESC_HDR_SEL0_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) DESC_HDR_MODE0_MDEU_MD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862) { .type = CRYPTO_ALG_TYPE_AHASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) .alg.hash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) .halg.digestsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) .halg.statesize = sizeof(struct talitos_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) .cra_name = "sha1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868) .cra_driver_name = "sha1-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) .cra_blocksize = SHA1_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) DESC_HDR_SEL0_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) DESC_HDR_MODE0_MDEU_SHA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878) { .type = CRYPTO_ALG_TYPE_AHASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) .alg.hash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) .halg.digestsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) .halg.statesize = sizeof(struct talitos_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) .cra_name = "sha224",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) .cra_driver_name = "sha224-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) .cra_blocksize = SHA224_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) DESC_HDR_SEL0_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) DESC_HDR_MODE0_MDEU_SHA224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) { .type = CRYPTO_ALG_TYPE_AHASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) .alg.hash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) .halg.digestsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897) .halg.statesize = sizeof(struct talitos_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) .cra_name = "sha256",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900) .cra_driver_name = "sha256-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) .cra_blocksize = SHA256_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907) DESC_HDR_SEL0_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) DESC_HDR_MODE0_MDEU_SHA256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910) { .type = CRYPTO_ALG_TYPE_AHASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) .alg.hash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) .halg.digestsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) .halg.statesize = sizeof(struct talitos_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) .cra_name = "sha384",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) .cra_driver_name = "sha384-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) .cra_blocksize = SHA384_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923) DESC_HDR_SEL0_MDEUB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) DESC_HDR_MODE0_MDEUB_SHA384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) { .type = CRYPTO_ALG_TYPE_AHASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) .alg.hash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) .halg.digestsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) .halg.statesize = sizeof(struct talitos_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931) .cra_name = "sha512",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) .cra_driver_name = "sha512-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) .cra_blocksize = SHA512_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) DESC_HDR_SEL0_MDEUB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) DESC_HDR_MODE0_MDEUB_SHA512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942) { .type = CRYPTO_ALG_TYPE_AHASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) .alg.hash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944) .halg.digestsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) .halg.statesize = sizeof(struct talitos_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) .cra_name = "hmac(md5)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) .cra_driver_name = "hmac-md5-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) .cra_blocksize = MD5_HMAC_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) DESC_HDR_SEL0_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) DESC_HDR_MODE0_MDEU_MD5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) { .type = CRYPTO_ALG_TYPE_AHASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) .alg.hash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) .halg.digestsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961) .halg.statesize = sizeof(struct talitos_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) .cra_name = "hmac(sha1)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964) .cra_driver_name = "hmac-sha1-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) .cra_blocksize = SHA1_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) DESC_HDR_SEL0_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) DESC_HDR_MODE0_MDEU_SHA1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) { .type = CRYPTO_ALG_TYPE_AHASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) .alg.hash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) .halg.digestsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) .halg.statesize = sizeof(struct talitos_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979) .cra_name = "hmac(sha224)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) .cra_driver_name = "hmac-sha224-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) .cra_blocksize = SHA224_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) DESC_HDR_SEL0_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988) DESC_HDR_MODE0_MDEU_SHA224,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) { .type = CRYPTO_ALG_TYPE_AHASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991) .alg.hash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) .halg.digestsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) .halg.statesize = sizeof(struct talitos_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) .cra_name = "hmac(sha256)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) .cra_driver_name = "hmac-sha256-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997) .cra_blocksize = SHA256_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) DESC_HDR_SEL0_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) DESC_HDR_MODE0_MDEU_SHA256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) { .type = CRYPTO_ALG_TYPE_AHASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) .alg.hash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) .halg.digestsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) .halg.statesize = sizeof(struct talitos_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) .cra_name = "hmac(sha384)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) .cra_driver_name = "hmac-sha384-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013) .cra_blocksize = SHA384_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) DESC_HDR_SEL0_MDEUB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) DESC_HDR_MODE0_MDEUB_SHA384,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) { .type = CRYPTO_ALG_TYPE_AHASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) .alg.hash = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) .halg.digestsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) .halg.statesize = sizeof(struct talitos_export_state),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) .cra_name = "hmac(sha512)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) .cra_driver_name = "hmac-sha512-talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) .cra_blocksize = SHA512_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) CRYPTO_ALG_ALLOCATES_MEMORY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) .desc_hdr_template = DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) DESC_HDR_SEL0_MDEUB |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036) DESC_HDR_MODE0_MDEUB_SHA512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) struct talitos_crypto_alg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) struct talitos_alg_template algt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) static int talitos_init_common(struct talitos_ctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) struct talitos_crypto_alg *talitos_alg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) struct talitos_private *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) /* update context with ptr to dev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) ctx->dev = talitos_alg->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054) /* assign SEC channel to tfm in round-robin fashion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) priv = dev_get_drvdata(ctx->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) ctx->ch = atomic_inc_return(&priv->last_chan) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) (priv->num_channels - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) /* copy descriptor header template value */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060) ctx->desc_hdr_template = talitos_alg->algt.desc_hdr_template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) /* select done notification */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) ctx->desc_hdr_template |= DESC_HDR_DONE_NOTIFY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) static int talitos_cra_init_aead(struct crypto_aead *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) struct aead_alg *alg = crypto_aead_alg(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071) struct talitos_crypto_alg *talitos_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) struct talitos_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) talitos_alg = container_of(alg, struct talitos_crypto_alg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) algt.alg.aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077) return talitos_init_common(ctx, talitos_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080) static int talitos_cra_init_skcipher(struct crypto_skcipher *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082) struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) struct talitos_crypto_alg *talitos_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) struct talitos_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086) talitos_alg = container_of(alg, struct talitos_crypto_alg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) algt.alg.skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) return talitos_init_common(ctx, talitos_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) static int talitos_cra_init_ahash(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) struct crypto_alg *alg = tfm->__crt_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) struct talitos_crypto_alg *talitos_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) talitos_alg = container_of(__crypto_ahash_alg(alg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099) struct talitos_crypto_alg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) algt.alg.hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102) ctx->keylen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) sizeof(struct talitos_ahash_req_ctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) return talitos_init_common(ctx, talitos_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) static void talitos_cra_exit(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) struct talitos_ctx *ctx = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) struct device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114) if (ctx->keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) dma_unmap_single(dev, ctx->dma_key, ctx->keylen, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) * given the alg's descriptor header template, determine whether descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) * type and primary/secondary execution units required match the hw
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) * capabilities description provided in the device tree node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) static int hw_supports(struct device *dev, __be32 desc_hdr_template)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) ret = (1 << DESC_TYPE(desc_hdr_template) & priv->desc_types) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) (1 << PRIMARY_EU(desc_hdr_template) & priv->exec_units);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131) if (SECONDARY_EU(desc_hdr_template))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) ret = ret && (1 << SECONDARY_EU(desc_hdr_template)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) & priv->exec_units);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) static int talitos_remove(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) struct device *dev = &ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) struct talitos_crypto_alg *t_alg, *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) list_for_each_entry_safe(t_alg, n, &priv->alg_list, entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146) switch (t_alg->algt.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) case CRYPTO_ALG_TYPE_SKCIPHER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148) crypto_unregister_skcipher(&t_alg->algt.alg.skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) case CRYPTO_ALG_TYPE_AEAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) crypto_unregister_aead(&t_alg->algt.alg.aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) case CRYPTO_ALG_TYPE_AHASH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) crypto_unregister_ahash(&t_alg->algt.alg.hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157) list_del(&t_alg->entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) if (hw_supports(dev, DESC_HDR_SEL0_RNG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161) talitos_unregister_rng(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) for (i = 0; i < 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) if (priv->irq[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) free_irq(priv->irq[i], dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) irq_dispose_mapping(priv->irq[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) tasklet_kill(&priv->done_task[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) if (priv->irq[1])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) tasklet_kill(&priv->done_task[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) static struct talitos_crypto_alg *talitos_alg_alloc(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177) struct talitos_alg_template
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) *template)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) struct talitos_crypto_alg *t_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) struct crypto_alg *alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) t_alg = devm_kzalloc(dev, sizeof(struct talitos_crypto_alg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) if (!t_alg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) t_alg->algt = *template;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) switch (t_alg->algt.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) case CRYPTO_ALG_TYPE_SKCIPHER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) alg = &t_alg->algt.alg.skcipher.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) alg->cra_exit = talitos_cra_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) t_alg->algt.alg.skcipher.init = talitos_cra_init_skcipher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) t_alg->algt.alg.skcipher.setkey =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) t_alg->algt.alg.skcipher.setkey ?: skcipher_setkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) t_alg->algt.alg.skcipher.encrypt = skcipher_encrypt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) t_alg->algt.alg.skcipher.decrypt = skcipher_decrypt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) if (!strcmp(alg->cra_name, "ctr(aes)") && !has_ftr_sec1(priv) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) DESC_TYPE(t_alg->algt.desc_hdr_template) !=
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) DESC_TYPE(DESC_HDR_TYPE_AESU_CTR_NONSNOOP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) devm_kfree(dev, t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204) return ERR_PTR(-ENOTSUPP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) case CRYPTO_ALG_TYPE_AEAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208) alg = &t_alg->algt.alg.aead.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) alg->cra_exit = talitos_cra_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) t_alg->algt.alg.aead.init = talitos_cra_init_aead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) t_alg->algt.alg.aead.setkey = t_alg->algt.alg.aead.setkey ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) aead_setkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213) t_alg->algt.alg.aead.encrypt = aead_encrypt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) t_alg->algt.alg.aead.decrypt = aead_decrypt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) !strncmp(alg->cra_name, "authenc(hmac(sha224)", 20)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) devm_kfree(dev, t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) return ERR_PTR(-ENOTSUPP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) case CRYPTO_ALG_TYPE_AHASH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) alg = &t_alg->algt.alg.hash.halg.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) alg->cra_init = talitos_cra_init_ahash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224) alg->cra_exit = talitos_cra_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) t_alg->algt.alg.hash.init = ahash_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) t_alg->algt.alg.hash.update = ahash_update;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) t_alg->algt.alg.hash.final = ahash_final;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228) t_alg->algt.alg.hash.finup = ahash_finup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) t_alg->algt.alg.hash.digest = ahash_digest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) if (!strncmp(alg->cra_name, "hmac", 4))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231) t_alg->algt.alg.hash.setkey = ahash_setkey;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) t_alg->algt.alg.hash.import = ahash_import;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) t_alg->algt.alg.hash.export = ahash_export;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235) if (!(priv->features & TALITOS_FTR_HMAC_OK) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) !strncmp(alg->cra_name, "hmac", 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) devm_kfree(dev, t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238) return ERR_PTR(-ENOTSUPP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) if (!(priv->features & TALITOS_FTR_SHA224_HWINIT) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241) (!strcmp(alg->cra_name, "sha224") ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) !strcmp(alg->cra_name, "hmac(sha224)"))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) t_alg->algt.alg.hash.init = ahash_init_sha224_swinit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) t_alg->algt.desc_hdr_template =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246) DESC_HDR_SEL0_MDEUA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) DESC_HDR_MODE0_MDEU_SHA256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) dev_err(dev, "unknown algorithm type %d\n", t_alg->algt.type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) devm_kfree(dev, t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) return ERR_PTR(-EINVAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) alg->cra_module = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) if (t_alg->algt.priority)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) alg->cra_priority = t_alg->algt.priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260) alg->cra_priority = TALITOS_CRA_PRIORITY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) if (has_ftr_sec1(priv))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) alg->cra_alignmask = 3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) alg->cra_alignmask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) alg->cra_ctxsize = sizeof(struct talitos_ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) alg->cra_flags |= CRYPTO_ALG_KERN_DRIVER_ONLY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) t_alg->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) return t_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) static int talitos_probe_irq(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275) struct device *dev = &ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) struct device_node *np = ofdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) struct talitos_private *priv = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) bool is_sec1 = has_ftr_sec1(priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) priv->irq[0] = irq_of_parse_and_map(np, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) if (!priv->irq[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) dev_err(dev, "failed to map irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286) if (is_sec1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) err = request_irq(priv->irq[0], talitos1_interrupt_4ch, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) dev_driver_string(dev), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) goto primary_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) priv->irq[1] = irq_of_parse_and_map(np, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) /* get the primary irq line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295) if (!priv->irq[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) err = request_irq(priv->irq[0], talitos2_interrupt_4ch, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) dev_driver_string(dev), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) goto primary_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) err = request_irq(priv->irq[0], talitos2_interrupt_ch0_2, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302) dev_driver_string(dev), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) goto primary_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) /* get the secondary irq line */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) err = request_irq(priv->irq[1], talitos2_interrupt_ch1_3, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) dev_driver_string(dev), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) dev_err(dev, "failed to request secondary irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311) irq_dispose_mapping(priv->irq[1]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) priv->irq[1] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317) primary_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) dev_err(dev, "failed to request primary irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) irq_dispose_mapping(priv->irq[0]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) priv->irq[0] = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) static int talitos_probe(struct platform_device *ofdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329) struct device *dev = &ofdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) struct device_node *np = ofdev->dev.of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) struct talitos_private *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) int stride;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336) priv = devm_kzalloc(dev, sizeof(struct talitos_private), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) if (!priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) INIT_LIST_HEAD(&priv->alg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) dev_set_drvdata(dev, priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344) priv->ofdev = ofdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) spin_lock_init(&priv->reg_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) res = platform_get_resource(ofdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) priv->reg = devm_ioremap(dev, res->start, resource_size(res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) if (!priv->reg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353) dev_err(dev, "failed to of_iomap\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) /* get SEC version capabilities from device tree */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) of_property_read_u32(np, "fsl,num-channels", &priv->num_channels);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360) of_property_read_u32(np, "fsl,channel-fifo-len", &priv->chfifo_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) of_property_read_u32(np, "fsl,exec-units-mask", &priv->exec_units);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) of_property_read_u32(np, "fsl,descriptor-types-mask",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) &priv->desc_types);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) if (!is_power_of_2(priv->num_channels) || !priv->chfifo_len ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) !priv->exec_units || !priv->desc_types) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) dev_err(dev, "invalid property data in device tree node\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) if (of_device_is_compatible(np, "fsl,sec3.0"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) priv->features |= TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375) if (of_device_is_compatible(np, "fsl,sec2.1"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) priv->features |= TALITOS_FTR_HW_AUTH_CHECK |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) TALITOS_FTR_SHA224_HWINIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378) TALITOS_FTR_HMAC_OK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) if (of_device_is_compatible(np, "fsl,sec1.0"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) priv->features |= TALITOS_FTR_SEC1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) if (of_device_is_compatible(np, "fsl,sec1.2")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) priv->reg_deu = priv->reg + TALITOS12_DEU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) priv->reg_aesu = priv->reg + TALITOS12_AESU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) priv->reg_mdeu = priv->reg + TALITOS12_MDEU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387) stride = TALITOS1_CH_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) } else if (of_device_is_compatible(np, "fsl,sec1.0")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) priv->reg_deu = priv->reg + TALITOS10_DEU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) priv->reg_aesu = priv->reg + TALITOS10_AESU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) priv->reg_mdeu = priv->reg + TALITOS10_MDEU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) priv->reg_afeu = priv->reg + TALITOS10_AFEU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393) priv->reg_rngu = priv->reg + TALITOS10_RNGU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) priv->reg_pkeu = priv->reg + TALITOS10_PKEU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) stride = TALITOS1_CH_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397) priv->reg_deu = priv->reg + TALITOS2_DEU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) priv->reg_aesu = priv->reg + TALITOS2_AESU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) priv->reg_mdeu = priv->reg + TALITOS2_MDEU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) priv->reg_afeu = priv->reg + TALITOS2_AFEU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) priv->reg_rngu = priv->reg + TALITOS2_RNGU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) priv->reg_pkeu = priv->reg + TALITOS2_PKEU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403) priv->reg_keu = priv->reg + TALITOS2_KEU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) priv->reg_crcu = priv->reg + TALITOS2_CRCU;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) stride = TALITOS2_CH_STRIDE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408) err = talitos_probe_irq(ofdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) if (has_ftr_sec1(priv)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) if (priv->num_channels == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414) tasklet_init(&priv->done_task[0], talitos1_done_ch0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) (unsigned long)dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) tasklet_init(&priv->done_task[0], talitos1_done_4ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) (unsigned long)dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) if (priv->irq[1]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421) tasklet_init(&priv->done_task[0], talitos2_done_ch0_2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) (unsigned long)dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) tasklet_init(&priv->done_task[1], talitos2_done_ch1_3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424) (unsigned long)dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) } else if (priv->num_channels == 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) tasklet_init(&priv->done_task[0], talitos2_done_ch0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) (unsigned long)dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429) tasklet_init(&priv->done_task[0], talitos2_done_4ch,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) (unsigned long)dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) priv->chan = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435) priv->num_channels,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) sizeof(struct talitos_channel),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) if (!priv->chan) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) dev_err(dev, "failed to allocate channel management space\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) priv->fifo_len = roundup_pow_of_two(priv->chfifo_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) for (i = 0; i < priv->num_channels; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) priv->chan[i].reg = priv->reg + stride * (i + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) if (!priv->irq[1] || !(i & 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449) priv->chan[i].reg += TALITOS_CH_BASE_OFFSET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) spin_lock_init(&priv->chan[i].head_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452) spin_lock_init(&priv->chan[i].tail_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) priv->chan[i].fifo = devm_kcalloc(dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) priv->fifo_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456) sizeof(struct talitos_request),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) if (!priv->chan[i].fifo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) dev_err(dev, "failed to allocate request fifo %d\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) atomic_set(&priv->chan[i].submit_count,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) -(priv->chfifo_len - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) dma_set_mask(dev, DMA_BIT_MASK(36));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) /* reset and initialize the h/w */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) err = init_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473) dev_err(dev, "failed to initialize device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) /* register the RNG, if available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) if (hw_supports(dev, DESC_HDR_SEL0_RNG)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479) err = talitos_register_rng(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) dev_err(dev, "failed to register hwrng: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484) dev_info(dev, "hwrng\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) /* register crypto algorithms the device supports */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) for (i = 0; i < ARRAY_SIZE(driver_algs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) if (hw_supports(dev, driver_algs[i].desc_hdr_template)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) struct talitos_crypto_alg *t_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) struct crypto_alg *alg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) t_alg = talitos_alg_alloc(dev, &driver_algs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) if (IS_ERR(t_alg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) err = PTR_ERR(t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) if (err == -ENOTSUPP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) switch (t_alg->algt.type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) case CRYPTO_ALG_TYPE_SKCIPHER:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) err = crypto_register_skcipher(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504) &t_alg->algt.alg.skcipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) alg = &t_alg->algt.alg.skcipher.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) case CRYPTO_ALG_TYPE_AEAD:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) err = crypto_register_aead(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) &t_alg->algt.alg.aead);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) alg = &t_alg->algt.alg.aead.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514) case CRYPTO_ALG_TYPE_AHASH:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) err = crypto_register_ahash(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) &t_alg->algt.alg.hash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) alg = &t_alg->algt.alg.hash.halg.base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) dev_err(dev, "%s alg registration failed\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) alg->cra_driver_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) devm_kfree(dev, t_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525) list_add_tail(&t_alg->entry, &priv->alg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) if (!list_empty(&priv->alg_list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) dev_info(dev, "%s algorithms registered in /proc/crypto\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) (char *)of_get_property(np, "compatible", NULL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) talitos_remove(ofdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) static const struct of_device_id talitos_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) #ifdef CONFIG_CRYPTO_DEV_TALITOS1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) .compatible = "fsl,sec1.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) #ifdef CONFIG_CRYPTO_DEV_TALITOS2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) .compatible = "fsl,sec2.0",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553) MODULE_DEVICE_TABLE(of, talitos_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) static struct platform_driver talitos_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) .name = "talitos",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) .of_match_table = talitos_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) .probe = talitos_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) .remove = talitos_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) module_platform_driver(talitos_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) MODULE_AUTHOR("Kim Phillips <kim.phillips@freescale.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) MODULE_DESCRIPTION("Freescale integrated security engine (SEC) driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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