^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) STMicroelectronics SA 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Fabien Dessenne <fabien.dessenne@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/reset.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <crypto/aes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <crypto/internal/des.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <crypto/engine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <crypto/scatterwalk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <crypto/internal/aead.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <crypto/internal/skcipher.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRIVER_NAME "stm32-cryp"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Bit [0] encrypt / decrypt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define FLG_ENCRYPT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) /* Bit [8..1] algo & operation mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define FLG_AES BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define FLG_DES BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define FLG_TDES BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define FLG_ECB BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define FLG_CBC BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define FLG_CTR BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define FLG_GCM BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define FLG_CCM BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) /* Mode mask = bits [15..0] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define FLG_MODE_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) /* Bit [31..16] status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CRYP_CR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CRYP_SR 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CRYP_DIN 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CRYP_DOUT 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CRYP_DMACR 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CRYP_IMSCR 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CRYP_RISR 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CRYP_MISR 0x0000001C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CRYP_K0LR 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CRYP_K0RR 0x00000024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CRYP_K1LR 0x00000028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CRYP_K1RR 0x0000002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CRYP_K2LR 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CRYP_K2RR 0x00000034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CRYP_K3LR 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CRYP_K3RR 0x0000003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CRYP_IV0LR 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CRYP_IV0RR 0x00000044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CRYP_IV1LR 0x00000048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CRYP_IV1RR 0x0000004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CRYP_CSGCMCCM0R 0x00000050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CRYP_CSGCM0R 0x00000070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* Registers values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CR_DEC_NOT_ENC 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CR_TDES_ECB 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CR_TDES_CBC 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CR_DES_ECB 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CR_DES_CBC 0x00000018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CR_AES_ECB 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CR_AES_CBC 0x00000028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CR_AES_CTR 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CR_AES_KP 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CR_AES_GCM 0x00080000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CR_AES_CCM 0x00080008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CR_AES_UNKNOWN 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CR_ALGO_MASK 0x00080038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CR_DATA32 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CR_DATA16 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CR_DATA8 0x00000080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CR_DATA1 0x000000C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CR_KEY128 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CR_KEY192 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CR_KEY256 0x00000200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CR_FFLUSH 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CR_CRYPEN 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CR_PH_INIT 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CR_PH_HEADER 0x00010000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CR_PH_PAYLOAD 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CR_PH_FINAL 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CR_PH_MASK 0x00030000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CR_NBPBL_SHIFT 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SR_BUSY 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SR_OFNE 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMSCR_IN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMSCR_OUT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define MISR_IN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MISR_OUT BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Misc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define AES_BLOCK_32 (AES_BLOCK_SIZE / sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GCM_CTR_INIT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CRYP_AUTOSUSPEND_DELAY 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) struct stm32_cryp_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) bool swap_final;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) bool padding_wa;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) struct stm32_cryp_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) struct crypto_engine_ctx enginectx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) struct stm32_cryp *cryp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) int keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) __be32 key[AES_KEYSIZE_256 / sizeof(u32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) struct stm32_cryp_reqctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) unsigned long mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) struct stm32_cryp {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 irq_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) const struct stm32_cryp_caps *caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) struct stm32_cryp_ctx *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct crypto_engine *engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) struct skcipher_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) struct aead_request *areq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) size_t authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) size_t hw_blocksize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) size_t payload_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) size_t header_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) size_t payload_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) struct scatterlist *out_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct scatter_walk in_walk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct scatter_walk out_walk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) __be32 last_ctr[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) u32 gcm_ctr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct stm32_cryp_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct list_head dev_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) spinlock_t lock; /* protect dev_list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static struct stm32_cryp_list cryp_list = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) .dev_list = LIST_HEAD_INIT(cryp_list.dev_list),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) .lock = __SPIN_LOCK_UNLOCKED(cryp_list.lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) static inline bool is_aes(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) return cryp->flags & FLG_AES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static inline bool is_des(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) return cryp->flags & FLG_DES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) static inline bool is_tdes(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) return cryp->flags & FLG_TDES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) static inline bool is_ecb(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) return cryp->flags & FLG_ECB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) static inline bool is_cbc(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) return cryp->flags & FLG_CBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) static inline bool is_ctr(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) return cryp->flags & FLG_CTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) static inline bool is_gcm(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) return cryp->flags & FLG_GCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) static inline bool is_ccm(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) return cryp->flags & FLG_CCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) static inline bool is_encrypt(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) return cryp->flags & FLG_ENCRYPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) static inline bool is_decrypt(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return !is_encrypt(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static inline u32 stm32_cryp_read(struct stm32_cryp *cryp, u32 ofst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return readl_relaxed(cryp->regs + ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static inline void stm32_cryp_write(struct stm32_cryp *cryp, u32 ofst, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) writel_relaxed(val, cryp->regs + ofst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) static inline int stm32_cryp_wait_busy(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) return readl_relaxed_poll_timeout(cryp->regs + CRYP_SR, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) !(status & SR_BUSY), 10, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) static inline int stm32_cryp_wait_enable(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return readl_relaxed_poll_timeout(cryp->regs + CRYP_CR, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) !(status & CR_CRYPEN), 10, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) static inline int stm32_cryp_wait_output(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) return readl_relaxed_poll_timeout(cryp->regs + CRYP_SR, status,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) status & SR_OFNE, 10, 100000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) static int stm32_cryp_read_auth_tag(struct stm32_cryp *cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static void stm32_cryp_finish_req(struct stm32_cryp *cryp, int err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static struct stm32_cryp *stm32_cryp_find_dev(struct stm32_cryp_ctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) struct stm32_cryp *tmp, *cryp = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) spin_lock_bh(&cryp_list.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) if (!ctx->cryp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) list_for_each_entry(tmp, &cryp_list.dev_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) cryp = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) ctx->cryp = cryp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) cryp = ctx->cryp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) spin_unlock_bh(&cryp_list.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) return cryp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static void stm32_cryp_hw_write_iv(struct stm32_cryp *cryp, __be32 *iv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (!iv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) stm32_cryp_write(cryp, CRYP_IV0LR, be32_to_cpu(*iv++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) stm32_cryp_write(cryp, CRYP_IV0RR, be32_to_cpu(*iv++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) if (is_aes(cryp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) stm32_cryp_write(cryp, CRYP_IV1LR, be32_to_cpu(*iv++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) stm32_cryp_write(cryp, CRYP_IV1RR, be32_to_cpu(*iv++));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) static void stm32_cryp_get_iv(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) struct skcipher_request *req = cryp->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) __be32 *tmp = (void *)req->iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) if (!tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) *tmp++ = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV0LR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) *tmp++ = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV0RR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) if (is_aes(cryp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) *tmp++ = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV1LR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) *tmp++ = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV1RR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) static void stm32_cryp_hw_write_key(struct stm32_cryp *c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) int r_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) if (is_des(c)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) stm32_cryp_write(c, CRYP_K1LR, be32_to_cpu(c->ctx->key[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) stm32_cryp_write(c, CRYP_K1RR, be32_to_cpu(c->ctx->key[1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) r_id = CRYP_K3RR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) for (i = c->ctx->keylen / sizeof(u32); i > 0; i--, r_id -= 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) stm32_cryp_write(c, r_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) be32_to_cpu(c->ctx->key[i - 1]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static u32 stm32_cryp_get_hw_mode(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (is_aes(cryp) && is_ecb(cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return CR_AES_ECB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) if (is_aes(cryp) && is_cbc(cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) return CR_AES_CBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (is_aes(cryp) && is_ctr(cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) return CR_AES_CTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) if (is_aes(cryp) && is_gcm(cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return CR_AES_GCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (is_aes(cryp) && is_ccm(cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) return CR_AES_CCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) if (is_des(cryp) && is_ecb(cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) return CR_DES_ECB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (is_des(cryp) && is_cbc(cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) return CR_DES_CBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) if (is_tdes(cryp) && is_ecb(cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) return CR_TDES_ECB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) if (is_tdes(cryp) && is_cbc(cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) return CR_TDES_CBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dev_err(cryp->dev, "Unknown mode\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) return CR_AES_UNKNOWN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) static unsigned int stm32_cryp_get_input_text_len(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return is_encrypt(cryp) ? cryp->areq->cryptlen :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) cryp->areq->cryptlen - cryp->authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) static int stm32_cryp_gcm_init(struct stm32_cryp *cryp, u32 cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) __be32 iv[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* Phase 1 : init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) memcpy(iv, cryp->areq->iv, 12);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) iv[3] = cpu_to_be32(GCM_CTR_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) cryp->gcm_ctr = GCM_CTR_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) stm32_cryp_hw_write_iv(cryp, iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) stm32_cryp_write(cryp, CRYP_CR, cfg | CR_PH_INIT | CR_CRYPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* Wait for end of processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) ret = stm32_cryp_wait_enable(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_err(cryp->dev, "Timeout (gcm init)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* Prepare next phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) if (cryp->areq->assoclen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) cfg |= CR_PH_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) } else if (stm32_cryp_get_input_text_len(cryp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) cfg |= CR_PH_PAYLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) static void stm32_crypt_gcmccm_end_header(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) /* Check if whole header written */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) if (!cryp->header_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) /* Wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) err = stm32_cryp_wait_busy(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) dev_err(cryp->dev, "Timeout (gcm/ccm header)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) stm32_cryp_write(cryp, CRYP_IMSCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) stm32_cryp_finish_req(cryp, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (stm32_cryp_get_input_text_len(cryp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) /* Phase 3 : payload */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) cfg = stm32_cryp_read(cryp, CRYP_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) cfg &= ~CR_CRYPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) cfg &= ~CR_PH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) cfg |= CR_PH_PAYLOAD | CR_CRYPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * Phase 4 : tag.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * Nothing to read, nothing to write, caller have to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * end request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) static void stm32_cryp_write_ccm_first_header(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) size_t written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) size_t len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) u32 alen = cryp->areq->assoclen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) u32 block[AES_BLOCK_32] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) u8 *b8 = (u8 *)block;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) if (alen <= 65280) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /* Write first u32 of B1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) b8[0] = (alen >> 8) & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) b8[1] = alen & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) len = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) /* Build the two first u32 of B1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) b8[0] = 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) b8[1] = 0xFE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) b8[2] = (alen & 0xFF000000) >> 24;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) b8[3] = (alen & 0x00FF0000) >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) b8[4] = (alen & 0x0000FF00) >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) b8[5] = alen & 0x000000FF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) len = 6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) written = min_t(size_t, AES_BLOCK_SIZE - len, alen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) scatterwalk_copychunks((char *)block + len, &cryp->in_walk, written, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) for (i = 0; i < AES_BLOCK_32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) stm32_cryp_write(cryp, CRYP_DIN, block[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) cryp->header_in -= written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) stm32_crypt_gcmccm_end_header(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) static int stm32_cryp_ccm_init(struct stm32_cryp *cryp, u32 cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) u32 iv_32[AES_BLOCK_32], b0_32[AES_BLOCK_32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) u8 *iv = (u8 *)iv_32, *b0 = (u8 *)b0_32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) __be32 *bd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) u32 *d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) unsigned int i, textlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) /* Phase 1 : init. Firstly set the CTR value to 1 (not 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) memcpy(iv, cryp->areq->iv, AES_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) memset(iv + AES_BLOCK_SIZE - 1 - iv[0], 0, iv[0] + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) iv[AES_BLOCK_SIZE - 1] = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) stm32_cryp_hw_write_iv(cryp, (__be32 *)iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) /* Build B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) memcpy(b0, iv, AES_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) b0[0] |= (8 * ((cryp->authsize - 2) / 2));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) if (cryp->areq->assoclen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) b0[0] |= 0x40;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) textlen = stm32_cryp_get_input_text_len(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) b0[AES_BLOCK_SIZE - 2] = textlen >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) b0[AES_BLOCK_SIZE - 1] = textlen & 0xFF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /* Enable HW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) stm32_cryp_write(cryp, CRYP_CR, cfg | CR_PH_INIT | CR_CRYPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Write B0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) d = (u32 *)b0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) bd = (__be32 *)b0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) for (i = 0; i < AES_BLOCK_32; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u32 xd = d[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) if (!cryp->caps->padding_wa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) xd = be32_to_cpu(bd[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) stm32_cryp_write(cryp, CRYP_DIN, xd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) /* Wait for end of processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) ret = stm32_cryp_wait_enable(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev_err(cryp->dev, "Timeout (ccm init)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /* Prepare next phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) if (cryp->areq->assoclen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) cfg |= CR_PH_HEADER | CR_CRYPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) /* Write first (special) block (may move to next phase [payload]) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) stm32_cryp_write_ccm_first_header(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) } else if (stm32_cryp_get_input_text_len(cryp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) cfg |= CR_PH_PAYLOAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) static int stm32_cryp_hw_init(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) u32 cfg, hw_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) pm_runtime_get_sync(cryp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /* Disable interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) stm32_cryp_write(cryp, CRYP_IMSCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* Set key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) stm32_cryp_hw_write_key(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /* Set configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) cfg = CR_DATA8 | CR_FFLUSH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) switch (cryp->ctx->keylen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) case AES_KEYSIZE_128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) cfg |= CR_KEY128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) case AES_KEYSIZE_192:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) cfg |= CR_KEY192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) case AES_KEYSIZE_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) cfg |= CR_KEY256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) hw_mode = stm32_cryp_get_hw_mode(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (hw_mode == CR_AES_UNKNOWN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /* AES ECB/CBC decrypt: run key preparation first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) if (is_decrypt(cryp) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ((hw_mode == CR_AES_ECB) || (hw_mode == CR_AES_CBC))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) stm32_cryp_write(cryp, CRYP_CR, cfg | CR_AES_KP | CR_CRYPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) /* Wait for end of processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) ret = stm32_cryp_wait_busy(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) dev_err(cryp->dev, "Timeout (key preparation)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) cfg |= hw_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) if (is_decrypt(cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) cfg |= CR_DEC_NOT_ENC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /* Apply config and flush (valid when CRYPEN = 0) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) switch (hw_mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) case CR_AES_GCM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) case CR_AES_CCM:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /* Phase 1 : init */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (hw_mode == CR_AES_CCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ret = stm32_cryp_ccm_init(cryp, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) ret = stm32_cryp_gcm_init(cryp, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) case CR_DES_CBC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) case CR_TDES_CBC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) case CR_AES_CBC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) case CR_AES_CTR:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) stm32_cryp_hw_write_iv(cryp, (__be32 *)cryp->req->iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /* Enable now */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) cfg |= CR_CRYPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static void stm32_cryp_finish_req(struct stm32_cryp *cryp, int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if (!err && (is_gcm(cryp) || is_ccm(cryp)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) /* Phase 4 : output tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) err = stm32_cryp_read_auth_tag(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) if (!err && (!(is_gcm(cryp) || is_ccm(cryp) || is_ecb(cryp))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) stm32_cryp_get_iv(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pm_runtime_mark_last_busy(cryp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) pm_runtime_put_autosuspend(cryp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) if (is_gcm(cryp) || is_ccm(cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) crypto_finalize_aead_request(cryp->engine, cryp->areq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) crypto_finalize_skcipher_request(cryp->engine, cryp->req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) static int stm32_cryp_cpu_start(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) /* Enable interrupt and let the IRQ handler do everything */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) stm32_cryp_write(cryp, CRYP_IMSCR, IMSCR_IN | IMSCR_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static int stm32_cryp_cipher_one_req(struct crypto_engine *engine, void *areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) static int stm32_cryp_prepare_cipher_req(struct crypto_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) void *areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int stm32_cryp_init_tfm(struct crypto_skcipher *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct stm32_cryp_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) crypto_skcipher_set_reqsize(tfm, sizeof(struct stm32_cryp_reqctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ctx->enginectx.op.do_one_request = stm32_cryp_cipher_one_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ctx->enginectx.op.prepare_request = stm32_cryp_prepare_cipher_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) ctx->enginectx.op.unprepare_request = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) static int stm32_cryp_aead_one_req(struct crypto_engine *engine, void *areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static int stm32_cryp_prepare_aead_req(struct crypto_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) void *areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) static int stm32_cryp_aes_aead_init(struct crypto_aead *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) struct stm32_cryp_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) tfm->reqsize = sizeof(struct stm32_cryp_reqctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ctx->enginectx.op.do_one_request = stm32_cryp_aead_one_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) ctx->enginectx.op.prepare_request = stm32_cryp_prepare_aead_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) ctx->enginectx.op.unprepare_request = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) static int stm32_cryp_crypt(struct skcipher_request *req, unsigned long mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) struct stm32_cryp_ctx *ctx = crypto_skcipher_ctx(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) struct stm32_cryp_reqctx *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) struct stm32_cryp *cryp = stm32_cryp_find_dev(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (!cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) rctx->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) return crypto_transfer_skcipher_request_to_engine(cryp->engine, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) static int stm32_cryp_aead_crypt(struct aead_request *req, unsigned long mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) struct stm32_cryp_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct stm32_cryp_reqctx *rctx = aead_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct stm32_cryp *cryp = stm32_cryp_find_dev(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) if (!cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) rctx->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) return crypto_transfer_aead_request_to_engine(cryp->engine, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) static int stm32_cryp_setkey(struct crypto_skcipher *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) struct stm32_cryp_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) ctx->keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) static int stm32_cryp_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) keylen != AES_KEYSIZE_256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) return stm32_cryp_setkey(tfm, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) static int stm32_cryp_des_setkey(struct crypto_skcipher *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return verify_skcipher_des_key(tfm, key) ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) stm32_cryp_setkey(tfm, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) static int stm32_cryp_tdes_setkey(struct crypto_skcipher *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) return verify_skcipher_des3_key(tfm, key) ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) stm32_cryp_setkey(tfm, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) static int stm32_cryp_aes_aead_setkey(struct crypto_aead *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) struct stm32_cryp_ctx *ctx = crypto_aead_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) keylen != AES_KEYSIZE_256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) ctx->keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) static int stm32_cryp_aes_gcm_setauthsize(struct crypto_aead *tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) switch (authsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) case 13:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) case 14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) case 15:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) static int stm32_cryp_aes_ccm_setauthsize(struct crypto_aead *tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) unsigned int authsize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) switch (authsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) case 4:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) case 6:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) case 8:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) case 10:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case 12:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) case 14:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) case 16:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) static int stm32_cryp_aes_ecb_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (req->cryptlen % AES_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) if (req->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) return stm32_cryp_crypt(req, FLG_AES | FLG_ECB | FLG_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) static int stm32_cryp_aes_ecb_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) if (req->cryptlen % AES_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (req->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) return stm32_cryp_crypt(req, FLG_AES | FLG_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static int stm32_cryp_aes_cbc_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) if (req->cryptlen % AES_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (req->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) return stm32_cryp_crypt(req, FLG_AES | FLG_CBC | FLG_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) static int stm32_cryp_aes_cbc_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (req->cryptlen % AES_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (req->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) return stm32_cryp_crypt(req, FLG_AES | FLG_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) static int stm32_cryp_aes_ctr_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) if (req->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) return stm32_cryp_crypt(req, FLG_AES | FLG_CTR | FLG_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) static int stm32_cryp_aes_ctr_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) if (req->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) return stm32_cryp_crypt(req, FLG_AES | FLG_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) static int stm32_cryp_aes_gcm_encrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) return stm32_cryp_aead_crypt(req, FLG_AES | FLG_GCM | FLG_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) static int stm32_cryp_aes_gcm_decrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return stm32_cryp_aead_crypt(req, FLG_AES | FLG_GCM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static inline int crypto_ccm_check_iv(const u8 *iv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /* 2 <= L <= 8, so 1 <= L' <= 7. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) if (iv[0] < 1 || iv[0] > 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) static int stm32_cryp_aes_ccm_encrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) err = crypto_ccm_check_iv(req->iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) return stm32_cryp_aead_crypt(req, FLG_AES | FLG_CCM | FLG_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) static int stm32_cryp_aes_ccm_decrypt(struct aead_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) err = crypto_ccm_check_iv(req->iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) return stm32_cryp_aead_crypt(req, FLG_AES | FLG_CCM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) static int stm32_cryp_des_ecb_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) if (req->cryptlen % DES_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) if (req->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return stm32_cryp_crypt(req, FLG_DES | FLG_ECB | FLG_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) static int stm32_cryp_des_ecb_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (req->cryptlen % DES_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) if (req->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) return stm32_cryp_crypt(req, FLG_DES | FLG_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) static int stm32_cryp_des_cbc_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) if (req->cryptlen % DES_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) if (req->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) return stm32_cryp_crypt(req, FLG_DES | FLG_CBC | FLG_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) static int stm32_cryp_des_cbc_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) if (req->cryptlen % DES_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (req->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return stm32_cryp_crypt(req, FLG_DES | FLG_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) static int stm32_cryp_tdes_ecb_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) if (req->cryptlen % DES_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (req->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) return stm32_cryp_crypt(req, FLG_TDES | FLG_ECB | FLG_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) static int stm32_cryp_tdes_ecb_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) if (req->cryptlen % DES_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) if (req->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return stm32_cryp_crypt(req, FLG_TDES | FLG_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static int stm32_cryp_tdes_cbc_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) if (req->cryptlen % DES_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) if (req->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) return stm32_cryp_crypt(req, FLG_TDES | FLG_CBC | FLG_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) static int stm32_cryp_tdes_cbc_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) if (req->cryptlen % DES_BLOCK_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) if (req->cryptlen == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) return stm32_cryp_crypt(req, FLG_TDES | FLG_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) static int stm32_cryp_prepare_req(struct skcipher_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) struct aead_request *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) struct stm32_cryp_ctx *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct stm32_cryp *cryp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct stm32_cryp_reqctx *rctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) struct scatterlist *in_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) if (!req && !areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) ctx = req ? crypto_skcipher_ctx(crypto_skcipher_reqtfm(req)) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) crypto_aead_ctx(crypto_aead_reqtfm(areq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) cryp = ctx->cryp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) if (!cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) rctx = req ? skcipher_request_ctx(req) : aead_request_ctx(areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) rctx->mode &= FLG_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) ctx->cryp = cryp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) cryp->flags = (cryp->flags & ~FLG_MODE_MASK) | rctx->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) cryp->hw_blocksize = is_aes(cryp) ? AES_BLOCK_SIZE : DES_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) cryp->ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) if (req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) cryp->req = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) cryp->areq = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) cryp->header_in = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) cryp->payload_in = req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) cryp->payload_out = req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) cryp->authsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) * Length of input and output data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) * Encryption case:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) * INPUT = AssocData || PlainText
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) * <- assoclen -> <- cryptlen ->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) * OUTPUT = AssocData || CipherText || AuthTag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) * <- assoclen -> <-- cryptlen --> <- authsize ->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) * Decryption case:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) * INPUT = AssocData || CipherTex || AuthTag
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) * <- assoclen ---> <---------- cryptlen ---------->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) * OUTPUT = AssocData || PlainText
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) * <- assoclen -> <- cryptlen - authsize ->
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) cryp->areq = areq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) cryp->req = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) cryp->authsize = crypto_aead_authsize(crypto_aead_reqtfm(areq));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (is_encrypt(cryp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) cryp->payload_in = areq->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) cryp->header_in = areq->assoclen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) cryp->payload_out = areq->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) cryp->payload_in = areq->cryptlen - cryp->authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) cryp->header_in = areq->assoclen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) cryp->payload_out = cryp->payload_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) in_sg = req ? req->src : areq->src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) scatterwalk_start(&cryp->in_walk, in_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) cryp->out_sg = req ? req->dst : areq->dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) scatterwalk_start(&cryp->out_walk, cryp->out_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) if (is_gcm(cryp) || is_ccm(cryp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) /* In output, jump after assoc data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) scatterwalk_copychunks(NULL, &cryp->out_walk, cryp->areq->assoclen, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) if (is_ctr(cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) memset(cryp->last_ctr, 0, sizeof(cryp->last_ctr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ret = stm32_cryp_hw_init(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) static int stm32_cryp_prepare_cipher_req(struct crypto_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) void *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) struct skcipher_request *req = container_of(areq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) struct skcipher_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return stm32_cryp_prepare_req(req, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static int stm32_cryp_cipher_one_req(struct crypto_engine *engine, void *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct skcipher_request *req = container_of(areq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct skcipher_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) struct stm32_cryp_ctx *ctx = crypto_skcipher_ctx(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) struct stm32_cryp *cryp = ctx->cryp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) if (!cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) return stm32_cryp_cpu_start(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) static int stm32_cryp_prepare_aead_req(struct crypto_engine *engine, void *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) struct aead_request *req = container_of(areq, struct aead_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) return stm32_cryp_prepare_req(NULL, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) static int stm32_cryp_aead_one_req(struct crypto_engine *engine, void *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct aead_request *req = container_of(areq, struct aead_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct stm32_cryp_ctx *ctx = crypto_aead_ctx(crypto_aead_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct stm32_cryp *cryp = ctx->cryp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (!cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (unlikely(!cryp->payload_in && !cryp->header_in)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) /* No input data to process: get tag and finish */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) stm32_cryp_finish_req(cryp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) return stm32_cryp_cpu_start(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) static int stm32_cryp_read_auth_tag(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) u32 cfg, size_bit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) /* Update Config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) cfg = stm32_cryp_read(cryp, CRYP_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) cfg &= ~CR_PH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) cfg |= CR_PH_FINAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) cfg &= ~CR_DEC_NOT_ENC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) cfg |= CR_CRYPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (is_gcm(cryp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) /* GCM: write aad and payload size (in bits) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) size_bit = cryp->areq->assoclen * 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) if (cryp->caps->swap_final)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) size_bit = (__force u32)cpu_to_be32(size_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) stm32_cryp_write(cryp, CRYP_DIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) stm32_cryp_write(cryp, CRYP_DIN, size_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) size_bit = is_encrypt(cryp) ? cryp->areq->cryptlen :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) cryp->areq->cryptlen - cryp->authsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) size_bit *= 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (cryp->caps->swap_final)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) size_bit = (__force u32)cpu_to_be32(size_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) stm32_cryp_write(cryp, CRYP_DIN, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) stm32_cryp_write(cryp, CRYP_DIN, size_bit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) /* CCM: write CTR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) u32 iv32[AES_BLOCK_32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) u8 *iv = (u8 *)iv32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) __be32 *biv = (__be32 *)iv32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) memcpy(iv, cryp->areq->iv, AES_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) memset(iv + AES_BLOCK_SIZE - 1 - iv[0], 0, iv[0] + 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) for (i = 0; i < AES_BLOCK_32; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) u32 xiv = iv32[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) if (!cryp->caps->padding_wa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) xiv = be32_to_cpu(biv[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) stm32_cryp_write(cryp, CRYP_DIN, xiv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) /* Wait for output data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) ret = stm32_cryp_wait_output(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) dev_err(cryp->dev, "Timeout (read tag)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (is_encrypt(cryp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) u32 out_tag[AES_BLOCK_32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) /* Get and write tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) for (i = 0; i < AES_BLOCK_32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) out_tag[i] = stm32_cryp_read(cryp, CRYP_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) scatterwalk_copychunks(out_tag, &cryp->out_walk, cryp->authsize, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) /* Get and check tag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) u32 in_tag[AES_BLOCK_32], out_tag[AES_BLOCK_32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) scatterwalk_copychunks(in_tag, &cryp->in_walk, cryp->authsize, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) for (i = 0; i < AES_BLOCK_32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) out_tag[i] = stm32_cryp_read(cryp, CRYP_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) if (crypto_memneq(in_tag, out_tag, cryp->authsize))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) ret = -EBADMSG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) /* Disable cryp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) cfg &= ~CR_CRYPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) static void stm32_cryp_check_ctr_counter(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) u32 cr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (unlikely(cryp->last_ctr[3] == cpu_to_be32(0xFFFFFFFF))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) * In this case, we need to increment manually the ctr counter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) * as HW doesn't handle the U32 carry.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) crypto_inc((u8 *)cryp->last_ctr, sizeof(cryp->last_ctr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) cr = stm32_cryp_read(cryp, CRYP_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) stm32_cryp_write(cryp, CRYP_CR, cr & ~CR_CRYPEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) stm32_cryp_hw_write_iv(cryp, cryp->last_ctr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) stm32_cryp_write(cryp, CRYP_CR, cr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) /* The IV registers are BE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) cryp->last_ctr[0] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV0LR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) cryp->last_ctr[1] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV0RR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) cryp->last_ctr[2] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV1LR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) cryp->last_ctr[3] = cpu_to_be32(stm32_cryp_read(cryp, CRYP_IV1RR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static void stm32_cryp_irq_read_data(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) u32 block[AES_BLOCK_32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) for (i = 0; i < cryp->hw_blocksize / sizeof(u32); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) block[i] = stm32_cryp_read(cryp, CRYP_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) scatterwalk_copychunks(block, &cryp->out_walk, min_t(size_t, cryp->hw_blocksize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) cryp->payload_out), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) cryp->payload_out -= min_t(size_t, cryp->hw_blocksize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) cryp->payload_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) static void stm32_cryp_irq_write_block(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) u32 block[AES_BLOCK_32] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) scatterwalk_copychunks(block, &cryp->in_walk, min_t(size_t, cryp->hw_blocksize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) cryp->payload_in), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) for (i = 0; i < cryp->hw_blocksize / sizeof(u32); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) stm32_cryp_write(cryp, CRYP_DIN, block[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) cryp->payload_in -= min_t(size_t, cryp->hw_blocksize, cryp->payload_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) static void stm32_cryp_irq_write_gcm_padded_data(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) u32 cfg, block[AES_BLOCK_32] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) /* 'Special workaround' procedure described in the datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) /* a) disable ip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) stm32_cryp_write(cryp, CRYP_IMSCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) cfg = stm32_cryp_read(cryp, CRYP_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) cfg &= ~CR_CRYPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) /* b) Update IV1R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) stm32_cryp_write(cryp, CRYP_IV1RR, cryp->gcm_ctr - 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) /* c) change mode to CTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) cfg &= ~CR_ALGO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) cfg |= CR_AES_CTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) /* a) enable IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) cfg |= CR_CRYPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /* b) pad and write the last block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) stm32_cryp_irq_write_block(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) /* wait end of process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) err = stm32_cryp_wait_output(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_err(cryp->dev, "Timeout (write gcm last data)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return stm32_cryp_finish_req(cryp, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) /* c) get and store encrypted data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) * Same code as stm32_cryp_irq_read_data(), but we want to store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) * block value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) for (i = 0; i < cryp->hw_blocksize / sizeof(u32); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) block[i] = stm32_cryp_read(cryp, CRYP_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) scatterwalk_copychunks(block, &cryp->out_walk, min_t(size_t, cryp->hw_blocksize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) cryp->payload_out), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) cryp->payload_out -= min_t(size_t, cryp->hw_blocksize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) cryp->payload_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) /* d) change mode back to AES GCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) cfg &= ~CR_ALGO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) cfg |= CR_AES_GCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) /* e) change phase to Final */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) cfg &= ~CR_PH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) cfg |= CR_PH_FINAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) /* f) write padded data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) for (i = 0; i < AES_BLOCK_32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) stm32_cryp_write(cryp, CRYP_DIN, block[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) /* g) Empty fifo out */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) err = stm32_cryp_wait_output(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) dev_err(cryp->dev, "Timeout (write gcm padded data)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) return stm32_cryp_finish_req(cryp, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) for (i = 0; i < AES_BLOCK_32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) stm32_cryp_read(cryp, CRYP_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) /* h) run the he normal Final phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) stm32_cryp_finish_req(cryp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) static void stm32_cryp_irq_set_npblb(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) u32 cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) /* disable ip, set NPBLB and reneable ip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) cfg = stm32_cryp_read(cryp, CRYP_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) cfg &= ~CR_CRYPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) cfg |= (cryp->hw_blocksize - cryp->payload_in) << CR_NBPBL_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) cfg |= CR_CRYPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) static void stm32_cryp_irq_write_ccm_padded_data(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) u32 cfg, iv1tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) u32 cstmp1[AES_BLOCK_32], cstmp2[AES_BLOCK_32];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) u32 block[AES_BLOCK_32] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) /* 'Special workaround' procedure described in the datasheet */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) /* a) disable ip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) stm32_cryp_write(cryp, CRYP_IMSCR, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) cfg = stm32_cryp_read(cryp, CRYP_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) cfg &= ~CR_CRYPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) /* b) get IV1 from CRYP_CSGCMCCM7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) iv1tmp = stm32_cryp_read(cryp, CRYP_CSGCMCCM0R + 7 * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) /* c) Load CRYP_CSGCMCCMxR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) for (i = 0; i < ARRAY_SIZE(cstmp1); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) cstmp1[i] = stm32_cryp_read(cryp, CRYP_CSGCMCCM0R + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) /* d) Write IV1R */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) stm32_cryp_write(cryp, CRYP_IV1RR, iv1tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) /* e) change mode to CTR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) cfg &= ~CR_ALGO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) cfg |= CR_AES_CTR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) /* a) enable IP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) cfg |= CR_CRYPEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* b) pad and write the last block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) stm32_cryp_irq_write_block(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) /* wait end of process */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) err = stm32_cryp_wait_output(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) dev_err(cryp->dev, "Timeout (wite ccm padded data)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) return stm32_cryp_finish_req(cryp, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) /* c) get and store decrypted data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) * Same code as stm32_cryp_irq_read_data(), but we want to store
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) * block value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) for (i = 0; i < cryp->hw_blocksize / sizeof(u32); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) block[i] = stm32_cryp_read(cryp, CRYP_DOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) scatterwalk_copychunks(block, &cryp->out_walk, min_t(size_t, cryp->hw_blocksize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) cryp->payload_out), 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) cryp->payload_out -= min_t(size_t, cryp->hw_blocksize, cryp->payload_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) /* d) Load again CRYP_CSGCMCCMxR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) for (i = 0; i < ARRAY_SIZE(cstmp2); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) cstmp2[i] = stm32_cryp_read(cryp, CRYP_CSGCMCCM0R + i * 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* e) change mode back to AES CCM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) cfg &= ~CR_ALGO_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) cfg |= CR_AES_CCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) /* f) change phase to header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) cfg &= ~CR_PH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) cfg |= CR_PH_HEADER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) stm32_cryp_write(cryp, CRYP_CR, cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) /* g) XOR and write padded data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) for (i = 0; i < ARRAY_SIZE(block); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) block[i] ^= cstmp1[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) block[i] ^= cstmp2[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) stm32_cryp_write(cryp, CRYP_DIN, block[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) /* h) wait for completion */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) err = stm32_cryp_wait_busy(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) dev_err(cryp->dev, "Timeout (wite ccm padded data)\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* i) run the he normal Final phase */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) stm32_cryp_finish_req(cryp, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) static void stm32_cryp_irq_write_data(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) if (unlikely(!cryp->payload_in)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) dev_warn(cryp->dev, "No more data to process\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) if (unlikely(cryp->payload_in < AES_BLOCK_SIZE &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) (stm32_cryp_get_hw_mode(cryp) == CR_AES_GCM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) is_encrypt(cryp))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) /* Padding for AES GCM encryption */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) if (cryp->caps->padding_wa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) /* Special case 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) stm32_cryp_irq_write_gcm_padded_data(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) /* Setting padding bytes (NBBLB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) stm32_cryp_irq_set_npblb(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (unlikely((cryp->payload_in < AES_BLOCK_SIZE) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) (stm32_cryp_get_hw_mode(cryp) == CR_AES_CCM) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) is_decrypt(cryp))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) /* Padding for AES CCM decryption */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) if (cryp->caps->padding_wa) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) /* Special case 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) stm32_cryp_irq_write_ccm_padded_data(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) /* Setting padding bytes (NBBLB) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) stm32_cryp_irq_set_npblb(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) if (is_aes(cryp) && is_ctr(cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) stm32_cryp_check_ctr_counter(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) stm32_cryp_irq_write_block(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) static void stm32_cryp_irq_write_gcmccm_header(struct stm32_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) u32 block[AES_BLOCK_32] = {0};
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) size_t written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) written = min_t(size_t, AES_BLOCK_SIZE, cryp->header_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) scatterwalk_copychunks(block, &cryp->in_walk, written, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) for (i = 0; i < AES_BLOCK_32; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) stm32_cryp_write(cryp, CRYP_DIN, block[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) cryp->header_in -= written;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) stm32_crypt_gcmccm_end_header(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) static irqreturn_t stm32_cryp_irq_thread(int irq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) struct stm32_cryp *cryp = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) u32 ph;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) u32 it_mask = stm32_cryp_read(cryp, CRYP_IMSCR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) if (cryp->irq_status & MISR_OUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) /* Output FIFO IRQ: read data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) stm32_cryp_irq_read_data(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) if (cryp->irq_status & MISR_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (is_gcm(cryp) || is_ccm(cryp)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) ph = stm32_cryp_read(cryp, CRYP_CR) & CR_PH_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) if (unlikely(ph == CR_PH_HEADER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) /* Write Header */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) stm32_cryp_irq_write_gcmccm_header(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) /* Input FIFO IRQ: write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) stm32_cryp_irq_write_data(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) if (is_gcm(cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) cryp->gcm_ctr++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) /* Input FIFO IRQ: write data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) stm32_cryp_irq_write_data(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) /* Mask useless interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) if (!cryp->payload_in && !cryp->header_in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) it_mask &= ~IMSCR_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) if (!cryp->payload_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) it_mask &= ~IMSCR_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) stm32_cryp_write(cryp, CRYP_IMSCR, it_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) if (!cryp->payload_in && !cryp->header_in && !cryp->payload_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) stm32_cryp_finish_req(cryp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) static irqreturn_t stm32_cryp_irq(int irq, void *arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) struct stm32_cryp *cryp = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) cryp->irq_status = stm32_cryp_read(cryp, CRYP_MISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) return IRQ_WAKE_THREAD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) static struct skcipher_alg crypto_algs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .base.cra_name = "ecb(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .base.cra_driver_name = "stm32-ecb-aes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .base.cra_priority = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .base.cra_flags = CRYPTO_ALG_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .base.cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) .base.cra_alignmask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .init = stm32_cryp_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .setkey = stm32_cryp_aes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) .encrypt = stm32_cryp_aes_ecb_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) .decrypt = stm32_cryp_aes_ecb_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .base.cra_name = "cbc(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .base.cra_driver_name = "stm32-cbc-aes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .base.cra_priority = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .base.cra_flags = CRYPTO_ALG_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .base.cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .base.cra_alignmask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .init = stm32_cryp_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .setkey = stm32_cryp_aes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .encrypt = stm32_cryp_aes_cbc_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .decrypt = stm32_cryp_aes_cbc_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) .base.cra_name = "ctr(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) .base.cra_driver_name = "stm32-ctr-aes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) .base.cra_priority = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .base.cra_flags = CRYPTO_ALG_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .base.cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .base.cra_alignmask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .init = stm32_cryp_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .setkey = stm32_cryp_aes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .encrypt = stm32_cryp_aes_ctr_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) .decrypt = stm32_cryp_aes_ctr_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .base.cra_name = "ecb(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) .base.cra_driver_name = "stm32-ecb-des",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .base.cra_priority = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .base.cra_flags = CRYPTO_ALG_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) .base.cra_alignmask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .init = stm32_cryp_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .min_keysize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .max_keysize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .setkey = stm32_cryp_des_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .encrypt = stm32_cryp_des_ecb_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .decrypt = stm32_cryp_des_ecb_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .base.cra_name = "cbc(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .base.cra_driver_name = "stm32-cbc-des",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .base.cra_priority = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .base.cra_flags = CRYPTO_ALG_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .base.cra_alignmask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .init = stm32_cryp_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .min_keysize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .max_keysize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) .setkey = stm32_cryp_des_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .encrypt = stm32_cryp_des_cbc_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .decrypt = stm32_cryp_des_cbc_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) .base.cra_name = "ecb(des3_ede)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .base.cra_driver_name = "stm32-ecb-des3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .base.cra_priority = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .base.cra_flags = CRYPTO_ALG_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .base.cra_alignmask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .init = stm32_cryp_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .min_keysize = 3 * DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .max_keysize = 3 * DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) .setkey = stm32_cryp_tdes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) .encrypt = stm32_cryp_tdes_ecb_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .decrypt = stm32_cryp_tdes_ecb_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .base.cra_name = "cbc(des3_ede)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .base.cra_driver_name = "stm32-cbc-des3",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .base.cra_priority = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) .base.cra_flags = CRYPTO_ALG_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) .base.cra_ctxsize = sizeof(struct stm32_cryp_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .base.cra_alignmask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .init = stm32_cryp_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .min_keysize = 3 * DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .max_keysize = 3 * DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .setkey = stm32_cryp_tdes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .encrypt = stm32_cryp_tdes_cbc_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .decrypt = stm32_cryp_tdes_cbc_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) static struct aead_alg aead_algs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .setkey = stm32_cryp_aes_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .setauthsize = stm32_cryp_aes_gcm_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .encrypt = stm32_cryp_aes_gcm_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .decrypt = stm32_cryp_aes_gcm_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) .init = stm32_cryp_aes_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) .ivsize = 12,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .cra_name = "gcm(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .cra_driver_name = "stm32-gcm-aes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .cra_priority = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .cra_flags = CRYPTO_ALG_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .cra_ctxsize = sizeof(struct stm32_cryp_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .cra_alignmask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) .setkey = stm32_cryp_aes_aead_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .setauthsize = stm32_cryp_aes_ccm_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .encrypt = stm32_cryp_aes_ccm_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) .decrypt = stm32_cryp_aes_ccm_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .init = stm32_cryp_aes_aead_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) .cra_name = "ccm(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) .cra_driver_name = "stm32-ccm-aes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .cra_priority = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .cra_flags = CRYPTO_ALG_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .cra_ctxsize = sizeof(struct stm32_cryp_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .cra_alignmask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) static const struct stm32_cryp_caps f7_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .swap_final = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) .padding_wa = true,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) static const struct stm32_cryp_caps mp1_data = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) .swap_final = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .padding_wa = false,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) static const struct of_device_id stm32_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) { .compatible = "st,stm32f756-cryp", .data = &f7_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) { .compatible = "st,stm32mp1-cryp", .data = &mp1_data},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) MODULE_DEVICE_TABLE(of, stm32_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) static int stm32_cryp_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) struct stm32_cryp *cryp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) struct reset_control *rst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) int irq, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) cryp = devm_kzalloc(dev, sizeof(*cryp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) if (!cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) cryp->caps = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) if (!cryp->caps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) cryp->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) cryp->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) if (IS_ERR(cryp->regs))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) return PTR_ERR(cryp->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) ret = devm_request_threaded_irq(dev, irq, stm32_cryp_irq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) stm32_cryp_irq_thread, IRQF_ONESHOT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) dev_name(dev), cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) dev_err(dev, "Cannot grab IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) cryp->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) if (IS_ERR(cryp->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) dev_err(dev, "Could not get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) return PTR_ERR(cryp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) ret = clk_prepare_enable(cryp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) dev_err(cryp->dev, "Failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) pm_runtime_set_autosuspend_delay(dev, CRYP_AUTOSUSPEND_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) pm_runtime_use_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) pm_runtime_get_noresume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) rst = devm_reset_control_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) if (!IS_ERR(rst)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) reset_control_assert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) udelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) reset_control_deassert(rst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) platform_set_drvdata(pdev, cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) spin_lock(&cryp_list.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) list_add(&cryp->list, &cryp_list.dev_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) spin_unlock(&cryp_list.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) /* Initialize crypto engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) cryp->engine = crypto_engine_alloc_init(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) if (!cryp->engine) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) dev_err(dev, "Could not init crypto engine\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) goto err_engine1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) ret = crypto_engine_start(cryp->engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) dev_err(dev, "Could not start crypto engine\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) goto err_engine2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) ret = crypto_register_skciphers(crypto_algs, ARRAY_SIZE(crypto_algs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) dev_err(dev, "Could not register algs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) goto err_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) ret = crypto_register_aeads(aead_algs, ARRAY_SIZE(aead_algs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) goto err_aead_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) dev_info(dev, "Initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) err_aead_algs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) crypto_unregister_skciphers(crypto_algs, ARRAY_SIZE(crypto_algs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) err_algs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) err_engine2:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) crypto_engine_exit(cryp->engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) err_engine1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) spin_lock(&cryp_list.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) list_del(&cryp->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) spin_unlock(&cryp_list.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) clk_disable_unprepare(cryp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) static int stm32_cryp_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) struct stm32_cryp *cryp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) if (!cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) ret = pm_runtime_resume_and_get(cryp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) crypto_unregister_aeads(aead_algs, ARRAY_SIZE(aead_algs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) crypto_unregister_skciphers(crypto_algs, ARRAY_SIZE(crypto_algs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) crypto_engine_exit(cryp->engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) spin_lock(&cryp_list.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) list_del(&cryp->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) spin_unlock(&cryp_list.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) pm_runtime_disable(cryp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) pm_runtime_put_noidle(cryp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) clk_disable_unprepare(cryp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) #ifdef CONFIG_PM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) static int stm32_cryp_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) struct stm32_cryp *cryp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) clk_disable_unprepare(cryp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) static int stm32_cryp_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) struct stm32_cryp *cryp = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) ret = clk_prepare_enable(cryp->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) dev_err(cryp->dev, "Failed to prepare_enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) static const struct dev_pm_ops stm32_cryp_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) pm_runtime_force_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) SET_RUNTIME_PM_OPS(stm32_cryp_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) stm32_cryp_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) static struct platform_driver stm32_cryp_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .probe = stm32_cryp_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .remove = stm32_cryp_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .pm = &stm32_cryp_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .of_match_table = stm32_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) module_platform_driver(stm32_cryp_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) MODULE_DESCRIPTION("STMicrolectronics STM32 CRYP hardware driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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