^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) STMicroelectronics SA 2017
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Fabien Dessenne <fabien.dessenne@st.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/bitrev.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/crc32.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/crc32poly.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <crypto/internal/hash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <asm/unaligned.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DRIVER_NAME "stm32-crc32"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CHKSUM_DIGEST_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CHKSUM_BLOCK_SIZE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CRC_DR 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CRC_CR 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CRC_INIT 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CRC_POL 0x00000014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) /* Registers values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CRC_CR_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CRC_CR_REV_IN_WORD (BIT(6) | BIT(5))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CRC_CR_REV_IN_BYTE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CRC_CR_REV_OUT BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CRC32C_INIT_DEFAULT 0xFFFFFFFF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CRC_AUTOSUSPEND_DELAY 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static unsigned int burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) module_param(burst_size, uint, 0644);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) MODULE_PARM_DESC(burst_size, "Select burst byte size (0 unlimited)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) struct stm32_crc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) struct stm32_crc_list {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) struct list_head dev_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) spinlock_t lock; /* protect dev_list */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) static struct stm32_crc_list crc_list = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) .dev_list = LIST_HEAD_INIT(crc_list.dev_list),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) .lock = __SPIN_LOCK_UNLOCKED(crc_list.lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) struct stm32_crc_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) u32 key;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) u32 poly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) struct stm32_crc_desc_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) u32 partial; /* crc32c: partial in first 4 bytes of that struct */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) static int stm32_crc32_cra_init(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) mctx->key = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) mctx->poly = CRC32_POLY_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) static int stm32_crc32c_cra_init(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) struct stm32_crc_ctx *mctx = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) mctx->key = CRC32C_INIT_DEFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mctx->poly = CRC32C_POLY_LE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static int stm32_crc_setkey(struct crypto_shash *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) struct stm32_crc_ctx *mctx = crypto_shash_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) if (keylen != sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) mctx->key = get_unaligned_le32(key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static struct stm32_crc *stm32_crc_get_next_crc(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) struct stm32_crc *crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) spin_lock_bh(&crc_list.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) crc = list_first_entry(&crc_list.dev_list, struct stm32_crc, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (crc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) list_move_tail(&crc->list, &crc_list.dev_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) spin_unlock_bh(&crc_list.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) static int stm32_crc_init(struct shash_desc *desc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) struct stm32_crc *crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) crc = stm32_crc_get_next_crc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) if (!crc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) pm_runtime_get_sync(crc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) spin_lock_irqsave(&crc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Reset, set key, poly and configure in bit reverse mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) writel_relaxed(bitrev32(mctx->key), crc->regs + CRC_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) writel_relaxed(CRC_CR_RESET | CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) crc->regs + CRC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* Store partial result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) ctx->partial = readl_relaxed(crc->regs + CRC_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) spin_unlock_irqrestore(&crc->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) pm_runtime_mark_last_busy(crc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) pm_runtime_put_autosuspend(crc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) static int burst_update(struct shash_desc *desc, const u8 *d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) size_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct stm32_crc *crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) crc = stm32_crc_get_next_crc();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) if (!crc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) pm_runtime_get_sync(crc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (!spin_trylock(&crc->lock)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* Hardware is busy, calculate crc32 by software */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) if (mctx->poly == CRC32_POLY_LE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) ctx->partial = crc32_le(ctx->partial, d8, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) ctx->partial = __crc32c_le(ctx->partial, d8, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) goto pm_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * Restore previously calculated CRC for this context as init value
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * Restore polynomial configuration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * Configure in register for word input data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * Configure out register in reversed bit mode data.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) writel_relaxed(bitrev32(ctx->partial), crc->regs + CRC_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) writel_relaxed(CRC_CR_RESET | CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) crc->regs + CRC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) if (d8 != PTR_ALIGN(d8, sizeof(u32))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Configure for byte data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) writel_relaxed(CRC_CR_REV_IN_BYTE | CRC_CR_REV_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) crc->regs + CRC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) while (d8 != PTR_ALIGN(d8, sizeof(u32)) && length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) writeb_relaxed(*d8++, crc->regs + CRC_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) length--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* Configure for word data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) writel_relaxed(CRC_CR_REV_IN_WORD | CRC_CR_REV_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) crc->regs + CRC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) for (; length >= sizeof(u32); d8 += sizeof(u32), length -= sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) writel_relaxed(*((u32 *)d8), crc->regs + CRC_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) if (length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* Configure for byte data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel_relaxed(CRC_CR_REV_IN_BYTE | CRC_CR_REV_OUT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) crc->regs + CRC_CR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) while (length--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) writeb_relaxed(*d8++, crc->regs + CRC_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* Store partial result */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ctx->partial = readl_relaxed(crc->regs + CRC_DR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) spin_unlock(&crc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) pm_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) pm_runtime_mark_last_busy(crc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) pm_runtime_put_autosuspend(crc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) static int stm32_crc_update(struct shash_desc *desc, const u8 *d8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) unsigned int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) const unsigned int burst_sz = burst_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) unsigned int rem_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) const u8 *cur;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) size_t size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) if (!burst_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) return burst_update(desc, d8, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) /* Digest first bytes not 32bit aligned at first pass in the loop */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) size = min_t(size_t, length, burst_sz + (size_t)d8 -
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ALIGN_DOWN((size_t)d8, sizeof(u32)));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) for (rem_sz = length, cur = d8; rem_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) rem_sz -= size, cur += size, size = min(rem_sz, burst_sz)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) ret = burst_update(desc, cur, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static int stm32_crc_final(struct shash_desc *desc, u8 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) struct stm32_crc_desc_ctx *ctx = shash_desc_ctx(desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct stm32_crc_ctx *mctx = crypto_shash_ctx(desc->tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* Send computed CRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) put_unaligned_le32(mctx->poly == CRC32C_POLY_LE ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) ~ctx->partial : ctx->partial, out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) static int stm32_crc_finup(struct shash_desc *desc, const u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) unsigned int length, u8 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) return stm32_crc_update(desc, data, length) ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) stm32_crc_final(desc, out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static int stm32_crc_digest(struct shash_desc *desc, const u8 *data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) unsigned int length, u8 *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) return stm32_crc_init(desc) ?: stm32_crc_finup(desc, data, length, out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static unsigned int refcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) static DEFINE_MUTEX(refcnt_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) static struct shash_alg algs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) /* CRC-32 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) .setkey = stm32_crc_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) .init = stm32_crc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) .update = stm32_crc_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) .final = stm32_crc_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) .finup = stm32_crc_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) .digest = stm32_crc_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) .descsize = sizeof(struct stm32_crc_desc_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) .digestsize = CHKSUM_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) .cra_name = "crc32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) .cra_driver_name = "stm32-crc32-crc32",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) .cra_priority = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) .cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) .cra_blocksize = CHKSUM_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) .cra_alignmask = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) .cra_ctxsize = sizeof(struct stm32_crc_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) .cra_init = stm32_crc32_cra_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* CRC-32Castagnoli */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) .setkey = stm32_crc_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) .init = stm32_crc_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) .update = stm32_crc_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) .final = stm32_crc_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) .finup = stm32_crc_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) .digest = stm32_crc_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) .descsize = sizeof(struct stm32_crc_desc_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) .digestsize = CHKSUM_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) .cra_name = "crc32c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) .cra_driver_name = "stm32-crc32-crc32c",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) .cra_priority = 200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) .cra_flags = CRYPTO_ALG_OPTIONAL_KEY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) .cra_blocksize = CHKSUM_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) .cra_alignmask = 3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) .cra_ctxsize = sizeof(struct stm32_crc_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) .cra_init = stm32_crc32c_cra_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) static int stm32_crc_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) struct stm32_crc *crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) if (!crc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) crc->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) crc->regs = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) if (IS_ERR(crc->regs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) dev_err(dev, "Cannot map CRC IO\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) return PTR_ERR(crc->regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) crc->clk = devm_clk_get(dev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) if (IS_ERR(crc->clk)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_err(dev, "Could not get clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) return PTR_ERR(crc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) ret = clk_prepare_enable(crc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) dev_err(crc->dev, "Failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) pm_runtime_set_autosuspend_delay(dev, CRC_AUTOSUSPEND_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) pm_runtime_use_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) pm_runtime_get_noresume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) pm_runtime_set_active(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) pm_runtime_irq_safe(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) spin_lock_init(&crc->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) platform_set_drvdata(pdev, crc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) spin_lock(&crc_list.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) list_add(&crc->list, &crc_list.dev_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) spin_unlock(&crc_list.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) mutex_lock(&refcnt_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) if (!refcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) ret = crypto_register_shashes(algs, ARRAY_SIZE(algs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) mutex_unlock(&refcnt_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_err(dev, "Failed to register\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) clk_disable_unprepare(crc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) refcnt++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) mutex_unlock(&refcnt_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_info(dev, "Initialized\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static int stm32_crc_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct stm32_crc *crc = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int ret = pm_runtime_get_sync(crc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) spin_lock(&crc_list.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) list_del(&crc->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) spin_unlock(&crc_list.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) mutex_lock(&refcnt_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) if (!--refcnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) crypto_unregister_shashes(algs, ARRAY_SIZE(algs));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) mutex_unlock(&refcnt_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) pm_runtime_disable(crc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) pm_runtime_put_noidle(crc->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) clk_disable_unprepare(crc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) static int __maybe_unused stm32_crc_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) struct stm32_crc *crc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret = pm_runtime_force_suspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) clk_unprepare(crc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int __maybe_unused stm32_crc_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct stm32_crc *crc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) ret = clk_prepare(crc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) dev_err(crc->dev, "Failed to prepare clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return pm_runtime_force_resume(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) static int __maybe_unused stm32_crc_runtime_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) struct stm32_crc *crc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) clk_disable(crc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) static int __maybe_unused stm32_crc_runtime_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) struct stm32_crc *crc = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) ret = clk_enable(crc->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) dev_err(crc->dev, "Failed to enable clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static const struct dev_pm_ops stm32_crc_pm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) SET_SYSTEM_SLEEP_PM_OPS(stm32_crc_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) stm32_crc_resume)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) SET_RUNTIME_PM_OPS(stm32_crc_runtime_suspend,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) stm32_crc_runtime_resume, NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) static const struct of_device_id stm32_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) { .compatible = "st,stm32f7-crc", },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) MODULE_DEVICE_TABLE(of, stm32_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) static struct platform_driver stm32_crc_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) .probe = stm32_crc_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) .remove = stm32_crc_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) .name = DRIVER_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) .pm = &stm32_crc_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) .of_match_table = stm32_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) module_platform_driver(stm32_crc_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) MODULE_AUTHOR("Fabien Dessenne <fabien.dessenne@st.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) MODULE_DESCRIPTION("STMicrolectronics STM32 CRC32 hardware driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) MODULE_LICENSE("GPL");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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