^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cryptographic API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Support for SAHARA cryptographic accelerator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2014 Steffen Trumtrar <s.trumtrar@pengutronix.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Copyright (c) 2013 Vista Silicon S.L.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Author: Javier Martin <javier.martin@vista-silicon.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Based on omap-aes.c and tegra-aes.c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <crypto/aes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <crypto/internal/hash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <crypto/internal/skcipher.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <crypto/scatterwalk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <crypto/sha.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/kthread.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/mutex.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SHA_BUFFER_LEN PAGE_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SAHARA_MAX_SHA_BLOCK_SIZE SHA256_BLOCK_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SAHARA_NAME "sahara"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SAHARA_VERSION_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SAHARA_VERSION_4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SAHARA_TIMEOUT_MS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SAHARA_MAX_HW_DESC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SAHARA_MAX_HW_LINK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define FLAGS_MODE_MASK 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define FLAGS_ENCRYPT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define FLAGS_CBC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define FLAGS_NEW_KEY BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SAHARA_HDR_BASE 0x00800000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SAHARA_HDR_SKHA_ALG_AES 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SAHARA_HDR_SKHA_OP_ENC (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SAHARA_HDR_SKHA_MODE_ECB (0 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SAHARA_HDR_SKHA_MODE_CBC (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SAHARA_HDR_FORM_DATA (5 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SAHARA_HDR_FORM_KEY (8 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SAHARA_HDR_LLO (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SAHARA_HDR_CHA_SKHA (1 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SAHARA_HDR_CHA_MDHA (2 << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SAHARA_HDR_PARITY_BIT (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SAHARA_HDR_MDHA_SET_MODE_MD_KEY 0x20880000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SAHARA_HDR_MDHA_SET_MODE_HASH 0x208D0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SAHARA_HDR_MDHA_HASH 0xA0850000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SAHARA_HDR_MDHA_STORE_DIGEST 0x20820000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SAHARA_HDR_MDHA_ALG_SHA1 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SAHARA_HDR_MDHA_ALG_MD5 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SAHARA_HDR_MDHA_ALG_SHA256 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SAHARA_HDR_MDHA_ALG_SHA224 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SAHARA_HDR_MDHA_PDATA (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SAHARA_HDR_MDHA_HMAC (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SAHARA_HDR_MDHA_INIT (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SAHARA_HDR_MDHA_IPAD (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SAHARA_HDR_MDHA_OPAD (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SAHARA_HDR_MDHA_SWAP (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SAHARA_HDR_MDHA_MAC_FULL (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SAHARA_HDR_MDHA_SSL (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* SAHARA can only process one request at a time */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SAHARA_QUEUE_LENGTH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SAHARA_REG_VERSION 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SAHARA_REG_DAR 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SAHARA_REG_CONTROL 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SAHARA_CONTROL_SET_THROTTLE(x) (((x) & 0xff) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SAHARA_CONTROL_SET_MAXBURST(x) (((x) & 0xff) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SAHARA_CONTROL_RNG_AUTORSD (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SAHARA_CONTROL_ENABLE_INT (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SAHARA_REG_CMD 0x0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SAHARA_CMD_RESET (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SAHARA_CMD_CLEAR_INT (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SAHARA_CMD_CLEAR_ERR (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SAHARA_CMD_SINGLE_STEP (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SAHARA_CMD_MODE_BATCH (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SAHARA_CMD_MODE_DEBUG (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SAHARA_REG_STATUS 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SAHARA_STATUS_GET_STATE(x) ((x) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SAHARA_STATE_IDLE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SAHARA_STATE_BUSY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SAHARA_STATE_ERR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SAHARA_STATE_FAULT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SAHARA_STATE_COMPLETE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SAHARA_STATE_COMP_FLAG (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SAHARA_STATUS_DAR_FULL (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SAHARA_STATUS_ERROR (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SAHARA_STATUS_SECURE (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SAHARA_STATUS_FAIL (1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SAHARA_STATUS_INIT (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SAHARA_STATUS_RNG_RESEED (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SAHARA_STATUS_ACTIVE_RNG (1 << 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SAHARA_STATUS_ACTIVE_MDHA (1 << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SAHARA_STATUS_ACTIVE_SKHA (1 << 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SAHARA_STATUS_MODE_BATCH (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SAHARA_STATUS_MODE_DEDICATED (1 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SAHARA_STATUS_MODE_DEBUG (1 << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SAHARA_STATUS_GET_ISTATE(x) (((x) >> 24) & 0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SAHARA_REG_ERRSTATUS 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SAHARA_ERRSTATUS_GET_SOURCE(x) ((x) & 0xf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SAHARA_ERRSOURCE_CHA 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SAHARA_ERRSOURCE_DMA 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SAHARA_ERRSTATUS_DMA_DIR (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SAHARA_ERRSTATUS_GET_DMASZ(x)(((x) >> 9) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SAHARA_ERRSTATUS_GET_DMASRC(x) (((x) >> 13) & 0x7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SAHARA_ERRSTATUS_GET_CHASRC(x) (((x) >> 16) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define SAHARA_ERRSTATUS_GET_CHAERR(x) (((x) >> 28) & 0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SAHARA_REG_FADDR 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define SAHARA_REG_CDAR 0x1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define SAHARA_REG_IDAR 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct sahara_hw_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 len1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 p1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 len2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 p2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct sahara_hw_link {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) u32 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) u32 p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) u32 next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct sahara_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) /* AES-specific context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) int keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) u8 key[AES_KEYSIZE_128];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) struct crypto_skcipher *fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct sahara_aes_reqctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) unsigned long mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) struct skcipher_request fallback_req; // keep at the end
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * struct sahara_sha_reqctx - private data per request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @buf: holds data for requests smaller than block_size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @rembuf: used to prepare one block_size-aligned request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @context: hw-specific context for request. Digest is extracted from this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @mode: specifies what type of hw-descriptor needs to be built
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @digest_size: length of digest for this request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @context_size: length of hw-context for this request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * Always digest_size + 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @buf_cnt: number of bytes saved in buf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @sg_in_idx: number of hw links
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * @in_sg: scatterlist for input data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @in_sg_chain: scatterlists for chained input data
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @total: total number of bytes for transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @last: is this the last block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @first: is this the first block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @active: inside a transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct sahara_sha_reqctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) u8 buf[SAHARA_MAX_SHA_BLOCK_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) u8 rembuf[SAHARA_MAX_SHA_BLOCK_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) u8 context[SHA256_DIGEST_SIZE + 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) unsigned int mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) unsigned int digest_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) unsigned int context_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) unsigned int buf_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) unsigned int sg_in_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) struct scatterlist *in_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) struct scatterlist in_sg_chain[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) size_t total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) unsigned int last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) unsigned int first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) unsigned int active;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) struct sahara_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) struct device *device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) unsigned int version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void __iomem *regs_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) struct clk *clk_ipg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) struct clk *clk_ahb;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) struct mutex queue_mutex;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) struct task_struct *kthread;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) struct completion dma_completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) struct sahara_ctx *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) struct crypto_queue queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) struct sahara_hw_desc *hw_desc[SAHARA_MAX_HW_DESC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) dma_addr_t hw_phys_desc[SAHARA_MAX_HW_DESC];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u8 *key_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) dma_addr_t key_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u8 *iv_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) dma_addr_t iv_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) u8 *context_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) dma_addr_t context_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct sahara_hw_link *hw_link[SAHARA_MAX_HW_LINK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) dma_addr_t hw_phys_link[SAHARA_MAX_HW_LINK];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) size_t total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) struct scatterlist *in_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int nb_in_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct scatterlist *out_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int nb_out_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u32 error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static struct sahara_dev *dev_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) static inline void sahara_write(struct sahara_dev *dev, u32 data, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) writel(data, dev->regs_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) static inline unsigned int sahara_read(struct sahara_dev *dev, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) return readl(dev->regs_base + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) static u32 sahara_aes_key_hdr(struct sahara_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) u32 hdr = SAHARA_HDR_BASE | SAHARA_HDR_SKHA_ALG_AES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) SAHARA_HDR_FORM_KEY | SAHARA_HDR_LLO |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) SAHARA_HDR_CHA_SKHA | SAHARA_HDR_PARITY_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) if (dev->flags & FLAGS_CBC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) hdr |= SAHARA_HDR_SKHA_MODE_CBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) hdr ^= SAHARA_HDR_PARITY_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) if (dev->flags & FLAGS_ENCRYPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) hdr |= SAHARA_HDR_SKHA_OP_ENC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) hdr ^= SAHARA_HDR_PARITY_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) return hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) static u32 sahara_aes_data_link_hdr(struct sahara_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) return SAHARA_HDR_BASE | SAHARA_HDR_FORM_DATA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) SAHARA_HDR_CHA_SKHA | SAHARA_HDR_PARITY_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static const char *sahara_err_src[16] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) "No error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) "Header error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) "Descriptor length error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) "Descriptor length or pointer error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) "Link length error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) "Link pointer error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) "Input buffer error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) "Output buffer error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) "Output buffer starvation",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) "Internal state fault",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) "General descriptor problem",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) "Descriptor address error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) "Link address error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) "CHA error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) "DMA error"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static const char *sahara_err_dmasize[4] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) "Byte transfer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) "Half-word transfer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) "Word transfer",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) static const char *sahara_err_dmasrc[8] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) "No error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) "AHB bus error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) "Internal IP bus error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) "Parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) "DMA crosses 256 byte boundary",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) "DMA is busy",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) "Reserved",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) "DMA HW error"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) static const char *sahara_cha_errsrc[12] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) "Input buffer non-empty",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) "Illegal address",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) "Illegal mode",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) "Illegal data size",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) "Illegal key size",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) "Write during processing",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) "CTX read during processing",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) "HW error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) "Input buffer disabled/underflow",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) "Output buffer disabled/overflow",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) "DES key parity error",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) "Reserved"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) static const char *sahara_cha_err[4] = { "No error", "SKHA", "MDHA", "RNG" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) static void sahara_decode_error(struct sahara_dev *dev, unsigned int error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) u8 source = SAHARA_ERRSTATUS_GET_SOURCE(error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) u16 chasrc = ffs(SAHARA_ERRSTATUS_GET_CHASRC(error));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) dev_err(dev->device, "%s: Error Register = 0x%08x\n", __func__, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) dev_err(dev->device, " - %s.\n", sahara_err_src[source]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) if (source == SAHARA_ERRSOURCE_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (error & SAHARA_ERRSTATUS_DMA_DIR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_err(dev->device, " * DMA read.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) dev_err(dev->device, " * DMA write.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) dev_err(dev->device, " * %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) sahara_err_dmasize[SAHARA_ERRSTATUS_GET_DMASZ(error)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) dev_err(dev->device, " * %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) sahara_err_dmasrc[SAHARA_ERRSTATUS_GET_DMASRC(error)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) } else if (source == SAHARA_ERRSOURCE_CHA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) dev_err(dev->device, " * %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) sahara_cha_errsrc[chasrc]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) dev_err(dev->device, " * %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) sahara_cha_err[SAHARA_ERRSTATUS_GET_CHAERR(error)]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) dev_err(dev->device, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static const char *sahara_state[4] = { "Idle", "Busy", "Error", "HW Fault" };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) static void sahara_decode_status(struct sahara_dev *dev, unsigned int status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u8 state;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) if (!__is_defined(DEBUG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) state = SAHARA_STATUS_GET_STATE(status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) dev_dbg(dev->device, "%s: Status Register = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) __func__, status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dev_dbg(dev->device, " - State = %d:\n", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) if (state & SAHARA_STATE_COMP_FLAG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) dev_dbg(dev->device, " * Descriptor completed. IRQ pending.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) dev_dbg(dev->device, " * %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) sahara_state[state & ~SAHARA_STATE_COMP_FLAG]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (status & SAHARA_STATUS_DAR_FULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) dev_dbg(dev->device, " - DAR Full.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) if (status & SAHARA_STATUS_ERROR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dev_dbg(dev->device, " - Error.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) if (status & SAHARA_STATUS_SECURE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) dev_dbg(dev->device, " - Secure.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (status & SAHARA_STATUS_FAIL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) dev_dbg(dev->device, " - Fail.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) if (status & SAHARA_STATUS_RNG_RESEED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) dev_dbg(dev->device, " - RNG Reseed Request.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (status & SAHARA_STATUS_ACTIVE_RNG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) dev_dbg(dev->device, " - RNG Active.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) if (status & SAHARA_STATUS_ACTIVE_MDHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) dev_dbg(dev->device, " - MDHA Active.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) if (status & SAHARA_STATUS_ACTIVE_SKHA)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) dev_dbg(dev->device, " - SKHA Active.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (status & SAHARA_STATUS_MODE_BATCH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) dev_dbg(dev->device, " - Batch Mode.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) else if (status & SAHARA_STATUS_MODE_DEDICATED)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) dev_dbg(dev->device, " - Dedicated Mode.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) else if (status & SAHARA_STATUS_MODE_DEBUG)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) dev_dbg(dev->device, " - Debug Mode.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) dev_dbg(dev->device, " - Internal state = 0x%02x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) SAHARA_STATUS_GET_ISTATE(status));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dev_dbg(dev->device, "Current DAR: 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) sahara_read(dev, SAHARA_REG_CDAR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) dev_dbg(dev->device, "Initial DAR: 0x%08x\n\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) sahara_read(dev, SAHARA_REG_IDAR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) static void sahara_dump_descriptors(struct sahara_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) if (!__is_defined(DEBUG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) for (i = 0; i < SAHARA_MAX_HW_DESC; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_dbg(dev->device, "Descriptor (%d) (%pad):\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) i, &dev->hw_phys_desc[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) dev_dbg(dev->device, "\thdr = 0x%08x\n", dev->hw_desc[i]->hdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_dbg(dev->device, "\tlen1 = %u\n", dev->hw_desc[i]->len1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) dev_dbg(dev->device, "\tp1 = 0x%08x\n", dev->hw_desc[i]->p1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_dbg(dev->device, "\tlen2 = %u\n", dev->hw_desc[i]->len2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) dev_dbg(dev->device, "\tp2 = 0x%08x\n", dev->hw_desc[i]->p2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) dev_dbg(dev->device, "\tnext = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) dev->hw_desc[i]->next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) dev_dbg(dev->device, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) static void sahara_dump_links(struct sahara_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) if (!__is_defined(DEBUG))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) for (i = 0; i < SAHARA_MAX_HW_LINK; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) dev_dbg(dev->device, "Link (%d) (%pad):\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) i, &dev->hw_phys_link[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) dev_dbg(dev->device, "\tlen = %u\n", dev->hw_link[i]->len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) dev_dbg(dev->device, "\tp = 0x%08x\n", dev->hw_link[i]->p);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) dev_dbg(dev->device, "\tnext = 0x%08x\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) dev->hw_link[i]->next);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_dbg(dev->device, "\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) static int sahara_hw_descriptor_create(struct sahara_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) struct sahara_ctx *ctx = dev->ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) int idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) /* Copy new key if necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) if (ctx->flags & FLAGS_NEW_KEY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) memcpy(dev->key_base, ctx->key, ctx->keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ctx->flags &= ~FLAGS_NEW_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) if (dev->flags & FLAGS_CBC) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dev->hw_desc[idx]->len1 = AES_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) dev->hw_desc[idx]->p1 = dev->iv_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) dev->hw_desc[idx]->len1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) dev->hw_desc[idx]->p1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev->hw_desc[idx]->len2 = ctx->keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) dev->hw_desc[idx]->p2 = dev->key_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) dev->hw_desc[idx]->next = dev->hw_phys_desc[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) dev->hw_desc[idx]->hdr = sahara_aes_key_hdr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dev->nb_in_sg = sg_nents_for_len(dev->in_sg, dev->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (dev->nb_in_sg < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) dev_err(dev->device, "Invalid numbers of src SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return dev->nb_in_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dev->nb_out_sg = sg_nents_for_len(dev->out_sg, dev->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) if (dev->nb_out_sg < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dev_err(dev->device, "Invalid numbers of dst SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) return dev->nb_out_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) if ((dev->nb_in_sg + dev->nb_out_sg) > SAHARA_MAX_HW_LINK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) dev_err(dev->device, "not enough hw links (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dev->nb_in_sg + dev->nb_out_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) ret = dma_map_sg(dev->device, dev->in_sg, dev->nb_in_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) if (ret != dev->nb_in_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) dev_err(dev->device, "couldn't map in sg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) goto unmap_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) ret = dma_map_sg(dev->device, dev->out_sg, dev->nb_out_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ret != dev->nb_out_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) dev_err(dev->device, "couldn't map out sg\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) goto unmap_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) /* Create input links */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) dev->hw_desc[idx]->p1 = dev->hw_phys_link[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) sg = dev->in_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) for (i = 0; i < dev->nb_in_sg; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) dev->hw_link[i]->len = sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) dev->hw_link[i]->p = sg->dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) if (i == (dev->nb_in_sg - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev->hw_link[i]->next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) dev->hw_link[i]->next = dev->hw_phys_link[i + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) sg = sg_next(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Create output links */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dev->hw_desc[idx]->p2 = dev->hw_phys_link[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) sg = dev->out_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) for (j = i; j < dev->nb_out_sg + i; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) dev->hw_link[j]->len = sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) dev->hw_link[j]->p = sg->dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (j == (dev->nb_out_sg + i - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) dev->hw_link[j]->next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev->hw_link[j]->next = dev->hw_phys_link[j + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) sg = sg_next(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) /* Fill remaining fields of hw_desc[1] */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev->hw_desc[idx]->hdr = sahara_aes_data_link_hdr(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev->hw_desc[idx]->len1 = dev->total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) dev->hw_desc[idx]->len2 = dev->total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev->hw_desc[idx]->next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) sahara_dump_descriptors(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) sahara_dump_links(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) sahara_write(dev, dev->hw_phys_desc[0], SAHARA_REG_DAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) unmap_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dma_unmap_sg(dev->device, dev->out_sg, dev->nb_out_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unmap_in:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dma_unmap_sg(dev->device, dev->in_sg, dev->nb_in_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int sahara_aes_process(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct sahara_dev *dev = dev_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct sahara_ctx *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) struct sahara_aes_reqctx *rctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /* Request is ready to be dispatched by the device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dev_dbg(dev->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) "dispatch request (nbytes=%d, src=%p, dst=%p)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) req->cryptlen, req->src, req->dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) /* assign new request to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dev->total = req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) dev->in_sg = req->src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) dev->out_sg = req->dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) rctx->mode &= FLAGS_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) dev->flags = (dev->flags & ~FLAGS_MODE_MASK) | rctx->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) if ((dev->flags & FLAGS_CBC) && req->iv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) memcpy(dev->iv_base, req->iv, AES_KEYSIZE_128);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /* assign new context to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) dev->ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) reinit_completion(&dev->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) ret = sahara_hw_descriptor_create(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) timeout = wait_for_completion_timeout(&dev->dma_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) msecs_to_jiffies(SAHARA_TIMEOUT_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dev_err(dev->device, "AES timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) dma_unmap_sg(dev->device, dev->out_sg, dev->nb_out_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) dma_unmap_sg(dev->device, dev->in_sg, dev->nb_in_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) static int sahara_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) struct sahara_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) ctx->keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) /* SAHARA only supports 128bit keys */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) if (keylen == AES_KEYSIZE_128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) ctx->flags |= FLAGS_NEW_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) if (keylen != AES_KEYSIZE_192 && keylen != AES_KEYSIZE_256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) * The requested key size is not supported by HW, do a fallback.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) crypto_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) crypto_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) CRYPTO_TFM_REQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return crypto_skcipher_setkey(ctx->fallback, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static int sahara_aes_crypt(struct skcipher_request *req, unsigned long mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) struct sahara_dev *dev = dev_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) dev_dbg(dev->device, "nbytes: %d, enc: %d, cbc: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) req->cryptlen, !!(mode & FLAGS_ENCRYPT), !!(mode & FLAGS_CBC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) if (!IS_ALIGNED(req->cryptlen, AES_BLOCK_SIZE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) dev_err(dev->device,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) "request size is not exact amount of AES blocks\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) rctx->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) mutex_lock(&dev->queue_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) err = crypto_enqueue_request(&dev->queue, &req->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) mutex_unlock(&dev->queue_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) wake_up_process(dev->kthread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) static int sahara_aes_ecb_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) struct sahara_ctx *ctx = crypto_skcipher_ctx(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) if (unlikely(ctx->keylen != AES_KEYSIZE_128)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) skcipher_request_set_callback(&rctx->fallback_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) req->base.flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) req->base.complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) req->base.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) skcipher_request_set_crypt(&rctx->fallback_req, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) req->dst, req->cryptlen, req->iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return crypto_skcipher_encrypt(&rctx->fallback_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) return sahara_aes_crypt(req, FLAGS_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) static int sahara_aes_ecb_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) struct sahara_ctx *ctx = crypto_skcipher_ctx(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) if (unlikely(ctx->keylen != AES_KEYSIZE_128)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) skcipher_request_set_callback(&rctx->fallback_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) req->base.flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) req->base.complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) req->base.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) skcipher_request_set_crypt(&rctx->fallback_req, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) req->dst, req->cryptlen, req->iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) return crypto_skcipher_decrypt(&rctx->fallback_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return sahara_aes_crypt(req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int sahara_aes_cbc_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct sahara_ctx *ctx = crypto_skcipher_ctx(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) if (unlikely(ctx->keylen != AES_KEYSIZE_128)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) skcipher_request_set_callback(&rctx->fallback_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) req->base.flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) req->base.complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) req->base.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) skcipher_request_set_crypt(&rctx->fallback_req, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) req->dst, req->cryptlen, req->iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) return crypto_skcipher_encrypt(&rctx->fallback_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return sahara_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int sahara_aes_cbc_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct sahara_aes_reqctx *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) struct sahara_ctx *ctx = crypto_skcipher_ctx(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) if (unlikely(ctx->keylen != AES_KEYSIZE_128)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) skcipher_request_set_callback(&rctx->fallback_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) req->base.flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) req->base.complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) req->base.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) skcipher_request_set_crypt(&rctx->fallback_req, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) req->dst, req->cryptlen, req->iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return crypto_skcipher_decrypt(&rctx->fallback_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return sahara_aes_crypt(req, FLAGS_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static int sahara_aes_init_tfm(struct crypto_skcipher *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) const char *name = crypto_tfm_alg_name(&tfm->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) struct sahara_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ctx->fallback = crypto_alloc_skcipher(name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) CRYPTO_ALG_NEED_FALLBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) if (IS_ERR(ctx->fallback)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) pr_err("Error allocating fallback algo %s\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) return PTR_ERR(ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) crypto_skcipher_set_reqsize(tfm, sizeof(struct sahara_aes_reqctx) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) crypto_skcipher_reqsize(ctx->fallback));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) static void sahara_aes_exit_tfm(struct crypto_skcipher *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct sahara_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) crypto_free_skcipher(ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static u32 sahara_sha_init_hdr(struct sahara_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) struct sahara_sha_reqctx *rctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) u32 hdr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) hdr = rctx->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (rctx->first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) hdr |= SAHARA_HDR_MDHA_SET_MODE_HASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) hdr |= SAHARA_HDR_MDHA_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) hdr |= SAHARA_HDR_MDHA_SET_MODE_MD_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (rctx->last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) hdr |= SAHARA_HDR_MDHA_PDATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (hweight_long(hdr) % 2 == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) hdr |= SAHARA_HDR_PARITY_BIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return hdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) static int sahara_sha_hw_links_create(struct sahara_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) struct sahara_sha_reqctx *rctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) int start)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) dev->in_sg = rctx->in_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) dev->nb_in_sg = sg_nents_for_len(dev->in_sg, rctx->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) if (dev->nb_in_sg < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) dev_err(dev->device, "Invalid numbers of src SG.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) return dev->nb_in_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if ((dev->nb_in_sg) > SAHARA_MAX_HW_LINK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) dev_err(dev->device, "not enough hw links (%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) dev->nb_in_sg + dev->nb_out_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) sg = dev->in_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) ret = dma_map_sg(dev->device, dev->in_sg, dev->nb_in_sg, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) for (i = start; i < dev->nb_in_sg + start; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) dev->hw_link[i]->len = sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) dev->hw_link[i]->p = sg->dma_address;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (i == (dev->nb_in_sg + start - 1)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) dev->hw_link[i]->next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) dev->hw_link[i]->next = dev->hw_phys_link[i + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) sg = sg_next(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) static int sahara_sha_hw_data_descriptor_create(struct sahara_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) struct sahara_sha_reqctx *rctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct ahash_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) unsigned result_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) int i = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) if (rctx->first)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* Create initial descriptor: #8*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) dev->hw_desc[index]->hdr = sahara_sha_init_hdr(dev, rctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /* Create hash descriptor: #10. Must follow #6. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) dev->hw_desc[index]->hdr = SAHARA_HDR_MDHA_HASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) dev->hw_desc[index]->len1 = rctx->total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) if (dev->hw_desc[index]->len1 == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) /* if len1 is 0, p1 must be 0, too */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) dev->hw_desc[index]->p1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) rctx->sg_in_idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) /* Create input links */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) dev->hw_desc[index]->p1 = dev->hw_phys_link[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) i = sahara_sha_hw_links_create(dev, rctx, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) rctx->sg_in_idx = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) if (i < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) dev->hw_desc[index]->p2 = dev->hw_phys_link[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) /* Save the context for the next operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) result_len = rctx->context_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) dev->hw_link[i]->p = dev->context_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dev->hw_link[i]->len = result_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) dev->hw_desc[index]->len2 = result_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dev->hw_link[i]->next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * Load descriptor aka #6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) * To load a previously saved context back to the MDHA unit
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) * p1: Saved Context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) * p2: NULL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) static int sahara_sha_hw_context_descriptor_create(struct sahara_dev *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct sahara_sha_reqctx *rctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct ahash_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) int index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) dev->hw_desc[index]->hdr = sahara_sha_init_hdr(dev, rctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) dev->hw_desc[index]->len1 = rctx->context_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) dev->hw_desc[index]->p1 = dev->hw_phys_link[index];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dev->hw_desc[index]->len2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) dev->hw_desc[index]->p2 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dev->hw_link[index]->len = rctx->context_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dev->hw_link[index]->p = dev->context_phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) dev->hw_link[index]->next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) static int sahara_walk_and_recalc(struct scatterlist *sg, unsigned int nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) if (!sg || !sg->length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) return nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) while (nbytes && sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) if (nbytes <= sg->length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) sg->length = nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) sg_mark_end(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) nbytes -= sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) sg = sg_next(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) return nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) static int sahara_sha_prepare_request(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) struct sahara_sha_reqctx *rctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) unsigned int hash_later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) unsigned int block_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) block_size = crypto_tfm_alg_blocksize(crypto_ahash_tfm(tfm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) /* append bytes from previous operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) len = rctx->buf_cnt + req->nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /* only the last transfer can be padded in hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) if (!rctx->last && (len < block_size)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /* to few data, save for next operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) scatterwalk_map_and_copy(rctx->buf + rctx->buf_cnt, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) 0, req->nbytes, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) rctx->buf_cnt += req->nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* add data from previous operation first */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) if (rctx->buf_cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) memcpy(rctx->rembuf, rctx->buf, rctx->buf_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) /* data must always be a multiple of block_size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) hash_later = rctx->last ? 0 : len & (block_size - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) if (hash_later) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) unsigned int offset = req->nbytes - hash_later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) /* Save remaining bytes for later use */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) scatterwalk_map_and_copy(rctx->buf, req->src, offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) hash_later, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) /* nbytes should now be multiple of blocksize */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) req->nbytes = req->nbytes - hash_later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) sahara_walk_and_recalc(req->src, req->nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* have data from previous operation and current */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (rctx->buf_cnt && req->nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) sg_init_table(rctx->in_sg_chain, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) sg_set_buf(rctx->in_sg_chain, rctx->rembuf, rctx->buf_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) sg_chain(rctx->in_sg_chain, 2, req->src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) rctx->total = req->nbytes + rctx->buf_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) rctx->in_sg = rctx->in_sg_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) req->src = rctx->in_sg_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) /* only data from previous operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) } else if (rctx->buf_cnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) if (req->src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) rctx->in_sg = req->src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) rctx->in_sg = rctx->in_sg_chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) /* buf was copied into rembuf above */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) sg_init_one(rctx->in_sg, rctx->rembuf, rctx->buf_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) rctx->total = rctx->buf_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) /* no data from previous operation */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) rctx->in_sg = req->src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) rctx->total = req->nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) req->src = rctx->in_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) /* on next call, we only have the remaining data in the buffer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) rctx->buf_cnt = hash_later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static int sahara_sha_process(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) struct sahara_dev *dev = dev_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) struct sahara_sha_reqctx *rctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) unsigned long timeout;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) ret = sahara_sha_prepare_request(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) if (rctx->first) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) sahara_sha_hw_data_descriptor_create(dev, rctx, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) dev->hw_desc[0]->next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) rctx->first = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) memcpy(dev->context_base, rctx->context, rctx->context_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) sahara_sha_hw_context_descriptor_create(dev, rctx, req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) dev->hw_desc[0]->next = dev->hw_phys_desc[1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) sahara_sha_hw_data_descriptor_create(dev, rctx, req, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dev->hw_desc[1]->next = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) sahara_dump_descriptors(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) sahara_dump_links(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) reinit_completion(&dev->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) sahara_write(dev, dev->hw_phys_desc[0], SAHARA_REG_DAR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) timeout = wait_for_completion_timeout(&dev->dma_completion,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) msecs_to_jiffies(SAHARA_TIMEOUT_MS));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) if (!timeout) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) dev_err(dev->device, "SHA timeout\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (rctx->sg_in_idx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dma_unmap_sg(dev->device, dev->in_sg, dev->nb_in_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) memcpy(rctx->context, dev->context_base, rctx->context_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) if (req->result)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) memcpy(req->result, rctx->context, rctx->digest_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) static int sahara_queue_manage(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) struct sahara_dev *dev = (struct sahara_dev *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) struct crypto_async_request *async_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) struct crypto_async_request *backlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) __set_current_state(TASK_INTERRUPTIBLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) mutex_lock(&dev->queue_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) backlog = crypto_get_backlog(&dev->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) async_req = crypto_dequeue_request(&dev->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) mutex_unlock(&dev->queue_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (backlog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) backlog->complete(backlog, -EINPROGRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) if (async_req) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) if (crypto_tfm_alg_type(async_req->tfm) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) CRYPTO_ALG_TYPE_AHASH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct ahash_request *req =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) ahash_request_cast(async_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ret = sahara_sha_process(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) struct skcipher_request *req =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) skcipher_request_cast(async_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) ret = sahara_aes_process(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) async_req->complete(async_req, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) schedule();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) } while (!kthread_should_stop());
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) static int sahara_sha_enqueue(struct ahash_request *req, int last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) struct sahara_sha_reqctx *rctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) struct sahara_dev *dev = dev_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) if (!req->nbytes && !last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) rctx->last = last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) if (!rctx->active) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) rctx->active = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) rctx->first = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) mutex_lock(&dev->queue_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) ret = crypto_enqueue_request(&dev->queue, &req->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) mutex_unlock(&dev->queue_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) wake_up_process(dev->kthread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) static int sahara_sha_init(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct sahara_sha_reqctx *rctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) memset(rctx, 0, sizeof(*rctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) switch (crypto_ahash_digestsize(tfm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) case SHA1_DIGEST_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) rctx->mode |= SAHARA_HDR_MDHA_ALG_SHA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) rctx->digest_size = SHA1_DIGEST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) case SHA256_DIGEST_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) rctx->mode |= SAHARA_HDR_MDHA_ALG_SHA256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) rctx->digest_size = SHA256_DIGEST_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) rctx->context_size = rctx->digest_size + 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) rctx->active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) static int sahara_sha_update(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return sahara_sha_enqueue(req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) static int sahara_sha_final(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) req->nbytes = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return sahara_sha_enqueue(req, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static int sahara_sha_finup(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) return sahara_sha_enqueue(req, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) static int sahara_sha_digest(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) sahara_sha_init(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return sahara_sha_finup(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) static int sahara_sha_export(struct ahash_request *req, void *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) struct sahara_sha_reqctx *rctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) memcpy(out, rctx, sizeof(struct sahara_sha_reqctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) static int sahara_sha_import(struct ahash_request *req, const void *in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) struct sahara_sha_reqctx *rctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) memcpy(rctx, in, sizeof(struct sahara_sha_reqctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) static int sahara_sha_cra_init(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) sizeof(struct sahara_sha_reqctx) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) SHA_BUFFER_LEN + SHA256_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) static struct skcipher_alg aes_algs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) .base.cra_name = "ecb(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) .base.cra_driver_name = "sahara-ecb-aes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) .base.cra_priority = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) .base.cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) .base.cra_ctxsize = sizeof(struct sahara_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) .base.cra_alignmask = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) .init = sahara_aes_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) .exit = sahara_aes_exit_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) .min_keysize = AES_MIN_KEY_SIZE ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) .setkey = sahara_aes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) .encrypt = sahara_aes_ecb_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) .decrypt = sahara_aes_ecb_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) }, {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) .base.cra_name = "cbc(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) .base.cra_driver_name = "sahara-cbc-aes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) .base.cra_priority = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) .base.cra_flags = CRYPTO_ALG_ASYNC | CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) .base.cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) .base.cra_ctxsize = sizeof(struct sahara_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) .base.cra_alignmask = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) .init = sahara_aes_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) .exit = sahara_aes_exit_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) .min_keysize = AES_MIN_KEY_SIZE ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) .setkey = sahara_aes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) .encrypt = sahara_aes_cbc_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) .decrypt = sahara_aes_cbc_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) static struct ahash_alg sha_v3_algs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) .init = sahara_sha_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) .update = sahara_sha_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) .final = sahara_sha_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) .finup = sahara_sha_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) .digest = sahara_sha_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) .export = sahara_sha_export,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) .import = sahara_sha_import,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) .halg.digestsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) .halg.statesize = sizeof(struct sahara_sha_reqctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) .cra_name = "sha1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) .cra_driver_name = "sahara-sha1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) .cra_priority = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) .cra_blocksize = SHA1_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) .cra_ctxsize = sizeof(struct sahara_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) .cra_alignmask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) .cra_init = sahara_sha_cra_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) static struct ahash_alg sha_v4_algs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) .init = sahara_sha_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) .update = sahara_sha_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) .final = sahara_sha_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) .finup = sahara_sha_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) .digest = sahara_sha_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) .export = sahara_sha_export,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) .import = sahara_sha_import,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) .halg.digestsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) .halg.statesize = sizeof(struct sahara_sha_reqctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) .cra_name = "sha256",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) .cra_driver_name = "sahara-sha256",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) .cra_priority = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) .cra_blocksize = SHA256_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) .cra_ctxsize = sizeof(struct sahara_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) .cra_alignmask = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) .cra_init = sahara_sha_cra_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) static irqreturn_t sahara_irq_handler(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) struct sahara_dev *dev = (struct sahara_dev *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) unsigned int stat = sahara_read(dev, SAHARA_REG_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) unsigned int err = sahara_read(dev, SAHARA_REG_ERRSTATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) sahara_write(dev, SAHARA_CMD_CLEAR_INT | SAHARA_CMD_CLEAR_ERR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) SAHARA_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) sahara_decode_status(dev, stat);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) if (SAHARA_STATUS_GET_STATE(stat) == SAHARA_STATE_BUSY) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) } else if (SAHARA_STATUS_GET_STATE(stat) == SAHARA_STATE_COMPLETE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) dev->error = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) sahara_decode_error(dev, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) dev->error = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) complete(&dev->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) static int sahara_register_algs(struct sahara_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) unsigned int i, j, k, l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) for (i = 0; i < ARRAY_SIZE(aes_algs); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) err = crypto_register_skcipher(&aes_algs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) goto err_aes_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) for (k = 0; k < ARRAY_SIZE(sha_v3_algs); k++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) err = crypto_register_ahash(&sha_v3_algs[k]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) goto err_sha_v3_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) if (dev->version > SAHARA_VERSION_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) for (l = 0; l < ARRAY_SIZE(sha_v4_algs); l++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) err = crypto_register_ahash(&sha_v4_algs[l]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) goto err_sha_v4_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) err_sha_v4_algs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) for (j = 0; j < l; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) crypto_unregister_ahash(&sha_v4_algs[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) err_sha_v3_algs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) for (j = 0; j < k; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) crypto_unregister_ahash(&sha_v3_algs[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) err_aes_algs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) for (j = 0; j < i; j++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) crypto_unregister_skcipher(&aes_algs[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) static void sahara_unregister_algs(struct sahara_dev *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) unsigned int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) for (i = 0; i < ARRAY_SIZE(aes_algs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) crypto_unregister_skcipher(&aes_algs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) for (i = 0; i < ARRAY_SIZE(sha_v3_algs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) crypto_unregister_ahash(&sha_v3_algs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) if (dev->version > SAHARA_VERSION_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) for (i = 0; i < ARRAY_SIZE(sha_v4_algs); i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) crypto_unregister_ahash(&sha_v4_algs[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) static const struct platform_device_id sahara_platform_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) { .name = "sahara-imx27" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) MODULE_DEVICE_TABLE(platform, sahara_platform_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) static const struct of_device_id sahara_dt_ids[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) { .compatible = "fsl,imx53-sahara" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) { .compatible = "fsl,imx27-sahara" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) MODULE_DEVICE_TABLE(of, sahara_dt_ids);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) static int sahara_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) struct sahara_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) u32 version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) dev = devm_kzalloc(&pdev->dev, sizeof(*dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) if (!dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) dev->device = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) platform_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) /* Get the base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) dev->regs_base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) if (IS_ERR(dev->regs_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) return PTR_ERR(dev->regs_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) /* Get the IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) if (irq < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) return irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) err = devm_request_irq(&pdev->dev, irq, sahara_irq_handler,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) 0, dev_name(&pdev->dev), dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) dev_err(&pdev->dev, "failed to request irq\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) /* clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) dev->clk_ipg = devm_clk_get(&pdev->dev, "ipg");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) if (IS_ERR(dev->clk_ipg)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) dev_err(&pdev->dev, "Could not get ipg clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return PTR_ERR(dev->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) dev->clk_ahb = devm_clk_get(&pdev->dev, "ahb");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) if (IS_ERR(dev->clk_ahb)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dev_err(&pdev->dev, "Could not get ahb clock\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) return PTR_ERR(dev->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) /* Allocate HW descriptors */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) dev->hw_desc[0] = dmam_alloc_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) SAHARA_MAX_HW_DESC * sizeof(struct sahara_hw_desc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) &dev->hw_phys_desc[0], GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) if (!dev->hw_desc[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415) dev_err(&pdev->dev, "Could not allocate hw descriptors\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) dev->hw_desc[1] = dev->hw_desc[0] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) dev->hw_phys_desc[1] = dev->hw_phys_desc[0] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) sizeof(struct sahara_hw_desc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) /* Allocate space for iv and key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) dev->key_base = dmam_alloc_coherent(&pdev->dev, 2 * AES_KEYSIZE_128,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) &dev->key_phys_base, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) if (!dev->key_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) dev_err(&pdev->dev, "Could not allocate memory for key\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) dev->iv_base = dev->key_base + AES_KEYSIZE_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) dev->iv_phys_base = dev->key_phys_base + AES_KEYSIZE_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) /* Allocate space for context: largest digest + message length field */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) dev->context_base = dmam_alloc_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) SHA256_DIGEST_SIZE + 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435) &dev->context_phys_base, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (!dev->context_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) dev_err(&pdev->dev, "Could not allocate memory for MDHA context\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) /* Allocate space for HW links */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) dev->hw_link[0] = dmam_alloc_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) SAHARA_MAX_HW_LINK * sizeof(struct sahara_hw_link),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) &dev->hw_phys_link[0], GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) if (!dev->hw_link[0]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) dev_err(&pdev->dev, "Could not allocate hw links\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) for (i = 1; i < SAHARA_MAX_HW_LINK; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) dev->hw_phys_link[i] = dev->hw_phys_link[i - 1] +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) sizeof(struct sahara_hw_link);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) dev->hw_link[i] = dev->hw_link[i - 1] + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) crypto_init_queue(&dev->queue, SAHARA_QUEUE_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) mutex_init(&dev->queue_mutex);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) dev_ptr = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) dev->kthread = kthread_run(sahara_queue_manage, dev, "sahara_crypto");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) if (IS_ERR(dev->kthread)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) return PTR_ERR(dev->kthread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) init_completion(&dev->dma_completion);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) err = clk_prepare_enable(dev->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) err = clk_prepare_enable(dev->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) goto clk_ipg_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) version = sahara_read(dev, SAHARA_REG_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) if (of_device_is_compatible(pdev->dev.of_node, "fsl,imx27-sahara")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) if (version != SAHARA_VERSION_3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) } else if (of_device_is_compatible(pdev->dev.of_node,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) "fsl,imx53-sahara")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) if (((version >> 8) & 0xff) != SAHARA_VERSION_4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) version = (version >> 8) & 0xff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) if (err == -ENODEV) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) dev_err(&pdev->dev, "SAHARA version %d not supported\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) goto err_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) dev->version = version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) sahara_write(dev, SAHARA_CMD_RESET | SAHARA_CMD_MODE_BATCH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) SAHARA_REG_CMD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) sahara_write(dev, SAHARA_CONTROL_SET_THROTTLE(0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) SAHARA_CONTROL_SET_MAXBURST(8) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) SAHARA_CONTROL_RNG_AUTORSD |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) SAHARA_CONTROL_ENABLE_INT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) SAHARA_REG_CONTROL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) err = sahara_register_algs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) goto err_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) dev_info(&pdev->dev, "SAHARA version %d initialized\n", version);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) err_algs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) kthread_stop(dev->kthread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) dev_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) clk_disable_unprepare(dev->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) clk_ipg_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) clk_disable_unprepare(dev->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) static int sahara_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) struct sahara_dev *dev = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) kthread_stop(dev->kthread);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) sahara_unregister_algs(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) clk_disable_unprepare(dev->clk_ipg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) clk_disable_unprepare(dev->clk_ahb);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) dev_ptr = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static struct platform_driver sahara_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) .probe = sahara_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) .remove = sahara_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .name = SAHARA_NAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .of_match_table = sahara_dt_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .id_table = sahara_platform_ids,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) module_platform_driver(sahara_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) MODULE_AUTHOR("Javier Martin <javier.martin@vista-silicon.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) MODULE_AUTHOR("Steffen Trumtrar <s.trumtrar@pengutronix.de>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) MODULE_DESCRIPTION("SAHARA2 HW crypto accelerator");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags