^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) // Copyright (c) 2017-18 Linaro Limited
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) // Based on msm-rng.c and downstream driver
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <crypto/internal/rng.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/crypto.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/iopoll.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) /* Device specific register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PRNG_DATA_OUT 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define PRNG_STATUS 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PRNG_LFSR_CFG 0x0100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PRNG_CONFIG 0x0104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* Device specific register masks and config values */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PRNG_LFSR_CFG_MASK 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PRNG_LFSR_CFG_CLOCKS 0x0000dddd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PRNG_CONFIG_HW_ENABLE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PRNG_STATUS_DATA_AVAIL BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define WORD_SZ 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct qcom_rng {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) struct mutex lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) unsigned int skip_init;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) struct qcom_rng_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) struct qcom_rng *rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) static struct qcom_rng *qcom_rng_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static int qcom_rng_read(struct qcom_rng *rng, u8 *data, unsigned int max)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) unsigned int currsize = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* read random data from hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) ret = readl_poll_timeout(rng->base + PRNG_STATUS, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) val & PRNG_STATUS_DATA_AVAIL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) 200, 10000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) val = readl_relaxed(rng->base + PRNG_DATA_OUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) if (!val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) if ((max - currsize) >= WORD_SZ) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) memcpy(data, &val, WORD_SZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) data += WORD_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) currsize += WORD_SZ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) /* copy only remaining bytes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) memcpy(data, &val, max - currsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) } while (currsize < max);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) static int qcom_rng_generate(struct crypto_rng *tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) const u8 *src, unsigned int slen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) u8 *dstn, unsigned int dlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) struct qcom_rng_ctx *ctx = crypto_rng_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) struct qcom_rng *rng = ctx->rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) ret = clk_prepare_enable(rng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) mutex_lock(&rng->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) ret = qcom_rng_read(rng, dstn, dlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) mutex_unlock(&rng->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) clk_disable_unprepare(rng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) static int qcom_rng_seed(struct crypto_rng *tfm, const u8 *seed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) unsigned int slen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) static int qcom_rng_enable(struct qcom_rng *rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) ret = clk_prepare_enable(rng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* Enable PRNG only if it is not already enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) val = readl_relaxed(rng->base + PRNG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) if (val & PRNG_CONFIG_HW_ENABLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) goto already_enabled;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) val = readl_relaxed(rng->base + PRNG_LFSR_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) val &= ~PRNG_LFSR_CFG_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) val |= PRNG_LFSR_CFG_CLOCKS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) writel(val, rng->base + PRNG_LFSR_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) val = readl_relaxed(rng->base + PRNG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) val |= PRNG_CONFIG_HW_ENABLE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel(val, rng->base + PRNG_CONFIG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) already_enabled:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) clk_disable_unprepare(rng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) static int qcom_rng_init(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct qcom_rng_ctx *ctx = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) ctx->rng = qcom_rng_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) if (!ctx->rng->skip_init)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) return qcom_rng_enable(ctx->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) static struct rng_alg qcom_rng_alg = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) .generate = qcom_rng_generate,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) .seed = qcom_rng_seed,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) .seedsize = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) .cra_name = "stdrng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) .cra_driver_name = "qcom-rng",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) .cra_flags = CRYPTO_ALG_TYPE_RNG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) .cra_priority = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) .cra_ctxsize = sizeof(struct qcom_rng_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) .cra_init = qcom_rng_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) static int qcom_rng_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct qcom_rng *rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) rng = devm_kzalloc(&pdev->dev, sizeof(*rng), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) if (!rng)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) platform_set_drvdata(pdev, rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) mutex_init(&rng->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) rng->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (IS_ERR(rng->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) return PTR_ERR(rng->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* ACPI systems have clk already on, so skip clk_get */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!has_acpi_companion(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) rng->clk = devm_clk_get(&pdev->dev, "core");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (IS_ERR(rng->clk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) return PTR_ERR(rng->clk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) rng->skip_init = (unsigned long)device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) qcom_rng_dev = rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) ret = crypto_register_rng(&qcom_rng_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) dev_err(&pdev->dev, "Register crypto rng failed: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) qcom_rng_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) static int qcom_rng_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) crypto_unregister_rng(&qcom_rng_alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) qcom_rng_dev = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #if IS_ENABLED(CONFIG_ACPI)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static const struct acpi_device_id qcom_rng_acpi_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) { .id = "QCOM8160", .driver_data = 1 },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) MODULE_DEVICE_TABLE(acpi, qcom_rng_acpi_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) static const struct of_device_id qcom_rng_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) { .compatible = "qcom,prng", .data = (void *)0},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) { .compatible = "qcom,prng-ee", .data = (void *)1},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) {}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) MODULE_DEVICE_TABLE(of, qcom_rng_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) static struct platform_driver qcom_rng_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) .probe = qcom_rng_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) .remove = qcom_rng_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) .name = KBUILD_MODNAME,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) .of_match_table = of_match_ptr(qcom_rng_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) .acpi_match_table = ACPI_PTR(qcom_rng_acpi_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) module_platform_driver(qcom_rng_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) MODULE_ALIAS("platform:" KBUILD_MODNAME);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) MODULE_DESCRIPTION("Qualcomm random number generator driver");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) MODULE_LICENSE("GPL v2");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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