Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2012-2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _REGS_V5_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _REGS_V5_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #include <linux/bitops.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define REG_VERSION			0x000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define REG_STATUS			0x100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define REG_STATUS2			0x104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define REG_ENGINES_AVAIL		0x108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define REG_FIFO_SIZES			0x10c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define REG_SEG_SIZE			0x110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define REG_GOPROC			0x120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define REG_ENCR_SEG_CFG		0x200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define REG_ENCR_SEG_SIZE		0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define REG_ENCR_SEG_START		0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define REG_CNTR0_IV0			0x20c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define REG_CNTR1_IV1			0x210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define REG_CNTR2_IV2			0x214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define REG_CNTR3_IV3			0x218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define REG_CNTR_MASK			0x21C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define REG_ENCR_CCM_INT_CNTR0		0x220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define REG_ENCR_CCM_INT_CNTR1		0x224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define REG_ENCR_CCM_INT_CNTR2		0x228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define REG_ENCR_CCM_INT_CNTR3		0x22c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define REG_ENCR_XTS_DU_SIZE		0x230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define REG_CNTR_MASK2			0x234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define REG_CNTR_MASK1			0x238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define REG_CNTR_MASK0			0x23c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define REG_AUTH_SEG_CFG		0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define REG_AUTH_SEG_SIZE		0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define REG_AUTH_SEG_START		0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define REG_AUTH_IV0			0x310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define REG_AUTH_IV1			0x314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define REG_AUTH_IV2			0x318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define REG_AUTH_IV3			0x31c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define REG_AUTH_IV4			0x320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define REG_AUTH_IV5			0x324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define REG_AUTH_IV6			0x328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define REG_AUTH_IV7			0x32c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define REG_AUTH_IV8			0x330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define REG_AUTH_IV9			0x334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define REG_AUTH_IV10			0x338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define REG_AUTH_IV11			0x33c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define REG_AUTH_IV12			0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define REG_AUTH_IV13			0x344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define REG_AUTH_IV14			0x348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define REG_AUTH_IV15			0x34c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define REG_AUTH_INFO_NONCE0		0x350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define REG_AUTH_INFO_NONCE1		0x354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define REG_AUTH_INFO_NONCE2		0x358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define REG_AUTH_INFO_NONCE3		0x35c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define REG_AUTH_BYTECNT0		0x390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define REG_AUTH_BYTECNT1		0x394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define REG_AUTH_BYTECNT2		0x398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define REG_AUTH_BYTECNT3		0x39c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define REG_AUTH_EXP_MAC0		0x3a0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define REG_AUTH_EXP_MAC1		0x3a4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define REG_AUTH_EXP_MAC2		0x3a8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define REG_AUTH_EXP_MAC3		0x3ac
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define REG_AUTH_EXP_MAC4		0x3b0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define REG_AUTH_EXP_MAC5		0x3b4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define REG_AUTH_EXP_MAC6		0x3b8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define REG_AUTH_EXP_MAC7		0x3bc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define REG_CONFIG			0x400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define REG_GOPROC_QC_KEY		0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define REG_GOPROC_OEM_KEY		0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define REG_ENCR_KEY0			0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define REG_ENCR_KEY1			0x3004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define REG_ENCR_KEY2			0x3008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define REG_ENCR_KEY3			0x300c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define REG_ENCR_KEY4			0x3010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define REG_ENCR_KEY5			0x3014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define REG_ENCR_KEY6			0x3018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define REG_ENCR_KEY7			0x301c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define REG_ENCR_XTS_KEY0		0x3020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define REG_ENCR_XTS_KEY1		0x3024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define REG_ENCR_XTS_KEY2		0x3028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define REG_ENCR_XTS_KEY3		0x302c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define REG_ENCR_XTS_KEY4		0x3030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define REG_ENCR_XTS_KEY5		0x3034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define REG_ENCR_XTS_KEY6		0x3038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define REG_ENCR_XTS_KEY7		0x303c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define REG_AUTH_KEY0			0x3040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define REG_AUTH_KEY1			0x3044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define REG_AUTH_KEY2			0x3048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define REG_AUTH_KEY3			0x304c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define REG_AUTH_KEY4			0x3050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define REG_AUTH_KEY5			0x3054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define REG_AUTH_KEY6			0x3058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define REG_AUTH_KEY7			0x305c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define REG_AUTH_KEY8			0x3060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define REG_AUTH_KEY9			0x3064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define REG_AUTH_KEY10			0x3068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define REG_AUTH_KEY11			0x306c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define REG_AUTH_KEY12			0x3070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define REG_AUTH_KEY13			0x3074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define REG_AUTH_KEY14			0x3078
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define REG_AUTH_KEY15			0x307c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* Register bits - REG_VERSION */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CORE_STEP_REV_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CORE_STEP_REV_MASK		GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CORE_MINOR_REV_SHIFT		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CORE_MINOR_REV_MASK		GENMASK(23, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CORE_MAJOR_REV_SHIFT		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CORE_MAJOR_REV_MASK		GENMASK(31, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* Register bits - REG_STATUS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define MAC_FAILED_SHIFT		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define DOUT_SIZE_AVAIL_SHIFT		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define DOUT_SIZE_AVAIL_MASK		GENMASK(30, 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define DIN_SIZE_AVAIL_SHIFT		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define DIN_SIZE_AVAIL_MASK		GENMASK(25, 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HSD_ERR_SHIFT			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ACCESS_VIOL_SHIFT		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PIPE_ACTIVE_ERR_SHIFT		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CFG_CHNG_ERR_SHIFT		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define DOUT_ERR_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define DIN_ERR_SHIFT			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define AXI_ERR_SHIFT			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CRYPTO_STATE_SHIFT		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CRYPTO_STATE_MASK		GENMASK(13, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ENCR_BUSY_SHIFT			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define AUTH_BUSY_SHIFT			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define DOUT_INTR_SHIFT			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define DIN_INTR_SHIFT			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OP_DONE_INTR_SHIFT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ERR_INTR_SHIFT			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define DOUT_RDY_SHIFT			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define DIN_RDY_SHIFT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define OPERATION_DONE_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define SW_ERR_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* Register bits - REG_STATUS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AXI_EXTRA_SHIFT			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define LOCKED_SHIFT			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* Register bits - REG_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define REQ_SIZE_SHIFT			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define REQ_SIZE_MASK			GENMASK(20, 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define REQ_SIZE_ENUM_1_BEAT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define REQ_SIZE_ENUM_2_BEAT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define REQ_SIZE_ENUM_3_BEAT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define REQ_SIZE_ENUM_4_BEAT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define REQ_SIZE_ENUM_5_BEAT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define REQ_SIZE_ENUM_6_BEAT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define REQ_SIZE_ENUM_7_BEAT		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define REQ_SIZE_ENUM_8_BEAT		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define REQ_SIZE_ENUM_9_BEAT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define REQ_SIZE_ENUM_10_BEAT		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define REQ_SIZE_ENUM_11_BEAT		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define REQ_SIZE_ENUM_12_BEAT		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define REQ_SIZE_ENUM_13_BEAT		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define REQ_SIZE_ENUM_14_BEAT		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define REQ_SIZE_ENUM_15_BEAT		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define REQ_SIZE_ENUM_16_BEAT		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define MAX_QUEUED_REQ_SHIFT		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define MAX_QUEUED_REQ_MASK		GENMASK(24, 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ENUM_1_QUEUED_REQS		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ENUM_2_QUEUED_REQS		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ENUM_3_QUEUED_REQS		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IRQ_ENABLES_SHIFT		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IRQ_ENABLES_MASK		GENMASK(13, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define LITTLE_ENDIAN_MODE_SHIFT	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PIPE_SET_SELECT_SHIFT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PIPE_SET_SELECT_MASK		GENMASK(8, 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define HIGH_SPD_EN_N_SHIFT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define MASK_DOUT_INTR_SHIFT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define MASK_DIN_INTR_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define MASK_OP_DONE_INTR_SHIFT		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define MASK_ERR_INTR_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* Register bits - REG_AUTH_SEG_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define COMP_EXP_MAC_SHIFT		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define COMP_EXP_MAC_DISABLED		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define COMP_EXP_MAC_ENABLED		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define F9_DIRECTION_SHIFT		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define F9_DIRECTION_UPLINK		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define F9_DIRECTION_DOWNLINK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define AUTH_NONCE_NUM_WORDS_SHIFT	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define AUTH_NONCE_NUM_WORDS_MASK	GENMASK(22, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define USE_PIPE_KEY_AUTH_SHIFT		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define USE_HW_KEY_AUTH_SHIFT		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define AUTH_FIRST_SHIFT		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define AUTH_LAST_SHIFT			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define AUTH_POS_SHIFT			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define AUTH_POS_MASK			GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define AUTH_POS_BEFORE			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define AUTH_POS_AFTER			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define AUTH_SIZE_SHIFT			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define AUTH_SIZE_MASK			GENMASK(13, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define AUTH_SIZE_SHA1			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define AUTH_SIZE_SHA256		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define AUTH_SIZE_ENUM_1_BYTES		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define AUTH_SIZE_ENUM_2_BYTES		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define AUTH_SIZE_ENUM_3_BYTES		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define AUTH_SIZE_ENUM_4_BYTES		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define AUTH_SIZE_ENUM_5_BYTES		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define AUTH_SIZE_ENUM_6_BYTES		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define AUTH_SIZE_ENUM_7_BYTES		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define AUTH_SIZE_ENUM_8_BYTES		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define AUTH_SIZE_ENUM_9_BYTES		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define AUTH_SIZE_ENUM_10_BYTES		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define AUTH_SIZE_ENUM_11_BYTES		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define AUTH_SIZE_ENUM_12_BYTES		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define AUTH_SIZE_ENUM_13_BYTES		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define AUTH_SIZE_ENUM_14_BYTES		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define AUTH_SIZE_ENUM_15_BYTES		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define AUTH_SIZE_ENUM_16_BYTES		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define AUTH_MODE_SHIFT			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define AUTH_MODE_MASK			GENMASK(8, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define AUTH_MODE_HASH			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define AUTH_MODE_HMAC			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define AUTH_MODE_CCM			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define AUTH_MODE_CMAC			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define AUTH_KEY_SIZE_SHIFT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define AUTH_KEY_SIZE_MASK		GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define AUTH_KEY_SZ_AES128		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define AUTH_KEY_SZ_AES256		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define AUTH_ALG_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define AUTH_ALG_MASK			GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define AUTH_ALG_NONE			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define AUTH_ALG_SHA			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define AUTH_ALG_AES			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define AUTH_ALG_KASUMI			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define AUTH_ALG_SNOW3G			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AUTH_ALG_ZUC			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) /* Register bits - REG_ENCR_XTS_DU_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ENCR_XTS_DU_SIZE_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ENCR_XTS_DU_SIZE_MASK		GENMASK(19, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* Register bits - REG_ENCR_SEG_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define F8_KEYSTREAM_ENABLE_SHIFT	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define F8_KEYSTREAM_DISABLED		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define F8_KEYSTREAM_ENABLED		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define F8_DIRECTION_SHIFT		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define F8_DIRECTION_UPLINK		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define F8_DIRECTION_DOWNLINK		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define USE_PIPE_KEY_ENCR_SHIFT		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define USE_PIPE_KEY_ENCR_ENABLED	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define USE_KEY_REGISTERS		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define USE_HW_KEY_ENCR_SHIFT		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define USE_KEY_REG			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define USE_HW_KEY			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define LAST_CCM_SHIFT			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define LAST_CCM_XFR			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define INTERM_CCM_XFR			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CNTR_ALG_SHIFT			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CNTR_ALG_MASK			GENMASK(12, 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CNTR_ALG_NIST			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define ENCODE_SHIFT			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ENCR_MODE_SHIFT			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define ENCR_MODE_MASK			GENMASK(9, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ENCR_MODE_ECB			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ENCR_MODE_CBC			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ENCR_MODE_CTR			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ENCR_MODE_XTS			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ENCR_MODE_CCM			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ENCR_KEY_SZ_SHIFT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ENCR_KEY_SZ_MASK		GENMASK(5, 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ENCR_KEY_SZ_DES			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define ENCR_KEY_SZ_3DES		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ENCR_KEY_SZ_AES128		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ENCR_KEY_SZ_AES256		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ENCR_ALG_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define ENCR_ALG_MASK			GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ENCR_ALG_NONE			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ENCR_ALG_DES			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define ENCR_ALG_AES			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ENCR_ALG_KASUMI			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ENCR_ALG_SNOW_3G		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define ENCR_ALG_ZUC			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) /* Register bits - REG_GOPROC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define GO_SHIFT			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CLR_CNTXT_SHIFT			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define RESULTS_DUMP_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Register bits - REG_ENGINES_AVAIL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define ENCR_AES_SEL_SHIFT		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define DES_SEL_SHIFT			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define ENCR_SNOW3G_SEL_SHIFT		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define ENCR_KASUMI_SEL_SHIFT		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define SHA_SEL_SHIFT			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define SHA512_SEL_SHIFT		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define AUTH_AES_SEL_SHIFT		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define AUTH_SNOW3G_SEL_SHIFT		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define AUTH_KASUMI_SEL_SHIFT		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define BAM_PIPE_SETS_SHIFT		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define BAM_PIPE_SETS_MASK		GENMASK(12, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define AXI_WR_BEATS_SHIFT		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define AXI_WR_BEATS_MASK		GENMASK(18, 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define AXI_RD_BEATS_SHIFT		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define AXI_RD_BEATS_MASK		GENMASK(24, 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define ENCR_ZUC_SEL_SHIFT		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define AUTH_ZUC_SEL_SHIFT		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define ZUC_ENABLE_SHIFT		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #endif /* _REGS_V5_H_ */