Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2011-2014, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DMA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DMA_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* maximum data transfer block size between BAM and CE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define QCE_BAM_BURST_SIZE		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define QCE_AUTHIV_REGS_CNT		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define QCE_AUTH_BYTECOUNT_REGS_CNT	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define QCE_CNTRIV_REGS_CNT		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) struct qce_result_dump {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 	u32 auth_iv[QCE_AUTHIV_REGS_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 	u32 auth_byte_count[QCE_AUTH_BYTECOUNT_REGS_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 	u32 encr_cntr_iv[QCE_CNTRIV_REGS_CNT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 	u32 status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) 	u32 status2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define QCE_IGNORE_BUF_SZ	(2 * QCE_BAM_BURST_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define QCE_RESULT_BUF_SZ	\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 		ALIGN(sizeof(struct qce_result_dump), QCE_BAM_BURST_SIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) struct qce_dma_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 	struct dma_chan *txchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 	struct dma_chan *rxchan;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 	struct qce_result_dump *result_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 	void *ignore_buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) int qce_dma_request(struct device *dev, struct qce_dma_data *dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) void qce_dma_release(struct qce_dma_data *dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) int qce_dma_prep_sgs(struct qce_dma_data *dma, struct scatterlist *sg_in,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 		     int in_ents, struct scatterlist *sg_out, int out_ents,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 		     dma_async_tx_callback cb, void *cb_param);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) void qce_dma_issue_pending(struct qce_dma_data *dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) int qce_dma_terminate_all(struct qce_dma_data *dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) struct scatterlist *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) qce_sgtable_add(struct sg_table *sgt, struct scatterlist *sg_add,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) 		unsigned int max_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif /* _DMA_H_ */