^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2010 Picochip Ltd., Jamie Iles
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef __PICOXCELL_CRYPTO_REGS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define __PICOXCELL_CRYPTO_REGS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define SPA_STATUS_OK 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define SPA_STATUS_ICV_FAIL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SPA_STATUS_MEMORY_ERROR 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SPA_STATUS_BLOCK_ERROR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SPA_IRQ_CTRL_STAT_CNT_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SPA_IRQ_STAT_STAT_MASK (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SPA_FIFO_STAT_STAT_OFFSET 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SPA_FIFO_STAT_STAT_CNT_MASK (0x3F << SPA_FIFO_STAT_STAT_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SPA_STATUS_RES_CODE_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SPA_STATUS_RES_CODE_MASK (0x3 << SPA_STATUS_RES_CODE_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SPA_KEY_SZ_CTX_INDEX_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SPA_KEY_SZ_CIPHER_OFFSET 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SPA_IRQ_EN_REG_OFFSET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SPA_IRQ_STAT_REG_OFFSET 0x00000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SPA_IRQ_CTRL_REG_OFFSET 0x00000008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SPA_FIFO_STAT_REG_OFFSET 0x0000000C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SPA_SDMA_BRST_SZ_REG_OFFSET 0x00000010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SPA_SRC_PTR_REG_OFFSET 0x00000020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SPA_DST_PTR_REG_OFFSET 0x00000024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SPA_OFFSET_REG_OFFSET 0x00000028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SPA_AAD_LEN_REG_OFFSET 0x0000002C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SPA_PROC_LEN_REG_OFFSET 0x00000030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SPA_ICV_LEN_REG_OFFSET 0x00000034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SPA_ICV_OFFSET_REG_OFFSET 0x00000038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SPA_SW_CTRL_REG_OFFSET 0x0000003C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SPA_CTRL_REG_OFFSET 0x00000040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SPA_AUX_INFO_REG_OFFSET 0x0000004C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SPA_STAT_POP_REG_OFFSET 0x00000050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SPA_STATUS_REG_OFFSET 0x00000054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SPA_KEY_SZ_REG_OFFSET 0x00000100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SPA_CIPH_KEY_BASE_REG_OFFSET 0x00004000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SPA_HASH_KEY_BASE_REG_OFFSET 0x00008000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SPA_RC4_CTX_BASE_REG_OFFSET 0x00020000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SPA_IRQ_EN_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SPA_IRQ_CTRL_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SPA_FIFO_STAT_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SPA_SDMA_BRST_SZ_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SPA_SRC_PTR_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SPA_DST_PTR_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SPA_OFFSET_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SPA_AAD_LEN_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SPA_PROC_LEN_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SPA_ICV_LEN_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SPA_ICV_OFFSET_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SPA_SW_CTRL_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SPA_CTRL_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SPA_AUX_INFO_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SPA_STAT_POP_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SPA_STATUS_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SPA_KEY_SZ_REG_RESET 0x00000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SPA_CTRL_HASH_ALG_IDX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SPA_CTRL_CIPH_MODE_IDX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SPA_CTRL_HASH_MODE_IDX 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SPA_CTRL_CTX_IDX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SPA_CTRL_ENCRYPT_IDX 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SPA_CTRL_AAD_COPY 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SPA_CTRL_ICV_PT 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SPA_CTRL_ICV_ENC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPA_CTRL_ICV_APPEND 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPA_CTRL_KEY_EXP 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SPA_KEY_SZ_CXT_IDX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SPA_KEY_SZ_CIPHER_IDX 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SPA_IRQ_EN_CMD0_EN (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SPA_IRQ_EN_STAT_EN (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SPA_IRQ_EN_GLBL_EN (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SPA_CTRL_CIPH_ALG_NULL 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SPA_CTRL_CIPH_ALG_DES 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SPA_CTRL_CIPH_ALG_AES 0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SPA_CTRL_CIPH_ALG_RC4 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SPA_CTRL_CIPH_ALG_MULTI2 0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SPA_CTRL_CIPH_ALG_KASUMI 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SPA_CTRL_HASH_ALG_NULL (0x00 << SPA_CTRL_HASH_ALG_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SPA_CTRL_HASH_ALG_MD5 (0x01 << SPA_CTRL_HASH_ALG_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SPA_CTRL_HASH_ALG_SHA (0x02 << SPA_CTRL_HASH_ALG_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SPA_CTRL_HASH_ALG_SHA224 (0x03 << SPA_CTRL_HASH_ALG_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SPA_CTRL_HASH_ALG_SHA256 (0x04 << SPA_CTRL_HASH_ALG_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SPA_CTRL_HASH_ALG_SHA384 (0x05 << SPA_CTRL_HASH_ALG_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SPA_CTRL_HASH_ALG_SHA512 (0x06 << SPA_CTRL_HASH_ALG_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SPA_CTRL_HASH_ALG_AESMAC (0x07 << SPA_CTRL_HASH_ALG_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SPA_CTRL_HASH_ALG_AESCMAC (0x08 << SPA_CTRL_HASH_ALG_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SPA_CTRL_HASH_ALG_KASF9 (0x09 << SPA_CTRL_HASH_ALG_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SPA_CTRL_CIPH_MODE_NULL (0x00 << SPA_CTRL_CIPH_MODE_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SPA_CTRL_CIPH_MODE_ECB (0x00 << SPA_CTRL_CIPH_MODE_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SPA_CTRL_CIPH_MODE_CBC (0x01 << SPA_CTRL_CIPH_MODE_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SPA_CTRL_CIPH_MODE_CTR (0x02 << SPA_CTRL_CIPH_MODE_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SPA_CTRL_CIPH_MODE_CCM (0x03 << SPA_CTRL_CIPH_MODE_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SPA_CTRL_CIPH_MODE_GCM (0x05 << SPA_CTRL_CIPH_MODE_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SPA_CTRL_CIPH_MODE_OFB (0x07 << SPA_CTRL_CIPH_MODE_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SPA_CTRL_CIPH_MODE_CFB (0x08 << SPA_CTRL_CIPH_MODE_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SPA_CTRL_CIPH_MODE_F8 (0x09 << SPA_CTRL_CIPH_MODE_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SPA_CTRL_HASH_MODE_RAW (0x00 << SPA_CTRL_HASH_MODE_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SPA_CTRL_HASH_MODE_SSLMAC (0x01 << SPA_CTRL_HASH_MODE_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SPA_CTRL_HASH_MODE_HMAC (0x02 << SPA_CTRL_HASH_MODE_IDX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SPA_FIFO_STAT_EMPTY (1 << 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SPA_FIFO_CMD_FULL (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #endif /* __PICOXCELL_CRYPTO_REGS_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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