^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cryptographic API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Support for OMAP SHA1/MD5 HW acceleration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2011 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * Some ideas are from old omap-sha1-md5.c driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define pr_fmt(fmt) "%s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/of_irq.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <linux/crypto.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <crypto/scatterwalk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <crypto/algapi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <crypto/sha.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <crypto/hash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include <crypto/hmac.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include <crypto/internal/hash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #include <crypto/engine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MD5_DIGEST_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SHA_REG_IDIGEST(dd, x) ((dd)->pdata->idigest_ofs + ((x)*0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SHA_REG_DIN(dd, x) ((dd)->pdata->din_ofs + ((x) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SHA_REG_DIGCNT(dd) ((dd)->pdata->digcnt_ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SHA_REG_ODIGEST(dd, x) ((dd)->pdata->odigest_ofs + (x * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SHA_REG_CTRL 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SHA_REG_CTRL_LENGTH (0xFFFFFFFF << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SHA_REG_CTRL_CLOSE_HASH (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SHA_REG_CTRL_ALGO_CONST (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define SHA_REG_CTRL_ALGO (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SHA_REG_CTRL_INPUT_READY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SHA_REG_CTRL_OUTPUT_READY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SHA_REG_REV(dd) ((dd)->pdata->rev_ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SHA_REG_MASK(dd) ((dd)->pdata->mask_ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SHA_REG_MASK_DMA_EN (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SHA_REG_MASK_IT_EN (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SHA_REG_MASK_SOFTRESET (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SHA_REG_AUTOIDLE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SHA_REG_SYSSTATUS(dd) ((dd)->pdata->sysstatus_ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SHA_REG_SYSSTATUS_RESETDONE (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SHA_REG_MODE(dd) ((dd)->pdata->mode_ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SHA_REG_MODE_HMAC_OUTER_HASH (1 << 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define SHA_REG_MODE_HMAC_KEY_PROC (1 << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define SHA_REG_MODE_CLOSE_HASH (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SHA_REG_MODE_ALGO_CONSTANT (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SHA_REG_MODE_ALGO_MASK (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define SHA_REG_MODE_ALGO_MD5_128 (0 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define SHA_REG_MODE_ALGO_SHA1_160 (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SHA_REG_MODE_ALGO_SHA2_224 (2 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SHA_REG_MODE_ALGO_SHA2_256 (3 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SHA_REG_MODE_ALGO_SHA2_384 (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SHA_REG_MODE_ALGO_SHA2_512 (3 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SHA_REG_LENGTH(dd) ((dd)->pdata->length_ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SHA_REG_IRQSTATUS 0x118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SHA_REG_IRQSTATUS_CTX_RDY (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SHA_REG_IRQSTATUS_PARTHASH_RDY (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SHA_REG_IRQSTATUS_INPUT_RDY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SHA_REG_IRQSTATUS_OUTPUT_RDY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SHA_REG_IRQENA 0x11C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SHA_REG_IRQENA_CTX_RDY (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SHA_REG_IRQENA_PARTHASH_RDY (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SHA_REG_IRQENA_INPUT_RDY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SHA_REG_IRQENA_OUTPUT_RDY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DEFAULT_TIMEOUT_INTERVAL HZ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DEFAULT_AUTOSUSPEND_DELAY 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* mostly device flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define FLAGS_FINAL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define FLAGS_DMA_ACTIVE 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define FLAGS_OUTPUT_READY 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define FLAGS_INIT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define FLAGS_CPU 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define FLAGS_DMA_READY 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define FLAGS_AUTO_XOR 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define FLAGS_BE32_SHA1 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define FLAGS_SGS_COPIED 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define FLAGS_SGS_ALLOCED 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define FLAGS_HUGE 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* context flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define FLAGS_FINUP 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define FLAGS_MODE_SHIFT 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define FLAGS_MODE_MASK (SHA_REG_MODE_ALGO_MASK << FLAGS_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define FLAGS_MODE_MD5 (SHA_REG_MODE_ALGO_MD5_128 << FLAGS_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define FLAGS_MODE_SHA1 (SHA_REG_MODE_ALGO_SHA1_160 << FLAGS_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define FLAGS_MODE_SHA224 (SHA_REG_MODE_ALGO_SHA2_224 << FLAGS_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define FLAGS_MODE_SHA256 (SHA_REG_MODE_ALGO_SHA2_256 << FLAGS_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define FLAGS_MODE_SHA384 (SHA_REG_MODE_ALGO_SHA2_384 << FLAGS_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define FLAGS_MODE_SHA512 (SHA_REG_MODE_ALGO_SHA2_512 << FLAGS_MODE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define FLAGS_HMAC 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define FLAGS_ERROR 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define OP_UPDATE 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define OP_FINAL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define OMAP_ALIGN_MASK (sizeof(u32)-1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define OMAP_ALIGNED __attribute__((aligned(sizeof(u32))))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define BUFLEN SHA512_BLOCK_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define OMAP_SHA_DMA_THRESHOLD 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define OMAP_SHA_MAX_DMA_LEN (1024 * 2048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) struct omap_sham_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct omap_sham_reqctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) struct omap_sham_dev *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) u8 op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) u8 digest[SHA512_DIGEST_SIZE] OMAP_ALIGNED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) size_t digcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) size_t bufcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) size_t buflen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* walk state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct scatterlist sgl[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) int offset; /* offset in current sg */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) int sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) unsigned int total; /* total request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) u8 buffer[] OMAP_ALIGNED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) struct omap_sham_hmac_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) struct crypto_shash *shash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) u8 ipad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) u8 opad[SHA512_BLOCK_SIZE] OMAP_ALIGNED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) struct omap_sham_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) struct crypto_engine_ctx enginectx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* fallback stuff */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) struct crypto_shash *fallback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) struct omap_sham_hmac_ctx base[];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define OMAP_SHAM_QUEUE_LENGTH 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) struct omap_sham_algs_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) struct ahash_alg *algs_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) unsigned int registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) struct omap_sham_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) struct omap_sham_algs_info *algs_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) unsigned int algs_info_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) int digest_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) void (*copy_hash)(struct ahash_request *req, int out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) void (*write_ctrl)(struct omap_sham_dev *dd, size_t length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) int final, int dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) void (*trigger)(struct omap_sham_dev *dd, size_t length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) int (*poll_irq)(struct omap_sham_dev *dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) irqreturn_t (*intr_hdlr)(int irq, void *dev_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 odigest_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) u32 idigest_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) u32 din_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) u32 digcnt_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) u32 rev_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 mask_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) u32 sysstatus_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 mode_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) u32 length_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) u32 major_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) u32 major_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) u32 minor_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) u32 minor_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) struct omap_sham_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) unsigned long phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct dma_chan *dma_lch;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) struct tasklet_struct done_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) u8 polling_mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) u8 xmit_buf[BUFLEN] OMAP_ALIGNED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) int fallback_sz;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) struct crypto_queue queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) struct ahash_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) struct crypto_engine *engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) const struct omap_sham_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) struct omap_sham_drv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct list_head dev_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) static struct omap_sham_drv sham = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) .dev_list = LIST_HEAD_INIT(sham.dev_list),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) .lock = __SPIN_LOCK_UNLOCKED(sham.lock),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) static int omap_sham_enqueue(struct ahash_request *req, unsigned int op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) static void omap_sham_finish_req(struct ahash_request *req, int err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) static inline u32 omap_sham_read(struct omap_sham_dev *dd, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) return __raw_readl(dd->io_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) static inline void omap_sham_write(struct omap_sham_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) u32 offset, u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __raw_writel(value, dd->io_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) static inline void omap_sham_write_mask(struct omap_sham_dev *dd, u32 address,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) u32 value, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) val = omap_sham_read(dd, address);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) val |= value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) omap_sham_write(dd, address, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) static inline int omap_sham_wait(struct omap_sham_dev *dd, u32 offset, u32 bit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) unsigned long timeout = jiffies + DEFAULT_TIMEOUT_INTERVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) while (!(omap_sham_read(dd, offset) & bit)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) if (time_is_before_jiffies(timeout))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) static void omap_sham_copy_hash_omap2(struct ahash_request *req, int out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) struct omap_sham_dev *dd = ctx->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) u32 *hash = (u32 *)ctx->digest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) if (out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) hash[i] = omap_sham_read(dd, SHA_REG_IDIGEST(dd, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) omap_sham_write(dd, SHA_REG_IDIGEST(dd, i), hash[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void omap_sham_copy_hash_omap4(struct ahash_request *req, int out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) struct omap_sham_dev *dd = ctx->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) if (ctx->flags & BIT(FLAGS_HMAC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct omap_sham_hmac_ctx *bctx = tctx->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) u32 *opad = (u32 *)bctx->opad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) for (i = 0; i < dd->pdata->digest_size / sizeof(u32); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) if (out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) opad[i] = omap_sham_read(dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) SHA_REG_ODIGEST(dd, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) omap_sham_write(dd, SHA_REG_ODIGEST(dd, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) opad[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) omap_sham_copy_hash_omap2(req, out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) static void omap_sham_copy_ready_hash(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) u32 *in = (u32 *)ctx->digest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) u32 *hash = (u32 *)req->result;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) int i, d, big_endian = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) if (!hash)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) switch (ctx->flags & FLAGS_MODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) case FLAGS_MODE_MD5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) d = MD5_DIGEST_SIZE / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) case FLAGS_MODE_SHA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* OMAP2 SHA1 is big endian */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) if (test_bit(FLAGS_BE32_SHA1, &ctx->dd->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) big_endian = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) d = SHA1_DIGEST_SIZE / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) case FLAGS_MODE_SHA224:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) d = SHA224_DIGEST_SIZE / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) case FLAGS_MODE_SHA256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) d = SHA256_DIGEST_SIZE / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) case FLAGS_MODE_SHA384:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) d = SHA384_DIGEST_SIZE / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) case FLAGS_MODE_SHA512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) d = SHA512_DIGEST_SIZE / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) d = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (big_endian)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) for (i = 0; i < d; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) hash[i] = be32_to_cpup((__be32 *)in + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) for (i = 0; i < d; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) hash[i] = le32_to_cpup((__le32 *)in + i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) static int omap_sham_hw_init(struct omap_sham_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) err = pm_runtime_resume_and_get(dd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) dev_err(dd->dev, "failed to get sync: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) if (!test_bit(FLAGS_INIT, &dd->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) set_bit(FLAGS_INIT, &dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) dd->err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) static void omap_sham_write_ctrl_omap2(struct omap_sham_dev *dd, size_t length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int final, int dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) u32 val = length << 5, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) if (likely(ctx->digcnt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) omap_sham_write_mask(dd, SHA_REG_MASK(dd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) SHA_REG_MASK_IT_EN | (dma ? SHA_REG_MASK_DMA_EN : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) * Setting ALGO_CONST only for the first iteration
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) * and CLOSE_HASH only for the last one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) if ((ctx->flags & FLAGS_MODE_MASK) == FLAGS_MODE_SHA1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) val |= SHA_REG_CTRL_ALGO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) if (!ctx->digcnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) val |= SHA_REG_CTRL_ALGO_CONST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) if (final)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) val |= SHA_REG_CTRL_CLOSE_HASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) mask = SHA_REG_CTRL_ALGO_CONST | SHA_REG_CTRL_CLOSE_HASH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) SHA_REG_CTRL_ALGO | SHA_REG_CTRL_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) omap_sham_write_mask(dd, SHA_REG_CTRL, val, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) static void omap_sham_trigger_omap2(struct omap_sham_dev *dd, size_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static int omap_sham_poll_irq_omap2(struct omap_sham_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) return omap_sham_wait(dd, SHA_REG_CTRL, SHA_REG_CTRL_INPUT_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) static int get_block_size(struct omap_sham_reqctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) int d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) switch (ctx->flags & FLAGS_MODE_MASK) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) case FLAGS_MODE_MD5:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) case FLAGS_MODE_SHA1:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) d = SHA1_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) case FLAGS_MODE_SHA224:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) case FLAGS_MODE_SHA256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) d = SHA256_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) case FLAGS_MODE_SHA384:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) case FLAGS_MODE_SHA512:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) d = SHA512_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) d = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) return d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) static void omap_sham_write_n(struct omap_sham_dev *dd, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) u32 *value, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) for (; count--; value++, offset += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) omap_sham_write(dd, offset, *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) static void omap_sham_write_ctrl_omap4(struct omap_sham_dev *dd, size_t length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) int final, int dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) u32 val, mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) if (likely(ctx->digcnt))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) omap_sham_write(dd, SHA_REG_DIGCNT(dd), ctx->digcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) * Setting ALGO_CONST only for the first iteration and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * CLOSE_HASH only for the last one. Note that flags mode bits
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * correspond to algorithm encoding in mode register.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) val = (ctx->flags & FLAGS_MODE_MASK) >> (FLAGS_MODE_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (!ctx->digcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) struct crypto_ahash *tfm = crypto_ahash_reqtfm(dd->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) struct omap_sham_hmac_ctx *bctx = tctx->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) int bs, nr_dr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) val |= SHA_REG_MODE_ALGO_CONSTANT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) if (ctx->flags & BIT(FLAGS_HMAC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) bs = get_block_size(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) nr_dr = bs / (2 * sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) val |= SHA_REG_MODE_HMAC_KEY_PROC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) omap_sham_write_n(dd, SHA_REG_ODIGEST(dd, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) (u32 *)bctx->ipad, nr_dr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) omap_sham_write_n(dd, SHA_REG_IDIGEST(dd, 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) (u32 *)bctx->ipad + nr_dr, nr_dr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) ctx->digcnt += bs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) if (final) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) val |= SHA_REG_MODE_CLOSE_HASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) if (ctx->flags & BIT(FLAGS_HMAC))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) val |= SHA_REG_MODE_HMAC_OUTER_HASH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) mask = SHA_REG_MODE_ALGO_CONSTANT | SHA_REG_MODE_CLOSE_HASH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) SHA_REG_MODE_ALGO_MASK | SHA_REG_MODE_HMAC_OUTER_HASH |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) SHA_REG_MODE_HMAC_KEY_PROC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) dev_dbg(dd->dev, "ctrl: %08x, flags: %08lx\n", val, ctx->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) omap_sham_write_mask(dd, SHA_REG_MODE(dd), val, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) omap_sham_write(dd, SHA_REG_IRQENA, SHA_REG_IRQENA_OUTPUT_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) omap_sham_write_mask(dd, SHA_REG_MASK(dd),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) SHA_REG_MASK_IT_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) (dma ? SHA_REG_MASK_DMA_EN : 0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) SHA_REG_MASK_IT_EN | SHA_REG_MASK_DMA_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) static void omap_sham_trigger_omap4(struct omap_sham_dev *dd, size_t length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) omap_sham_write(dd, SHA_REG_LENGTH(dd), length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int omap_sham_poll_irq_omap4(struct omap_sham_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) return omap_sham_wait(dd, SHA_REG_IRQSTATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) SHA_REG_IRQSTATUS_INPUT_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) static int omap_sham_xmit_cpu(struct omap_sham_dev *dd, size_t length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) int final)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) int count, len32, bs32, offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) const u32 *buffer;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) int mlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct sg_mapping_iter mi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) dev_dbg(dd->dev, "xmit_cpu: digcnt: %zd, length: %zd, final: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) ctx->digcnt, length, final);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) dd->pdata->write_ctrl(dd, length, final, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) dd->pdata->trigger(dd, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) /* should be non-zero before next lines to disable clocks later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) ctx->digcnt += length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) ctx->total -= length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) if (final)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) set_bit(FLAGS_CPU, &dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) len32 = DIV_ROUND_UP(length, sizeof(u32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) bs32 = get_block_size(ctx) / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) sg_miter_start(&mi, ctx->sg, ctx->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) SG_MITER_FROM_SG | SG_MITER_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) mlen = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) while (len32) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) if (dd->pdata->poll_irq(dd))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) for (count = 0; count < min(len32, bs32); count++, offset++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) if (!mlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) sg_miter_next(&mi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) mlen = mi.length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) if (!mlen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) pr_err("sg miter failure.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) buffer = mi.addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) omap_sham_write(dd, SHA_REG_DIN(dd, count),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) buffer[offset]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) mlen -= 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) len32 -= min(len32, bs32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) sg_miter_stop(&mi);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) return -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) static void omap_sham_dma_callback(void *param)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct omap_sham_dev *dd = param;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) set_bit(FLAGS_DMA_READY, &dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) tasklet_schedule(&dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) static int omap_sham_xmit_dma(struct omap_sham_dev *dd, size_t length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) int final)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) struct dma_async_tx_descriptor *tx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) dev_dbg(dd->dev, "xmit_dma: digcnt: %zd, length: %zd, final: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) ctx->digcnt, length, final);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) if (!dma_map_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) dev_err(dd->dev, "dma_map_sg error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) memset(&cfg, 0, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) cfg.dst_addr = dd->phys_base + SHA_REG_DIN(dd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) cfg.dst_maxburst = get_block_size(ctx) / DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) ret = dmaengine_slave_config(dd->dma_lch, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) pr_err("omap-sham: can't configure dmaengine slave: %d\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) tx = dmaengine_prep_slave_sg(dd->dma_lch, ctx->sg, ctx->sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) if (!tx) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) dev_err(dd->dev, "prep_slave_sg failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) tx->callback = omap_sham_dma_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) tx->callback_param = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dd->pdata->write_ctrl(dd, length, final, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) ctx->digcnt += length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) ctx->total -= length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) if (final)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) set_bit(FLAGS_FINAL, &dd->flags); /* catch last interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) set_bit(FLAGS_DMA_ACTIVE, &dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) dmaengine_submit(tx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) dma_async_issue_pending(dd->dma_lch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) dd->pdata->trigger(dd, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static int omap_sham_copy_sg_lists(struct omap_sham_reqctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct scatterlist *sg, int bs, int new_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int n = sg_nents(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) struct scatterlist *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) int offset = ctx->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ctx->total = new_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) if (ctx->bufcnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) ctx->sg = kmalloc_array(n, sizeof(*sg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) if (!ctx->sg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) sg_init_table(ctx->sg, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) tmp = ctx->sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) ctx->sg_len = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) if (ctx->bufcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) sg_set_buf(tmp, ctx->dd->xmit_buf, ctx->bufcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) tmp = sg_next(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) ctx->sg_len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) new_len -= ctx->bufcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) while (sg && new_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) int len = sg->length - offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) if (len <= 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) offset -= sg->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) sg = sg_next(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) if (new_len < len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) len = new_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) if (len > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) new_len -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) sg_set_page(tmp, sg_page(sg), len, sg->offset + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) ctx->offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) ctx->sg_len++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (new_len <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) tmp = sg_next(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) sg = sg_next(sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) if (tmp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) sg_mark_end(tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) set_bit(FLAGS_SGS_ALLOCED, &ctx->dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) ctx->offset += new_len - ctx->bufcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) ctx->bufcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) static int omap_sham_copy_sgs(struct omap_sham_reqctx *ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) struct scatterlist *sg, int bs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) unsigned int new_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) int pages;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) void *buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) pages = get_order(new_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) buf = (void *)__get_free_pages(GFP_ATOMIC, pages);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) if (!buf) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) pr_err("Couldn't allocate pages for unaligned cases.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) if (ctx->bufcnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) memcpy(buf, ctx->dd->xmit_buf, ctx->bufcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) scatterwalk_map_and_copy(buf + ctx->bufcnt, sg, ctx->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) min(new_len, ctx->total) - ctx->bufcnt, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) sg_init_table(ctx->sgl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) sg_set_buf(ctx->sgl, buf, new_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) ctx->sg = ctx->sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) set_bit(FLAGS_SGS_COPIED, &ctx->dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) ctx->sg_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) ctx->offset += new_len - ctx->bufcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) ctx->bufcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) ctx->total = new_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) static int omap_sham_align_sgs(struct scatterlist *sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) int nbytes, int bs, bool final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) struct omap_sham_reqctx *rctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) int n = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) bool aligned = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) bool list_ok = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) struct scatterlist *sg_tmp = sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) int new_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) int offset = rctx->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) int bufcnt = rctx->bufcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) if (!sg || !sg->length || !nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (bufcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) bufcnt = DIV_ROUND_UP(bufcnt, bs) * bs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) sg_init_table(rctx->sgl, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, bufcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) rctx->sg = rctx->sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) rctx->sg_len = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) new_len = nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) if (offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) list_ok = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) if (final)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) new_len = DIV_ROUND_UP(new_len, bs) * bs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) new_len = (new_len - 1) / bs * bs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) if (!new_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) if (nbytes != new_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) list_ok = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) while (nbytes > 0 && sg_tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) n++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) if (bufcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) if (!IS_ALIGNED(bufcnt, bs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) aligned = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) nbytes -= bufcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) bufcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) if (!nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) list_ok = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #ifdef CONFIG_ZONE_DMA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) if (page_zonenum(sg_page(sg_tmp)) != ZONE_DMA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) aligned = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if (offset < sg_tmp->length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) if (!IS_ALIGNED(offset + sg_tmp->offset, 4)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) aligned = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) if (!IS_ALIGNED(sg_tmp->length - offset, bs)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) aligned = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) if (offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) offset -= sg_tmp->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) if (offset < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) nbytes += offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) nbytes -= sg_tmp->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) sg_tmp = sg_next(sg_tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) if (nbytes < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) list_ok = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) if (new_len > OMAP_SHA_MAX_DMA_LEN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) new_len = OMAP_SHA_MAX_DMA_LEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) aligned = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (!aligned)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) return omap_sham_copy_sgs(rctx, sg, bs, new_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) else if (!list_ok)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) return omap_sham_copy_sg_lists(rctx, sg, bs, new_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) rctx->total = new_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) rctx->offset += new_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) rctx->sg_len = n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) if (rctx->bufcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) sg_init_table(rctx->sgl, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) sg_set_buf(rctx->sgl, rctx->dd->xmit_buf, rctx->bufcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) sg_chain(rctx->sgl, 2, sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) rctx->sg = rctx->sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) rctx->sg = sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static int omap_sham_prepare_request(struct crypto_engine *engine, void *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct ahash_request *req = container_of(areq, struct ahash_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) int bs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) unsigned int nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) bool final = rctx->flags & BIT(FLAGS_FINUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) bool update = rctx->op == OP_UPDATE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) int hash_later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) bs = get_block_size(rctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) nbytes = rctx->bufcnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) if (update)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) nbytes += req->nbytes - rctx->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dev_dbg(rctx->dd->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) "%s: nbytes=%d, bs=%d, total=%d, offset=%d, bufcnt=%zd\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) __func__, nbytes, bs, rctx->total, rctx->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) rctx->bufcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (!nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) rctx->total = nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) if (update && req->nbytes && (!IS_ALIGNED(rctx->bufcnt, bs))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) int len = bs - rctx->bufcnt % bs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) if (len > req->nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) len = req->nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) scatterwalk_map_and_copy(rctx->buffer + rctx->bufcnt, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) 0, len, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) rctx->bufcnt += len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) rctx->offset = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) if (rctx->bufcnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) memcpy(rctx->dd->xmit_buf, rctx->buffer, rctx->bufcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) ret = omap_sham_align_sgs(req->src, nbytes, bs, final, rctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) hash_later = nbytes - rctx->total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) if (hash_later < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) hash_later = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) if (hash_later && hash_later <= rctx->buflen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) scatterwalk_map_and_copy(rctx->buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) req->nbytes - hash_later,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) hash_later, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) rctx->bufcnt = hash_later;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) rctx->bufcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) if (hash_later > rctx->buflen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) set_bit(FLAGS_HUGE, &rctx->dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) rctx->total = min(nbytes, rctx->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) static int omap_sham_update_dma_stop(struct omap_sham_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) struct omap_sham_reqctx *ctx = ahash_request_ctx(dd->req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) dma_unmap_sg(dd->dev, ctx->sg, ctx->sg_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) clear_bit(FLAGS_DMA_ACTIVE, &dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) static struct omap_sham_dev *omap_sham_find_dev(struct omap_sham_reqctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) struct omap_sham_dev *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) if (ctx->dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) return ctx->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) spin_lock_bh(&sham.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dd = list_first_entry(&sham.dev_list, struct omap_sham_dev, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) list_move_tail(&dd->list, &sham.dev_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) ctx->dd = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) spin_unlock_bh(&sham.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static int omap_sham_init(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct crypto_ahash *tfm = crypto_ahash_reqtfm(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) struct omap_sham_dev *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) int bs = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) ctx->dd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) dd = omap_sham_find_dev(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) ctx->flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dev_dbg(dd->dev, "init: digest size: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) crypto_ahash_digestsize(tfm));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) switch (crypto_ahash_digestsize(tfm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) case MD5_DIGEST_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) ctx->flags |= FLAGS_MODE_MD5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) bs = SHA1_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) case SHA1_DIGEST_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) ctx->flags |= FLAGS_MODE_SHA1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) bs = SHA1_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) case SHA224_DIGEST_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) ctx->flags |= FLAGS_MODE_SHA224;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) bs = SHA224_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) case SHA256_DIGEST_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) ctx->flags |= FLAGS_MODE_SHA256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) bs = SHA256_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) case SHA384_DIGEST_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) ctx->flags |= FLAGS_MODE_SHA384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) bs = SHA384_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) case SHA512_DIGEST_SIZE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) ctx->flags |= FLAGS_MODE_SHA512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) bs = SHA512_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) ctx->bufcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) ctx->digcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) ctx->total = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) ctx->offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) ctx->buflen = BUFLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) if (tctx->flags & BIT(FLAGS_HMAC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) if (!test_bit(FLAGS_AUTO_XOR, &dd->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) struct omap_sham_hmac_ctx *bctx = tctx->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) memcpy(ctx->buffer, bctx->ipad, bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) ctx->bufcnt = bs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) ctx->flags |= BIT(FLAGS_HMAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) static int omap_sham_update_req(struct omap_sham_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) struct ahash_request *req = dd->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) bool final = (ctx->flags & BIT(FLAGS_FINUP)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) !(dd->flags & BIT(FLAGS_HUGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) dev_dbg(dd->dev, "update_req: total: %u, digcnt: %zd, final: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) ctx->total, ctx->digcnt, final);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) if (ctx->total < get_block_size(ctx) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) ctx->total < dd->fallback_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) ctx->flags |= BIT(FLAGS_CPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) if (ctx->flags & BIT(FLAGS_CPU))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) err = omap_sham_xmit_cpu(dd, ctx->total, final);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) err = omap_sham_xmit_dma(dd, ctx->total, final);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) /* wait for dma completion before can take more data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) dev_dbg(dd->dev, "update: err: %d, digcnt: %zd\n", err, ctx->digcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static int omap_sham_final_req(struct omap_sham_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) struct ahash_request *req = dd->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) int err = 0, use_dma = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (dd->flags & BIT(FLAGS_HUGE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) if ((ctx->total <= get_block_size(ctx)) || dd->polling_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) * faster to handle last block with cpu or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) * use cpu when dma is not present.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) use_dma = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) if (use_dma)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) err = omap_sham_xmit_dma(dd, ctx->total, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) err = omap_sham_xmit_cpu(dd, ctx->total, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) ctx->bufcnt = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) dev_dbg(dd->dev, "final_req: err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) static int omap_sham_hash_one_req(struct crypto_engine *engine, void *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) struct ahash_request *req = container_of(areq, struct ahash_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) struct omap_sham_dev *dd = ctx->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) bool final = (ctx->flags & BIT(FLAGS_FINUP)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) !(dd->flags & BIT(FLAGS_HUGE));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) dev_dbg(dd->dev, "hash-one: op: %u, total: %u, digcnt: %zd, final: %d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) ctx->op, ctx->total, ctx->digcnt, final);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) dd->req = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) err = omap_sham_hw_init(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) if (ctx->digcnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) dd->pdata->copy_hash(req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (ctx->op == OP_UPDATE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) err = omap_sham_update_req(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) else if (ctx->op == OP_FINAL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) err = omap_sham_final_req(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) if (err != -EINPROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) omap_sham_finish_req(req, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) static int omap_sham_finish_hmac(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) struct omap_sham_hmac_ctx *bctx = tctx->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) int bs = crypto_shash_blocksize(bctx->shash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) int ds = crypto_shash_digestsize(bctx->shash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) SHASH_DESC_ON_STACK(shash, bctx->shash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) shash->tfm = bctx->shash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) return crypto_shash_init(shash) ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) crypto_shash_update(shash, bctx->opad, bs) ?:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) crypto_shash_finup(shash, req->result, ds, req->result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static int omap_sham_finish(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) struct omap_sham_dev *dd = ctx->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) if (ctx->digcnt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) omap_sham_copy_ready_hash(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) if ((ctx->flags & BIT(FLAGS_HMAC)) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) !test_bit(FLAGS_AUTO_XOR, &dd->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) err = omap_sham_finish_hmac(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) dev_dbg(dd->dev, "digcnt: %zd, bufcnt: %zd\n", ctx->digcnt, ctx->bufcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) static void omap_sham_finish_req(struct ahash_request *req, int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) struct omap_sham_dev *dd = ctx->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) if (test_bit(FLAGS_SGS_COPIED, &dd->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) free_pages((unsigned long)sg_virt(ctx->sg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) get_order(ctx->sg->length));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) if (test_bit(FLAGS_SGS_ALLOCED, &dd->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) kfree(ctx->sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) ctx->sg = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) dd->flags &= ~(BIT(FLAGS_SGS_ALLOCED) | BIT(FLAGS_SGS_COPIED) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) BIT(FLAGS_CPU) | BIT(FLAGS_DMA_READY) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) BIT(FLAGS_OUTPUT_READY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166) if (!err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) dd->pdata->copy_hash(req, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (dd->flags & BIT(FLAGS_HUGE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) /* Re-enqueue the request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) omap_sham_enqueue(req, ctx->op);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) if (test_bit(FLAGS_FINAL, &dd->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) err = omap_sham_finish(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) ctx->flags |= BIT(FLAGS_ERROR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* atomic operation is not needed here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) dd->flags &= ~(BIT(FLAGS_FINAL) | BIT(FLAGS_CPU) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) BIT(FLAGS_DMA_READY) | BIT(FLAGS_OUTPUT_READY));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) pm_runtime_mark_last_busy(dd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) pm_runtime_put_autosuspend(dd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) ctx->offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) crypto_finalize_hash_request(dd->engine, req, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) static int omap_sham_handle_queue(struct omap_sham_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) return crypto_transfer_hash_request_to_engine(dd->engine, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) static int omap_sham_enqueue(struct ahash_request *req, unsigned int op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) struct omap_sham_dev *dd = ctx->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) ctx->op = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) return omap_sham_handle_queue(dd, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) static int omap_sham_update(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) struct omap_sham_dev *dd = omap_sham_find_dev(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (!req->nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) if (ctx->bufcnt + req->nbytes <= ctx->buflen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) scatterwalk_map_and_copy(ctx->buffer + ctx->bufcnt, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) 0, req->nbytes, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) ctx->bufcnt += req->nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (dd->polling_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) ctx->flags |= BIT(FLAGS_CPU);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return omap_sham_enqueue(req, OP_UPDATE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static int omap_sham_final_shash(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) struct omap_sham_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) int offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) * If we are running HMAC on limited hardware support, skip
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) * the ipad in the beginning of the buffer if we are going for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) * software fallback algorithm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) if (test_bit(FLAGS_HMAC, &ctx->flags) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) !test_bit(FLAGS_AUTO_XOR, &ctx->dd->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) offset = get_block_size(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) return crypto_shash_tfm_digest(tctx->fallback, ctx->buffer + offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) ctx->bufcnt - offset, req->result);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) static int omap_sham_final(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) ctx->flags |= BIT(FLAGS_FINUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) if (ctx->flags & BIT(FLAGS_ERROR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) return 0; /* uncompleted hash is not needed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) * OMAP HW accel works only with buffers >= 9.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) * HMAC is always >= 9 because ipad == block size.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) * If buffersize is less than fallback_sz, we use fallback
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) * SW encoding, as using DMA + HW in this case doesn't provide
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) * any benefit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) if (!ctx->digcnt && ctx->bufcnt < ctx->dd->fallback_sz)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) return omap_sham_final_shash(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) else if (ctx->bufcnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) return omap_sham_enqueue(req, OP_FINAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /* copy ready hash (+ finalize hmac) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) return omap_sham_finish(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) static int omap_sham_finup(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) struct omap_sham_reqctx *ctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) int err1, err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) ctx->flags |= BIT(FLAGS_FINUP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) err1 = omap_sham_update(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (err1 == -EINPROGRESS || err1 == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) return err1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) * final() has to be always called to cleanup resources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) * even if udpate() failed, except EINPROGRESS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) err2 = omap_sham_final(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return err1 ?: err2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) static int omap_sham_digest(struct ahash_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return omap_sham_init(req) ?: omap_sham_finup(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) static int omap_sham_setkey(struct crypto_ahash *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) struct omap_sham_ctx *tctx = crypto_ahash_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) struct omap_sham_hmac_ctx *bctx = tctx->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) int bs = crypto_shash_blocksize(bctx->shash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) int ds = crypto_shash_digestsize(bctx->shash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) err = crypto_shash_setkey(tctx->fallback, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) if (keylen > bs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) err = crypto_shash_tfm_digest(bctx->shash, key, keylen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) bctx->ipad);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) keylen = ds;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) memcpy(bctx->ipad, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) memset(bctx->ipad + keylen, 0, bs - keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) if (!test_bit(FLAGS_AUTO_XOR, &sham.flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) memcpy(bctx->opad, bctx->ipad, bs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) for (i = 0; i < bs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) bctx->ipad[i] ^= HMAC_IPAD_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329) bctx->opad[i] ^= HMAC_OPAD_VALUE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) static int omap_sham_cra_init_alg(struct crypto_tfm *tfm, const char *alg_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) const char *alg_name = crypto_tfm_alg_name(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) /* Allocate a fallback and abort if it failed. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) tctx->fallback = crypto_alloc_shash(alg_name, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) CRYPTO_ALG_NEED_FALLBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) if (IS_ERR(tctx->fallback)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) pr_err("omap-sham: fallback driver '%s' "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) "could not be loaded.\n", alg_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) return PTR_ERR(tctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) crypto_ahash_set_reqsize(__crypto_ahash_cast(tfm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) sizeof(struct omap_sham_reqctx) + BUFLEN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) if (alg_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) struct omap_sham_hmac_ctx *bctx = tctx->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) tctx->flags |= BIT(FLAGS_HMAC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) bctx->shash = crypto_alloc_shash(alg_base, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) CRYPTO_ALG_NEED_FALLBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) if (IS_ERR(bctx->shash)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) pr_err("omap-sham: base driver '%s' "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) "could not be loaded.\n", alg_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) crypto_free_shash(tctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) return PTR_ERR(bctx->shash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) tctx->enginectx.op.do_one_request = omap_sham_hash_one_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) tctx->enginectx.op.prepare_request = omap_sham_prepare_request;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) tctx->enginectx.op.unprepare_request = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) static int omap_sham_cra_init(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) return omap_sham_cra_init_alg(tfm, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) static int omap_sham_cra_sha1_init(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) return omap_sham_cra_init_alg(tfm, "sha1");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) static int omap_sham_cra_sha224_init(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) return omap_sham_cra_init_alg(tfm, "sha224");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) static int omap_sham_cra_sha256_init(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391) return omap_sham_cra_init_alg(tfm, "sha256");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) static int omap_sham_cra_md5_init(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) return omap_sham_cra_init_alg(tfm, "md5");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) static int omap_sham_cra_sha384_init(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) return omap_sham_cra_init_alg(tfm, "sha384");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) static int omap_sham_cra_sha512_init(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) return omap_sham_cra_init_alg(tfm, "sha512");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) static void omap_sham_cra_exit(struct crypto_tfm *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) struct omap_sham_ctx *tctx = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) crypto_free_shash(tctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) tctx->fallback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (tctx->flags & BIT(FLAGS_HMAC)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) struct omap_sham_hmac_ctx *bctx = tctx->base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418) crypto_free_shash(bctx->shash);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) static int omap_sham_export(struct ahash_request *req, void *out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) memcpy(out, rctx, sizeof(*rctx) + rctx->bufcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) static int omap_sham_import(struct ahash_request *req, const void *in)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) struct omap_sham_reqctx *rctx = ahash_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) const struct omap_sham_reqctx *ctx_in = in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) memcpy(rctx, in, sizeof(*rctx) + ctx_in->bufcnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) static struct ahash_alg algs_sha1_md5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) .init = omap_sham_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) .update = omap_sham_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) .final = omap_sham_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) .finup = omap_sham_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) .digest = omap_sham_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) .halg.digestsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) .cra_name = "sha1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) .cra_driver_name = "omap-sha1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) .cra_priority = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) .cra_blocksize = SHA1_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) .cra_ctxsize = sizeof(struct omap_sham_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) .cra_alignmask = OMAP_ALIGN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) .cra_init = omap_sham_cra_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) .cra_exit = omap_sham_cra_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) .init = omap_sham_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) .update = omap_sham_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) .final = omap_sham_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) .finup = omap_sham_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) .digest = omap_sham_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) .halg.digestsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) .cra_name = "md5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) .cra_driver_name = "omap-md5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) .cra_priority = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) .cra_blocksize = SHA1_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) .cra_ctxsize = sizeof(struct omap_sham_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) .cra_alignmask = OMAP_ALIGN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) .cra_init = omap_sham_cra_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) .cra_exit = omap_sham_cra_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) .init = omap_sham_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) .update = omap_sham_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) .final = omap_sham_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) .finup = omap_sham_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) .digest = omap_sham_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) .setkey = omap_sham_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) .halg.digestsize = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) .cra_name = "hmac(sha1)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) .cra_driver_name = "omap-hmac-sha1",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) .cra_priority = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501) .cra_blocksize = SHA1_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) .cra_ctxsize = sizeof(struct omap_sham_ctx) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) sizeof(struct omap_sham_hmac_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) .cra_alignmask = OMAP_ALIGN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) .cra_init = omap_sham_cra_sha1_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507) .cra_exit = omap_sham_cra_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) .init = omap_sham_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) .update = omap_sham_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) .final = omap_sham_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .finup = omap_sham_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .digest = omap_sham_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .setkey = omap_sham_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .halg.digestsize = MD5_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) .cra_name = "hmac(md5)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) .cra_driver_name = "omap-hmac-md5",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) .cra_priority = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) .cra_blocksize = SHA1_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) .cra_ctxsize = sizeof(struct omap_sham_ctx) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) sizeof(struct omap_sham_hmac_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) .cra_alignmask = OMAP_ALIGN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) .cra_init = omap_sham_cra_md5_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) .cra_exit = omap_sham_cra_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) /* OMAP4 has some algs in addition to what OMAP2 has */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) static struct ahash_alg algs_sha224_sha256[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) .init = omap_sham_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) .update = omap_sham_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) .final = omap_sham_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) .finup = omap_sham_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) .digest = omap_sham_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) .halg.digestsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546) .cra_name = "sha224",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) .cra_driver_name = "omap-sha224",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) .cra_priority = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) .cra_blocksize = SHA224_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) .cra_ctxsize = sizeof(struct omap_sham_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) .cra_alignmask = OMAP_ALIGN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556) .cra_init = omap_sham_cra_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) .cra_exit = omap_sham_cra_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) .init = omap_sham_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) .update = omap_sham_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) .final = omap_sham_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) .finup = omap_sham_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) .digest = omap_sham_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) .halg.digestsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) .cra_name = "sha256",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) .cra_driver_name = "omap-sha256",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) .cra_priority = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) .cra_blocksize = SHA256_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) .cra_ctxsize = sizeof(struct omap_sham_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) .cra_alignmask = OMAP_ALIGN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) .cra_init = omap_sham_cra_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) .cra_exit = omap_sham_cra_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) .init = omap_sham_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) .update = omap_sham_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) .final = omap_sham_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) .finup = omap_sham_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) .digest = omap_sham_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) .setkey = omap_sham_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) .halg.digestsize = SHA224_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) .cra_name = "hmac(sha224)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) .cra_driver_name = "omap-hmac-sha224",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593) .cra_priority = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) .cra_blocksize = SHA224_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) .cra_ctxsize = sizeof(struct omap_sham_ctx) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) sizeof(struct omap_sham_hmac_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) .cra_alignmask = OMAP_ALIGN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) .cra_init = omap_sham_cra_sha224_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) .cra_exit = omap_sham_cra_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) .init = omap_sham_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) .update = omap_sham_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) .final = omap_sham_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610) .finup = omap_sham_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) .digest = omap_sham_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) .setkey = omap_sham_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) .halg.digestsize = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) .cra_name = "hmac(sha256)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) .cra_driver_name = "omap-hmac-sha256",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) .cra_priority = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) .cra_blocksize = SHA256_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) .cra_ctxsize = sizeof(struct omap_sham_ctx) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) sizeof(struct omap_sham_hmac_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) .cra_alignmask = OMAP_ALIGN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) .cra_init = omap_sham_cra_sha256_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) .cra_exit = omap_sham_cra_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) static struct ahash_alg algs_sha384_sha512[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) .init = omap_sham_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .update = omap_sham_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .final = omap_sham_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .finup = omap_sham_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .digest = omap_sham_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .halg.digestsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) .cra_name = "sha384",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) .cra_driver_name = "omap-sha384",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) .cra_priority = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) .cra_blocksize = SHA384_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) .cra_ctxsize = sizeof(struct omap_sham_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) .cra_alignmask = OMAP_ALIGN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) .cra_init = omap_sham_cra_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) .cra_exit = omap_sham_cra_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) .init = omap_sham_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) .update = omap_sham_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) .final = omap_sham_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) .finup = omap_sham_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) .digest = omap_sham_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) .halg.digestsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) .cra_name = "sha512",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) .cra_driver_name = "omap-sha512",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) .cra_priority = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669) .cra_blocksize = SHA512_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) .cra_ctxsize = sizeof(struct omap_sham_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) .cra_alignmask = OMAP_ALIGN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) .cra_init = omap_sham_cra_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) .cra_exit = omap_sham_cra_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) .init = omap_sham_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679) .update = omap_sham_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) .final = omap_sham_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) .finup = omap_sham_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) .digest = omap_sham_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) .setkey = omap_sham_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) .halg.digestsize = SHA384_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) .cra_name = "hmac(sha384)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) .cra_driver_name = "omap-hmac-sha384",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) .cra_priority = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) .cra_blocksize = SHA384_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) .cra_ctxsize = sizeof(struct omap_sham_ctx) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) sizeof(struct omap_sham_hmac_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) .cra_alignmask = OMAP_ALIGN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) .cra_init = omap_sham_cra_sha384_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) .cra_exit = omap_sham_cra_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) .init = omap_sham_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) .update = omap_sham_update,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) .final = omap_sham_final,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) .finup = omap_sham_finup,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) .digest = omap_sham_digest,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707) .setkey = omap_sham_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) .halg.digestsize = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) .halg.base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) .cra_name = "hmac(sha512)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) .cra_driver_name = "omap-hmac-sha512",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) .cra_priority = 400,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) .cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) .cra_blocksize = SHA512_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) .cra_ctxsize = sizeof(struct omap_sham_ctx) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) sizeof(struct omap_sham_hmac_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) .cra_alignmask = OMAP_ALIGN_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721) .cra_init = omap_sham_cra_sha512_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) .cra_exit = omap_sham_cra_exit,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) static void omap_sham_done_task(unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) struct omap_sham_dev *dd = (struct omap_sham_dev *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) dev_dbg(dd->dev, "%s: flags=%lx\n", __func__, dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (test_bit(FLAGS_CPU, &dd->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) } else if (test_bit(FLAGS_DMA_READY, &dd->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) if (test_bit(FLAGS_DMA_ACTIVE, &dd->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) omap_sham_update_dma_stop(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) if (dd->err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) err = dd->err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) if (test_and_clear_bit(FLAGS_OUTPUT_READY, &dd->flags)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) /* hash or semi-hash ready */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) clear_bit(FLAGS_DMA_READY, &dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) goto finish;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) finish:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) dev_dbg(dd->dev, "update done: err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) /* finish curent request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) omap_sham_finish_req(dd->req, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) static irqreturn_t omap_sham_irq_common(struct omap_sham_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) set_bit(FLAGS_OUTPUT_READY, &dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) tasklet_schedule(&dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) static irqreturn_t omap_sham_irq_omap2(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) struct omap_sham_dev *dd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) if (unlikely(test_bit(FLAGS_FINAL, &dd->flags)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) /* final -> allow device to go to power-saving mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) omap_sham_write_mask(dd, SHA_REG_CTRL, 0, SHA_REG_CTRL_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) omap_sham_write_mask(dd, SHA_REG_CTRL, SHA_REG_CTRL_OUTPUT_READY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) SHA_REG_CTRL_OUTPUT_READY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) omap_sham_read(dd, SHA_REG_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) return omap_sham_irq_common(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) static irqreturn_t omap_sham_irq_omap4(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) struct omap_sham_dev *dd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) omap_sham_write_mask(dd, SHA_REG_MASK(dd), 0, SHA_REG_MASK_IT_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) return omap_sham_irq_common(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) static struct omap_sham_algs_info omap_sham_algs_info_omap2[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) .algs_list = algs_sha1_md5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) .size = ARRAY_SIZE(algs_sha1_md5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) static const struct omap_sham_pdata omap_sham_pdata_omap2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) .algs_info = omap_sham_algs_info_omap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) .flags = BIT(FLAGS_BE32_SHA1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) .digest_size = SHA1_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) .copy_hash = omap_sham_copy_hash_omap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) .write_ctrl = omap_sham_write_ctrl_omap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) .trigger = omap_sham_trigger_omap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) .poll_irq = omap_sham_poll_irq_omap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) .intr_hdlr = omap_sham_irq_omap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) .idigest_ofs = 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) .din_ofs = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) .digcnt_ofs = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) .rev_ofs = 0x5c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) .mask_ofs = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) .sysstatus_ofs = 0x64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) .major_mask = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) .major_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) .minor_mask = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) .minor_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) static struct omap_sham_algs_info omap_sham_algs_info_omap4[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) .algs_list = algs_sha1_md5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) .size = ARRAY_SIZE(algs_sha1_md5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) .algs_list = algs_sha224_sha256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) .size = ARRAY_SIZE(algs_sha224_sha256),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) static const struct omap_sham_pdata omap_sham_pdata_omap4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) .algs_info = omap_sham_algs_info_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836) .flags = BIT(FLAGS_AUTO_XOR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) .digest_size = SHA256_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) .copy_hash = omap_sham_copy_hash_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) .write_ctrl = omap_sham_write_ctrl_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) .trigger = omap_sham_trigger_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) .poll_irq = omap_sham_poll_irq_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) .intr_hdlr = omap_sham_irq_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) .idigest_ofs = 0x020,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) .odigest_ofs = 0x0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) .din_ofs = 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) .digcnt_ofs = 0x040,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) .rev_ofs = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) .mask_ofs = 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) .sysstatus_ofs = 0x114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) .mode_ofs = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) .length_ofs = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) .major_mask = 0x0700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) .major_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) .minor_mask = 0x003f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) .minor_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) static struct omap_sham_algs_info omap_sham_algs_info_omap5[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) .algs_list = algs_sha1_md5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) .size = ARRAY_SIZE(algs_sha1_md5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) .algs_list = algs_sha224_sha256,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) .size = ARRAY_SIZE(algs_sha224_sha256),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) .algs_list = algs_sha384_sha512,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) .size = ARRAY_SIZE(algs_sha384_sha512),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) static const struct omap_sham_pdata omap_sham_pdata_omap5 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) .algs_info = omap_sham_algs_info_omap5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) .algs_info_size = ARRAY_SIZE(omap_sham_algs_info_omap5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) .flags = BIT(FLAGS_AUTO_XOR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) .digest_size = SHA512_DIGEST_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) .copy_hash = omap_sham_copy_hash_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) .write_ctrl = omap_sham_write_ctrl_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) .trigger = omap_sham_trigger_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) .poll_irq = omap_sham_poll_irq_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) .intr_hdlr = omap_sham_irq_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) .idigest_ofs = 0x240,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) .odigest_ofs = 0x200,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) .din_ofs = 0x080,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) .digcnt_ofs = 0x280,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) .rev_ofs = 0x100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) .mask_ofs = 0x110,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) .sysstatus_ofs = 0x114,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) .mode_ofs = 0x284,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) .length_ofs = 0x288,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) .major_mask = 0x0700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) .major_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) .minor_mask = 0x003f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) .minor_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) static const struct of_device_id omap_sham_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) .compatible = "ti,omap2-sham",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) .data = &omap_sham_pdata_omap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) .compatible = "ti,omap3-sham",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) .data = &omap_sham_pdata_omap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) .compatible = "ti,omap4-sham",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) .data = &omap_sham_pdata_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) .compatible = "ti,omap5-sham",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) .data = &omap_sham_pdata_omap5,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) MODULE_DEVICE_TABLE(of, omap_sham_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) static int omap_sham_get_res_of(struct omap_sham_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) struct device *dev, struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) dd->pdata = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) if (!dd->pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) dev_err(dev, "no compatible OF match\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) err = of_address_to_resource(node, 0, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) dev_err(dev, "can't translate OF node address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) dd->irq = irq_of_parse_and_map(node, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) if (!dd->irq) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941) dev_err(dev, "can't translate OF irq value\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) static const struct of_device_id omap_sham_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) static int omap_sham_get_res_of(struct omap_sham_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) struct device *dev, struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) static int omap_sham_get_res_pdev(struct omap_sham_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) struct platform_device *pdev, struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) /* Get the base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) dev_err(dev, "no MEM resource info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) memcpy(res, r, sizeof(*res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) /* Get the IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) dd->irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) if (dd->irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) err = dd->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) /* Only OMAP2/3 can be non-DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) dd->pdata = &omap_sham_pdata_omap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991) static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) struct omap_sham_dev *dd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) return sprintf(buf, "%d\n", dd->fallback_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) const char *buf, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) struct omap_sham_dev *dd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) ssize_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) status = kstrtol(buf, 0, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) /* HW accelerator only works with buffers > 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) if (value < 9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) dev_err(dev, "minimum fallback size 9\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) dd->fallback_sz = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024) struct omap_sham_dev *dd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) return sprintf(buf, "%d\n", dd->queue.max_qlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) static ssize_t queue_len_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) struct omap_sham_dev *dd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) ssize_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) status = kstrtol(buf, 0, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) if (value < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) * Changing the queue size in fly is safe, if size becomes smaller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) * than current size, it will just not accept new entries until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) * it has shrank enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) dd->queue.max_qlen = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) static DEVICE_ATTR_RW(queue_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) static DEVICE_ATTR_RW(fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) static struct attribute *omap_sham_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) &dev_attr_queue_len.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) &dev_attr_fallback.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) static struct attribute_group omap_sham_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) .attrs = omap_sham_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) static int omap_sham_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) struct omap_sham_dev *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) dma_cap_mask_t mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) int err, i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) u32 rev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) dd = devm_kzalloc(dev, sizeof(struct omap_sham_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) if (dd == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) dev_err(dev, "unable to alloc data struct.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) goto data_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) dd->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) platform_set_drvdata(pdev, dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) INIT_LIST_HEAD(&dd->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) tasklet_init(&dd->done_task, omap_sham_done_task, (unsigned long)dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) crypto_init_queue(&dd->queue, OMAP_SHAM_QUEUE_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) err = (dev->of_node) ? omap_sham_get_res_of(dd, dev, &res) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) omap_sham_get_res_pdev(dd, pdev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) goto data_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) dd->io_base = devm_ioremap_resource(dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) if (IS_ERR(dd->io_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) err = PTR_ERR(dd->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) goto data_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) dd->phys_base = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) err = devm_request_irq(dev, dd->irq, dd->pdata->intr_hdlr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) IRQF_TRIGGER_NONE, dev_name(dev), dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) dev_err(dev, "unable to request irq %d, err = %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) dd->irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) goto data_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109) dma_cap_zero(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) dma_cap_set(DMA_SLAVE, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) dd->dma_lch = dma_request_chan(dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) if (IS_ERR(dd->dma_lch)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) err = PTR_ERR(dd->dma_lch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) if (err == -EPROBE_DEFER)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) goto data_err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) dd->polling_mode = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) dev_dbg(dev, "using polling mode instead of dma\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) dd->flags |= dd->pdata->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) sham.flags |= dd->pdata->flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) pm_runtime_use_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) dd->fallback_sz = OMAP_SHA_DMA_THRESHOLD;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) pm_runtime_irq_safe(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) err = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) dev_err(dev, "failed to get sync: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) goto err_pm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) rev = omap_sham_read(dd, SHA_REG_REV(dd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) pm_runtime_put_sync(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) dev_info(dev, "hw accel on OMAP rev %u.%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) (rev & dd->pdata->major_mask) >> dd->pdata->major_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) (rev & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) spin_lock_bh(&sham.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) list_add_tail(&dd->list, &sham.dev_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) spin_unlock_bh(&sham.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) dd->engine = crypto_engine_alloc_init(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) if (!dd->engine) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) goto err_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) err = crypto_engine_start(dd->engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) goto err_engine_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) for (i = 0; i < dd->pdata->algs_info_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) if (dd->pdata->algs_info[i].registered)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) struct ahash_alg *alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) alg = &dd->pdata->algs_info[i].algs_list[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) alg->export = omap_sham_export;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) alg->import = omap_sham_import;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) alg->halg.statesize = sizeof(struct omap_sham_reqctx) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) BUFLEN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) err = crypto_register_ahash(alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) goto err_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) dd->pdata->algs_info[i].registered++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) err = sysfs_create_group(&dev->kobj, &omap_sham_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) dev_err(dev, "could not create sysfs device attrs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) goto err_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) err_algs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) crypto_unregister_ahash(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) &dd->pdata->algs_info[i].algs_list[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) err_engine_start:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) crypto_engine_exit(dd->engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) err_engine:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) spin_lock_bh(&sham.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) list_del(&dd->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) spin_unlock_bh(&sham.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) err_pm:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) if (!dd->polling_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) dma_release_channel(dd->dma_lch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) data_err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) dev_err(dev, "initialization failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) static int omap_sham_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) struct omap_sham_dev *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) dd = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) spin_lock_bh(&sham.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) list_del(&dd->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) spin_unlock_bh(&sham.lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) crypto_unregister_ahash(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) &dd->pdata->algs_info[i].algs_list[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) dd->pdata->algs_info[i].registered--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) tasklet_kill(&dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) pm_runtime_disable(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) if (!dd->polling_mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) dma_release_channel(dd->dma_lch);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) sysfs_remove_group(&dd->dev->kobj, &omap_sham_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) static int omap_sham_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) static int omap_sham_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) int err = pm_runtime_resume_and_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) dev_err(dev, "failed to get sync: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) static SIMPLE_DEV_PM_OPS(omap_sham_pm_ops, omap_sham_suspend, omap_sham_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) static struct platform_driver omap_sham_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) .probe = omap_sham_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) .remove = omap_sham_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .name = "omap-sham",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .pm = &omap_sham_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .of_match_table = omap_sham_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) module_platform_driver(omap_sham_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) MODULE_DESCRIPTION("OMAP SHA1/MD5 hw acceleration support.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) MODULE_AUTHOR("Dmitry Kasatkin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) MODULE_ALIAS("platform:omap-sham");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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