^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Support for OMAP DES and Triple DES HW acceleration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2013 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Author: Joel Fernandes <joelf@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define pr_fmt(fmt) "%s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define prn(num) printk(#num "=%d\n", num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define prx(num) printk(#num "=%x\n", num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define prn(num) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define prx(num) do { } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <linux/crypto.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <crypto/scatterwalk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <crypto/internal/des.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <crypto/internal/skcipher.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #include <crypto/algapi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include <crypto/engine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #include "omap-crypto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define DST_MAXBURST 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define DES_BLOCK_WORDS (DES_BLOCK_SIZE >> 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define _calc_walked(inout) (dd->inout##_walk.offset - dd->inout##_sg->offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define DES_REG_KEY(dd, x) ((dd)->pdata->key_ofs - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ((x ^ 0x01) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define DES_REG_IV(dd, x) ((dd)->pdata->iv_ofs + ((x) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define DES_REG_CTRL(dd) ((dd)->pdata->ctrl_ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DES_REG_CTRL_CBC BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DES_REG_CTRL_TDES BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define DES_REG_CTRL_DIRECTION BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define DES_REG_CTRL_INPUT_READY BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DES_REG_CTRL_OUTPUT_READY BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define DES_REG_DATA_N(dd, x) ((dd)->pdata->data_ofs + ((x) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DES_REG_REV(dd) ((dd)->pdata->rev_ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DES_REG_MASK(dd) ((dd)->pdata->mask_ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DES_REG_LENGTH_N(x) (0x24 + ((x) * 0x04))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DES_REG_IRQ_STATUS(dd) ((dd)->pdata->irq_status_ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DES_REG_IRQ_ENABLE(dd) ((dd)->pdata->irq_enable_ofs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DES_REG_IRQ_DATA_IN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DES_REG_IRQ_DATA_OUT BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define FLAGS_MODE_MASK 0x000f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define FLAGS_ENCRYPT BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define FLAGS_CBC BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define FLAGS_INIT BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define FLAGS_BUSY BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DEFAULT_AUTOSUSPEND_DELAY 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define FLAGS_IN_DATA_ST_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define FLAGS_OUT_DATA_ST_SHIFT 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) struct omap_des_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) struct crypto_engine_ctx enginectx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) struct omap_des_dev *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) int keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) __le32 key[(3 * DES_KEY_SIZE) / sizeof(u32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) struct omap_des_reqctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) unsigned long mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define OMAP_DES_QUEUE_LENGTH 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define OMAP_DES_CACHE_SIZE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) struct omap_des_algs_info {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) struct skcipher_alg *algs_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) unsigned int registered;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) struct omap_des_pdata {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) struct omap_des_algs_info *algs_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) unsigned int algs_info_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) void (*trigger)(struct omap_des_dev *dd, int length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 key_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) u32 iv_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 ctrl_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) u32 data_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 rev_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) u32 mask_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) u32 irq_enable_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) u32 irq_status_ofs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) u32 dma_enable_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) u32 dma_enable_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) u32 dma_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) u32 major_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 major_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) u32 minor_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) u32 minor_shift;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) struct omap_des_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) unsigned long phys_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) void __iomem *io_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) struct omap_des_ctx *ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) struct tasklet_struct done_task;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) struct skcipher_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) struct crypto_engine *engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * total is used by PIO mode for book keeping so introduce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * variable total_save as need it to calc page_order
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) size_t total;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) size_t total_save;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) struct scatterlist *in_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) struct scatterlist *out_sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* Buffers for copying for unaligned cases */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) struct scatterlist in_sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) struct scatterlist out_sgl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) struct scatterlist *orig_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) struct scatter_walk in_walk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) struct scatter_walk out_walk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) struct dma_chan *dma_lch_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) struct dma_chan *dma_lch_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int in_sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) int out_sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) int pio_only;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) const struct omap_des_pdata *pdata;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* keep registered devices data here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static LIST_HEAD(dev_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) static DEFINE_SPINLOCK(list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define omap_des_read(dd, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) int _read_ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) _read_ret = __raw_readl(dd->io_base + offset); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) pr_err("omap_des_read(" #offset "=%#x)= %#x\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) offset, _read_ret); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) _read_ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) static inline u32 omap_des_read(struct omap_des_dev *dd, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) return __raw_readl(dd->io_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define omap_des_write(dd, offset, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) pr_err("omap_des_write(" #offset "=%#x) value=%#x\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) offset, value); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) __raw_writel(value, dd->io_base + offset); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) static inline void omap_des_write(struct omap_des_dev *dd, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) __raw_writel(value, dd->io_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) static inline void omap_des_write_mask(struct omap_des_dev *dd, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) u32 value, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) val = omap_des_read(dd, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) val |= value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) omap_des_write(dd, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) static void omap_des_write_n(struct omap_des_dev *dd, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) u32 *value, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) for (; count--; value++, offset += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) omap_des_write(dd, offset, *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) static int omap_des_hw_init(struct omap_des_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * clocks are enabled when request starts and disabled when finished.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * It may be long delays between requests.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * Device might go to off mode to save power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) err = pm_runtime_get_sync(dd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) pm_runtime_put_noidle(dd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) if (!(dd->flags & FLAGS_INIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) dd->flags |= FLAGS_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) dd->err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) static int omap_des_write_ctrl(struct omap_des_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) unsigned int key32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) u32 val = 0, mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) err = omap_des_hw_init(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) key32 = dd->ctx->keylen / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* it seems a key should always be set even if it has not changed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) for (i = 0; i < key32; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) omap_des_write(dd, DES_REG_KEY(dd, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) __le32_to_cpu(dd->ctx->key[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) if ((dd->flags & FLAGS_CBC) && dd->req->iv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) omap_des_write_n(dd, DES_REG_IV(dd, 0), (void *)dd->req->iv, 2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) if (dd->flags & FLAGS_CBC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) val |= DES_REG_CTRL_CBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) if (dd->flags & FLAGS_ENCRYPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) val |= DES_REG_CTRL_DIRECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) if (key32 == 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) val |= DES_REG_CTRL_TDES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) mask |= DES_REG_CTRL_CBC | DES_REG_CTRL_DIRECTION | DES_REG_CTRL_TDES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) omap_des_write_mask(dd, DES_REG_CTRL(dd), val, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) static void omap_des_dma_trigger_omap4(struct omap_des_dev *dd, int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) omap_des_write(dd, DES_REG_LENGTH_N(0), length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) val = dd->pdata->dma_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) if (dd->dma_lch_out != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) val |= dd->pdata->dma_enable_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) if (dd->dma_lch_in != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) val |= dd->pdata->dma_enable_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) dd->pdata->dma_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) omap_des_write_mask(dd, DES_REG_MASK(dd), val, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) static void omap_des_dma_stop(struct omap_des_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) dd->pdata->dma_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) omap_des_write_mask(dd, DES_REG_MASK(dd), 0, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) static struct omap_des_dev *omap_des_find_dev(struct omap_des_ctx *ctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct omap_des_dev *dd = NULL, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) spin_lock_bh(&list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) if (!ctx->dd) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) list_for_each_entry(tmp, &dev_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* FIXME: take fist available des core */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dd = tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) ctx->dd = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* already found before */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) dd = ctx->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) spin_unlock_bh(&list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) return dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) static void omap_des_dma_out_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct omap_des_dev *dd = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* dma_lch_out - completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) tasklet_schedule(&dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) static int omap_des_dma_init(struct omap_des_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) dd->dma_lch_out = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) dd->dma_lch_in = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) if (IS_ERR(dd->dma_lch_in)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) dev_err(dd->dev, "Unable to request in DMA channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) return PTR_ERR(dd->dma_lch_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) if (IS_ERR(dd->dma_lch_out)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) dev_err(dd->dev, "Unable to request out DMA channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) err = PTR_ERR(dd->dma_lch_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) goto err_dma_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) err_dma_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) dma_release_channel(dd->dma_lch_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) static void omap_des_dma_cleanup(struct omap_des_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) if (dd->pio_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) dma_release_channel(dd->dma_lch_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) dma_release_channel(dd->dma_lch_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) static int omap_des_crypt_dma(struct crypto_tfm *tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct scatterlist *in_sg, struct scatterlist *out_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int in_sg_len, int out_sg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct omap_des_ctx *ctx = crypto_tfm_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) struct omap_des_dev *dd = ctx->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct dma_async_tx_descriptor *tx_in, *tx_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) if (dd->pio_only) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) scatterwalk_start(&dd->in_walk, dd->in_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) scatterwalk_start(&dd->out_walk, dd->out_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* Enable DATAIN interrupt and let it take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) care of the rest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) memset(&cfg, 0, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) cfg.src_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) cfg.dst_addr = dd->phys_base + DES_REG_DATA_N(dd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) cfg.src_maxburst = DST_MAXBURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) cfg.dst_maxburst = DST_MAXBURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) if (!tx_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) dev_err(dd->dev, "IN prep_slave_sg() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* No callback necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) tx_in->callback_param = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg, out_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if (!tx_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) tx_out->callback = omap_des_dma_out_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) tx_out->callback_param = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dmaengine_submit(tx_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dmaengine_submit(tx_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dma_async_issue_pending(dd->dma_lch_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) dma_async_issue_pending(dd->dma_lch_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) /* start DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) dd->pdata->trigger(dd, dd->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) static int omap_des_crypt_dma_start(struct omap_des_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct crypto_tfm *tfm = crypto_skcipher_tfm(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) crypto_skcipher_reqtfm(dd->req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) pr_debug("total: %zd\n", dd->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) if (!dd->pio_only) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) dev_err(dd->dev, "dma_map_sg() error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) dev_err(dd->dev, "dma_map_sg() error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) err = omap_des_crypt_dma(tfm, dd->in_sg, dd->out_sg, dd->in_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) dd->out_sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) if (err && !dd->pio_only) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) static void omap_des_finish_req(struct omap_des_dev *dd, int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct skcipher_request *req = dd->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) pr_debug("err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) crypto_finalize_skcipher_request(dd->engine, req, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pm_runtime_mark_last_busy(dd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) pm_runtime_put_autosuspend(dd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static int omap_des_crypt_dma_stop(struct omap_des_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) pr_debug("total: %zd\n", dd->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) omap_des_dma_stop(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) dmaengine_terminate_all(dd->dma_lch_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dmaengine_terminate_all(dd->dma_lch_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) static int omap_des_handle_queue(struct omap_des_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) return crypto_transfer_skcipher_request_to_engine(dd->engine, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) static int omap_des_prepare_req(struct crypto_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) void *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) struct omap_des_ctx *ctx = crypto_skcipher_ctx(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct omap_des_dev *dd = omap_des_find_dev(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct omap_des_reqctx *rctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* assign new request to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) dd->req = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) dd->total = req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) dd->total_save = req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) dd->in_sg = req->src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) dd->out_sg = req->dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) dd->orig_out = req->dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) flags = OMAP_CRYPTO_COPY_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) if (req->src == req->dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) flags |= OMAP_CRYPTO_FORCE_COPY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) ret = omap_crypto_align_sg(&dd->in_sg, dd->total, DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) &dd->in_sgl, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) ret = omap_crypto_align_sg(&dd->out_sg, dd->total, DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) &dd->out_sgl, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) if (dd->in_sg_len < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) return dd->in_sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) if (dd->out_sg_len < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) return dd->out_sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) ctx = crypto_skcipher_ctx(crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) rctx->mode &= FLAGS_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) dd->ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) ctx->dd = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) return omap_des_write_ctrl(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) static int omap_des_crypt_req(struct crypto_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) void *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct omap_des_ctx *ctx = crypto_skcipher_ctx(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) struct omap_des_dev *dd = omap_des_find_dev(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) return omap_des_crypt_dma_start(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) static void omap_des_done_task(unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct omap_des_dev *dd = (struct omap_des_dev *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) pr_debug("enter done_task\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) if (!dd->pio_only) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) omap_des_crypt_dma_stop(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) omap_crypto_cleanup(&dd->in_sgl, NULL, 0, dd->total_save,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) FLAGS_IN_DATA_ST_SHIFT, dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) omap_crypto_cleanup(&dd->out_sgl, dd->orig_out, 0, dd->total_save,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) if ((dd->flags & FLAGS_CBC) && dd->req->iv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) for (i = 0; i < 2; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) ((u32 *)dd->req->iv)[i] =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) omap_des_read(dd, DES_REG_IV(dd, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) omap_des_finish_req(dd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) pr_debug("exit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static int omap_des_crypt(struct skcipher_request *req, unsigned long mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) struct omap_des_ctx *ctx = crypto_skcipher_ctx(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) struct omap_des_reqctx *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) struct omap_des_dev *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) !!(mode & FLAGS_ENCRYPT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) !!(mode & FLAGS_CBC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) if (!req->cryptlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) if (!IS_ALIGNED(req->cryptlen, DES_BLOCK_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) dd = omap_des_find_dev(ctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) rctx->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) return omap_des_handle_queue(dd, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /* ********************** ALG API ************************************ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) static int omap_des_setkey(struct crypto_skcipher *cipher, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) pr_debug("enter, keylen: %d\n", keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) err = verify_skcipher_des_key(cipher, key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) ctx->keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) static int omap_des3_setkey(struct crypto_skcipher *cipher, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct omap_des_ctx *ctx = crypto_skcipher_ctx(cipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) pr_debug("enter, keylen: %d\n", keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) err = verify_skcipher_des3_key(cipher, key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) ctx->keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) static int omap_des_ecb_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) return omap_des_crypt(req, FLAGS_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static int omap_des_ecb_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return omap_des_crypt(req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static int omap_des_cbc_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) return omap_des_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) static int omap_des_cbc_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) return omap_des_crypt(req, FLAGS_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static int omap_des_prepare_req(struct crypto_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) void *areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static int omap_des_crypt_req(struct crypto_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) void *areq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) static int omap_des_init_tfm(struct crypto_skcipher *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct omap_des_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) pr_debug("enter\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_des_reqctx));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) ctx->enginectx.op.prepare_request = omap_des_prepare_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) ctx->enginectx.op.unprepare_request = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) ctx->enginectx.op.do_one_request = omap_des_crypt_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /* ********************** ALGS ************************************ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) static struct skcipher_alg algs_ecb_cbc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) .base.cra_name = "ecb(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .base.cra_driver_name = "ecb-des-omap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .base.cra_priority = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) CRYPTO_ALG_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) .base.cra_ctxsize = sizeof(struct omap_des_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .setkey = omap_des_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .encrypt = omap_des_ecb_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) .decrypt = omap_des_ecb_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .init = omap_des_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .base.cra_name = "cbc(des)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) .base.cra_driver_name = "cbc-des-omap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .base.cra_priority = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) CRYPTO_ALG_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .base.cra_blocksize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .base.cra_ctxsize = sizeof(struct omap_des_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) .min_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) .max_keysize = DES_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .ivsize = DES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .setkey = omap_des_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .encrypt = omap_des_cbc_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .decrypt = omap_des_cbc_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .init = omap_des_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .base.cra_name = "ecb(des3_ede)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .base.cra_driver_name = "ecb-des3-omap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .base.cra_priority = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) CRYPTO_ALG_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .base.cra_ctxsize = sizeof(struct omap_des_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .min_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .max_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) .setkey = omap_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) .encrypt = omap_des_ecb_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) .decrypt = omap_des_ecb_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) .init = omap_des_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) .base.cra_name = "cbc(des3_ede)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) .base.cra_driver_name = "cbc-des3-omap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) .base.cra_priority = 100,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) CRYPTO_ALG_ASYNC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .base.cra_blocksize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .base.cra_ctxsize = sizeof(struct omap_des_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .min_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .max_keysize = DES3_EDE_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .ivsize = DES3_EDE_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .setkey = omap_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .encrypt = omap_des_cbc_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .decrypt = omap_des_cbc_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .init = omap_des_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) static struct omap_des_algs_info omap_des_algs_info_ecb_cbc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) .algs_list = algs_ecb_cbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) .size = ARRAY_SIZE(algs_ecb_cbc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) static const struct omap_des_pdata omap_des_pdata_omap4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .algs_info = omap_des_algs_info_ecb_cbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .algs_info_size = ARRAY_SIZE(omap_des_algs_info_ecb_cbc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) .trigger = omap_des_dma_trigger_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) .key_ofs = 0x14,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) .iv_ofs = 0x18,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) .ctrl_ofs = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .data_ofs = 0x28,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .rev_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .mask_ofs = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .irq_status_ofs = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .irq_enable_ofs = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .dma_enable_in = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .dma_enable_out = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .major_mask = 0x0700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .major_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .minor_mask = 0x003f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .minor_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) static irqreturn_t omap_des_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) struct omap_des_dev *dd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u32 status, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) u32 *src, *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) status = omap_des_read(dd, DES_REG_IRQ_STATUS(dd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) if (status & DES_REG_IRQ_DATA_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) BUG_ON(!dd->in_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) BUG_ON(_calc_walked(in) > dd->in_sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) src = sg_virt(dd->in_sg) + _calc_walked(in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) for (i = 0; i < DES_BLOCK_WORDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) omap_des_write(dd, DES_REG_DATA_N(dd, i), *src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) scatterwalk_advance(&dd->in_walk, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) if (dd->in_sg->length == _calc_walked(in)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) dd->in_sg = sg_next(dd->in_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) if (dd->in_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) scatterwalk_start(&dd->in_walk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) dd->in_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) src = sg_virt(dd->in_sg) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) _calc_walked(in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) /* Clear IRQ status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) status &= ~DES_REG_IRQ_DATA_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) /* Enable DATA_OUT interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) } else if (status & DES_REG_IRQ_DATA_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) BUG_ON(!dd->out_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) BUG_ON(_calc_walked(out) > dd->out_sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dst = sg_virt(dd->out_sg) + _calc_walked(out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) for (i = 0; i < DES_BLOCK_WORDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) *dst = omap_des_read(dd, DES_REG_DATA_N(dd, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) scatterwalk_advance(&dd->out_walk, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) if (dd->out_sg->length == _calc_walked(out)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) dd->out_sg = sg_next(dd->out_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) if (dd->out_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) scatterwalk_start(&dd->out_walk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) dd->out_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) dst = sg_virt(dd->out_sg) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) _calc_walked(out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) BUG_ON(dd->total < DES_BLOCK_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dd->total -= DES_BLOCK_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) /* Clear IRQ status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) status &= ~DES_REG_IRQ_DATA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) omap_des_write(dd, DES_REG_IRQ_STATUS(dd), status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) if (!dd->total)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /* All bytes read! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) tasklet_schedule(&dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) /* Enable DATA_IN interrupt for next block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) omap_des_write(dd, DES_REG_IRQ_ENABLE(dd), 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) static const struct of_device_id omap_des_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) .compatible = "ti,omap4-des",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) .data = &omap_des_pdata_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) MODULE_DEVICE_TABLE(of, omap_des_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) static int omap_des_get_of(struct omap_des_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) dd->pdata = of_device_get_match_data(&pdev->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) if (!dd->pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) dev_err(&pdev->dev, "no compatible OF match\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) static int omap_des_get_of(struct omap_des_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) static int omap_des_get_pdev(struct omap_des_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) /* non-DT devices get pdata from pdev */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) dd->pdata = pdev->dev.platform_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) static int omap_des_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) struct omap_des_dev *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct skcipher_alg *algp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) struct resource *res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) int err = -ENOMEM, i, j, irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) dd = devm_kzalloc(dev, sizeof(struct omap_des_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (dd == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dev_err(dev, "unable to alloc data struct.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) goto err_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) dd->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) platform_set_drvdata(pdev, dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) if (!res) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) dev_err(dev, "no MEM resource info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) goto err_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) err = (dev->of_node) ? omap_des_get_of(dd, pdev) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) omap_des_get_pdev(dd, pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) goto err_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) dd->io_base = devm_ioremap_resource(dev, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) if (IS_ERR(dd->io_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) err = PTR_ERR(dd->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) goto err_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) dd->phys_base = res->start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) pm_runtime_use_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) err = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) dev_err(dd->dev, "%s: failed to get_sync(%d)\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) goto err_get;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) omap_des_dma_stop(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) reg = omap_des_read(dd, DES_REG_REV(dd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) dev_info(dev, "OMAP DES hw accel rev: %u.%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) tasklet_init(&dd->done_task, omap_des_done_task, (unsigned long)dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) err = omap_des_dma_init(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) if (err == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) } else if (err && DES_REG_IRQ_STATUS(dd) && DES_REG_IRQ_ENABLE(dd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) dd->pio_only = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) err = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) err = devm_request_irq(dev, irq, omap_des_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) dev_name(dev), dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) dev_err(dev, "Unable to grab omap-des IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) INIT_LIST_HEAD(&dd->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) spin_lock_bh(&list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) list_add_tail(&dd->list, &dev_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) spin_unlock_bh(&list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) /* Initialize des crypto engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) dd->engine = crypto_engine_alloc_init(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) if (!dd->engine) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) goto err_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) err = crypto_engine_start(dd->engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) goto err_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) for (i = 0; i < dd->pdata->algs_info_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) algp = &dd->pdata->algs_info[i].algs_list[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) pr_debug("reg alg: %s\n", algp->base.cra_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) err = crypto_register_skcipher(algp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) goto err_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) dd->pdata->algs_info[i].registered++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) err_algs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) crypto_unregister_skcipher(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) &dd->pdata->algs_info[i].algs_list[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) err_engine:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) if (dd->engine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) crypto_engine_exit(dd->engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) omap_des_dma_cleanup(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) tasklet_kill(&dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) err_get:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) err_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) dd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) err_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) dev_err(dev, "initialization failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) static int omap_des_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) struct omap_des_dev *dd = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) spin_lock_bh(&list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) list_del(&dd->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) spin_unlock_bh(&list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) crypto_unregister_skcipher(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) &dd->pdata->algs_info[i].algs_list[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) tasklet_kill(&dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) omap_des_dma_cleanup(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) pm_runtime_disable(dd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) dd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) static int omap_des_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) static int omap_des_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) err = pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) pm_runtime_put_noidle(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dev_err(dev, "%s: failed to get_sync(%d)\n", __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) static SIMPLE_DEV_PM_OPS(omap_des_pm_ops, omap_des_suspend, omap_des_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) static struct platform_driver omap_des_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) .probe = omap_des_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) .remove = omap_des_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) .name = "omap-des",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) .pm = &omap_des_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) .of_match_table = of_match_ptr(omap_des_of_match),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) module_platform_driver(omap_des_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) MODULE_DESCRIPTION("OMAP DES hw acceleration support.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) MODULE_AUTHOR("Joel Fernandes <joelf@ti.com>");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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