^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Cryptographic API.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Support for OMAP AES HW acceleration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * Copyright (c) 2010 Nokia Corporation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * Author: Dmitry Kasatkin <dmitry.kasatkin@nokia.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * Copyright (c) 2011 Texas Instruments Incorporated
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define pr_fmt(fmt) "%20s: " fmt, __func__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define prn(num) pr_debug(#num "=%d\n", num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define prx(num) pr_debug(#num "=%x\n", num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/err.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/errno.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <linux/dmaengine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #include <linux/of.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #include <linux/of_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #include <linux/of_address.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #include <linux/crypto.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #include <crypto/scatterwalk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #include <crypto/aes.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #include <crypto/gcm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #include <crypto/engine.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #include <crypto/internal/skcipher.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #include <crypto/internal/aead.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #include "omap-crypto.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #include "omap-aes.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* keep registered devices data here */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) static LIST_HEAD(dev_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) static DEFINE_SPINLOCK(list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) static int aes_fallback_sz = 200;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define omap_aes_read(dd, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) ({ \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) int _read_ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) _read_ret = __raw_readl(dd->io_base + offset); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) pr_debug("omap_aes_read(" #offset "=%#x)= %#x\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) offset, _read_ret); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) _read_ret; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) })
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) inline u32 omap_aes_read(struct omap_aes_dev *dd, u32 offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) return __raw_readl(dd->io_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #ifdef DEBUG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define omap_aes_write(dd, offset, value) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) pr_debug("omap_aes_write(" #offset "=%#x) value=%#x\n", \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) offset, value); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) __raw_writel(value, dd->io_base + offset); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) inline void omap_aes_write(struct omap_aes_dev *dd, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) u32 value)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) __raw_writel(value, dd->io_base + offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) static inline void omap_aes_write_mask(struct omap_aes_dev *dd, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) u32 value, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) val = omap_aes_read(dd, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) val &= ~mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) val |= value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) omap_aes_write(dd, offset, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) static void omap_aes_write_n(struct omap_aes_dev *dd, u32 offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) u32 *value, int count)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) for (; count--; value++, offset += 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) omap_aes_write(dd, offset, *value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) static int omap_aes_hw_init(struct omap_aes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) if (!(dd->flags & FLAGS_INIT)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) dd->flags |= FLAGS_INIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) dd->err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) err = pm_runtime_resume_and_get(dd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) dev_err(dd->dev, "failed to get sync: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) void omap_aes_clear_copy_flags(struct omap_aes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_IN_DATA_ST_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_OUT_DATA_ST_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) dd->flags &= ~(OMAP_CRYPTO_COPY_MASK << FLAGS_ASSOC_DATA_ST_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) int omap_aes_write_ctrl(struct omap_aes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) struct omap_aes_reqctx *rctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) unsigned int key32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) err = omap_aes_hw_init(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) key32 = dd->ctx->keylen / sizeof(u32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* RESET the key as previous HASH keys should not get affected*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) if (dd->flags & FLAGS_GCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) for (i = 0; i < 0x40; i = i + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) omap_aes_write(dd, i, 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) for (i = 0; i < key32; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) omap_aes_write(dd, AES_REG_KEY(dd, i),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) (__force u32)cpu_to_le32(dd->ctx->key[i]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) if ((dd->flags & (FLAGS_CBC | FLAGS_CTR)) && dd->req->iv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) omap_aes_write_n(dd, AES_REG_IV(dd, 0), (void *)dd->req->iv, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) if ((dd->flags & (FLAGS_GCM)) && dd->aead_req->iv) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) rctx = aead_request_ctx(dd->aead_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) omap_aes_write_n(dd, AES_REG_IV(dd, 0), (u32 *)rctx->iv, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) val = FLD_VAL(((dd->ctx->keylen >> 3) - 1), 4, 3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) if (dd->flags & FLAGS_CBC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) val |= AES_REG_CTRL_CBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) if (dd->flags & (FLAGS_CTR | FLAGS_GCM))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) val |= AES_REG_CTRL_CTR | AES_REG_CTRL_CTR_WIDTH_128;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) if (dd->flags & FLAGS_GCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) val |= AES_REG_CTRL_GCM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) if (dd->flags & FLAGS_ENCRYPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) val |= AES_REG_CTRL_DIRECTION;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) omap_aes_write_mask(dd, AES_REG_CTRL(dd), val, AES_REG_CTRL_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) static void omap_aes_dma_trigger_omap2(struct omap_aes_dev *dd, int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) u32 mask, val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) val = dd->pdata->dma_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) if (dd->dma_lch_out != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) val |= dd->pdata->dma_enable_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) if (dd->dma_lch_in != NULL)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) val |= dd->pdata->dma_enable_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) dd->pdata->dma_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) omap_aes_write_mask(dd, AES_REG_MASK(dd), val, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) static void omap_aes_dma_trigger_omap4(struct omap_aes_dev *dd, int length)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) omap_aes_write(dd, AES_REG_LENGTH_N(0), length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) omap_aes_write(dd, AES_REG_LENGTH_N(1), 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) if (dd->flags & FLAGS_GCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) omap_aes_write(dd, AES_REG_A_LEN, dd->assoc_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) omap_aes_dma_trigger_omap2(dd, length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) static void omap_aes_dma_stop(struct omap_aes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) u32 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) mask = dd->pdata->dma_enable_out | dd->pdata->dma_enable_in |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) dd->pdata->dma_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) omap_aes_write_mask(dd, AES_REG_MASK(dd), 0, mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) struct omap_aes_dev *omap_aes_find_dev(struct omap_aes_reqctx *rctx)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) struct omap_aes_dev *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) spin_lock_bh(&list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) dd = list_first_entry(&dev_list, struct omap_aes_dev, list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) list_move_tail(&dd->list, &dev_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) rctx->dd = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) spin_unlock_bh(&list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) return dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) static void omap_aes_dma_out_callback(void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) struct omap_aes_dev *dd = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* dma_lch_out - completed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) tasklet_schedule(&dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) static int omap_aes_dma_init(struct omap_aes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) dd->dma_lch_out = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) dd->dma_lch_in = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) dd->dma_lch_in = dma_request_chan(dd->dev, "rx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) if (IS_ERR(dd->dma_lch_in)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) dev_err(dd->dev, "Unable to request in DMA channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) return PTR_ERR(dd->dma_lch_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) dd->dma_lch_out = dma_request_chan(dd->dev, "tx");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) if (IS_ERR(dd->dma_lch_out)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) dev_err(dd->dev, "Unable to request out DMA channel\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) err = PTR_ERR(dd->dma_lch_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) goto err_dma_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) err_dma_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) dma_release_channel(dd->dma_lch_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) static void omap_aes_dma_cleanup(struct omap_aes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) if (dd->pio_only)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) dma_release_channel(dd->dma_lch_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) dma_release_channel(dd->dma_lch_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) static int omap_aes_crypt_dma(struct omap_aes_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct scatterlist *in_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) struct scatterlist *out_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) int in_sg_len, int out_sg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) struct dma_async_tx_descriptor *tx_in, *tx_out = NULL, *cb_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) struct dma_slave_config cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) if (dd->pio_only) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) scatterwalk_start(&dd->in_walk, dd->in_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) if (out_sg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) scatterwalk_start(&dd->out_walk, dd->out_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) /* Enable DATAIN interrupt and let it take
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) care of the rest */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) dma_sync_sg_for_device(dd->dev, dd->in_sg, in_sg_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) memset(&cfg, 0, sizeof(cfg));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) cfg.src_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cfg.dst_addr = dd->phys_base + AES_REG_DATA_N(dd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) cfg.src_maxburst = DST_MAXBURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) cfg.dst_maxburst = DST_MAXBURST;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) ret = dmaengine_slave_config(dd->dma_lch_in, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) dev_err(dd->dev, "can't configure IN dmaengine slave: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) tx_in = dmaengine_prep_slave_sg(dd->dma_lch_in, in_sg, in_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) DMA_MEM_TO_DEV,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) if (!tx_in) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) dev_err(dd->dev, "IN prep_slave_sg() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* No callback necessary */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) tx_in->callback_param = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) tx_in->callback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) /* OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) if (out_sg_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) ret = dmaengine_slave_config(dd->dma_lch_out, &cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) dev_err(dd->dev, "can't configure OUT dmaengine slave: %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) tx_out = dmaengine_prep_slave_sg(dd->dma_lch_out, out_sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) out_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) DMA_DEV_TO_MEM,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) if (!tx_out) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) dev_err(dd->dev, "OUT prep_slave_sg() failed\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) cb_desc = tx_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) cb_desc = tx_in;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) if (dd->flags & FLAGS_GCM)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) cb_desc->callback = omap_aes_gcm_dma_out_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) cb_desc->callback = omap_aes_dma_out_callback;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) cb_desc->callback_param = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) dmaengine_submit(tx_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) if (tx_out)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) dmaengine_submit(tx_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) dma_async_issue_pending(dd->dma_lch_in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (out_sg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) dma_async_issue_pending(dd->dma_lch_out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) /* start DMA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) dd->pdata->trigger(dd, dd->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) int omap_aes_crypt_dma_start(struct omap_aes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) pr_debug("total: %zu\n", dd->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!dd->pio_only) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) err = dma_map_sg(dd->dev, dd->in_sg, dd->in_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) dev_err(dd->dev, "dma_map_sg() error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) if (dd->out_sg_len) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) err = dma_map_sg(dd->dev, dd->out_sg, dd->out_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (!err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) dev_err(dd->dev, "dma_map_sg() error\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) err = omap_aes_crypt_dma(dd, dd->in_sg, dd->out_sg, dd->in_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) dd->out_sg_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) if (err && !dd->pio_only) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) if (dd->out_sg_len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static void omap_aes_finish_req(struct omap_aes_dev *dd, int err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct skcipher_request *req = dd->req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) pr_debug("err: %d\n", err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) crypto_finalize_skcipher_request(dd->engine, req, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) pm_runtime_mark_last_busy(dd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) pm_runtime_put_autosuspend(dd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) int omap_aes_crypt_dma_stop(struct omap_aes_dev *dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) pr_debug("total: %zu\n", dd->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) omap_aes_dma_stop(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) static int omap_aes_handle_queue(struct omap_aes_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) if (req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) return crypto_transfer_skcipher_request_to_engine(dd->engine, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) static int omap_aes_prepare_req(struct crypto_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) void *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) struct omap_aes_ctx *ctx = crypto_skcipher_ctx(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct omap_aes_dev *dd = rctx->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) u16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /* assign new request to device */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) dd->req = req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) dd->total = req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) dd->total_save = req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) dd->in_sg = req->src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) dd->out_sg = req->dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) dd->orig_out = req->dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) flags = OMAP_CRYPTO_COPY_DATA;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) if (req->src == req->dst)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) flags |= OMAP_CRYPTO_FORCE_COPY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) ret = omap_crypto_align_sg(&dd->in_sg, dd->total, AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) dd->in_sgl, flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) FLAGS_IN_DATA_ST_SHIFT, &dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ret = omap_crypto_align_sg(&dd->out_sg, dd->total, AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) &dd->out_sgl, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) FLAGS_OUT_DATA_ST_SHIFT, &dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dd->in_sg_len = sg_nents_for_len(dd->in_sg, dd->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) if (dd->in_sg_len < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) return dd->in_sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) dd->out_sg_len = sg_nents_for_len(dd->out_sg, dd->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) if (dd->out_sg_len < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return dd->out_sg_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) rctx->mode &= FLAGS_MODE_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) dd->flags = (dd->flags & ~FLAGS_MODE_MASK) | rctx->mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) dd->ctx = ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) rctx->dd = dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) return omap_aes_write_ctrl(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) static int omap_aes_crypt_req(struct crypto_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) void *areq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) struct skcipher_request *req = container_of(areq, struct skcipher_request, base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) struct omap_aes_dev *dd = rctx->dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) return omap_aes_crypt_dma_start(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) static void omap_aes_copy_ivout(struct omap_aes_dev *dd, u8 *ivbuf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) for (i = 0; i < 4; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) ((u32 *)ivbuf)[i] = omap_aes_read(dd, AES_REG_IV(dd, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) static void omap_aes_done_task(unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) struct omap_aes_dev *dd = (struct omap_aes_dev *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) pr_debug("enter done_task\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) if (!dd->pio_only) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) dma_sync_sg_for_device(dd->dev, dd->out_sg, dd->out_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) dma_unmap_sg(dd->dev, dd->in_sg, dd->in_sg_len, DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) dma_unmap_sg(dd->dev, dd->out_sg, dd->out_sg_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) omap_aes_crypt_dma_stop(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) omap_crypto_cleanup(dd->in_sg, NULL, 0, dd->total_save,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) FLAGS_IN_DATA_ST_SHIFT, dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) omap_crypto_cleanup(dd->out_sg, dd->orig_out, 0, dd->total_save,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) FLAGS_OUT_DATA_ST_SHIFT, dd->flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /* Update IV output */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) if (dd->flags & (FLAGS_CBC | FLAGS_CTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) omap_aes_copy_ivout(dd, dd->req->iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) omap_aes_finish_req(dd, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) pr_debug("exit\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) static int omap_aes_crypt(struct skcipher_request *req, unsigned long mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) struct omap_aes_ctx *ctx = crypto_skcipher_ctx(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) struct omap_aes_reqctx *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) struct omap_aes_dev *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) if ((req->cryptlen % AES_BLOCK_SIZE) && !(mode & FLAGS_CTR))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pr_debug("nbytes: %d, enc: %d, cbc: %d\n", req->cryptlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) !!(mode & FLAGS_ENCRYPT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) !!(mode & FLAGS_CBC));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) if (req->cryptlen < aes_fallback_sz) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) skcipher_request_set_tfm(&rctx->fallback_req, ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) skcipher_request_set_callback(&rctx->fallback_req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) req->base.flags,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) req->base.complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) req->base.data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) skcipher_request_set_crypt(&rctx->fallback_req, req->src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) req->dst, req->cryptlen, req->iv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (mode & FLAGS_ENCRYPT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) ret = crypto_skcipher_encrypt(&rctx->fallback_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) ret = crypto_skcipher_decrypt(&rctx->fallback_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) dd = omap_aes_find_dev(rctx);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) rctx->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) return omap_aes_handle_queue(dd, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* ********************** ALG API ************************************ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) static int omap_aes_setkey(struct crypto_skcipher *tfm, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) unsigned int keylen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) if (keylen != AES_KEYSIZE_128 && keylen != AES_KEYSIZE_192 &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) keylen != AES_KEYSIZE_256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) pr_debug("enter, keylen: %d\n", keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) memcpy(ctx->key, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) ctx->keylen = keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) crypto_skcipher_clear_flags(ctx->fallback, CRYPTO_TFM_REQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) crypto_skcipher_set_flags(ctx->fallback, tfm->base.crt_flags &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) CRYPTO_TFM_REQ_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) ret = crypto_skcipher_setkey(ctx->fallback, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static int omap_aes_ecb_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) return omap_aes_crypt(req, FLAGS_ENCRYPT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) static int omap_aes_ecb_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) return omap_aes_crypt(req, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) static int omap_aes_cbc_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) static int omap_aes_cbc_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) return omap_aes_crypt(req, FLAGS_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) static int omap_aes_ctr_encrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) return omap_aes_crypt(req, FLAGS_ENCRYPT | FLAGS_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) static int omap_aes_ctr_decrypt(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) return omap_aes_crypt(req, FLAGS_CTR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) static int omap_aes_prepare_req(struct crypto_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) void *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static int omap_aes_crypt_req(struct crypto_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) void *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) static int omap_aes_init_tfm(struct crypto_skcipher *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) const char *name = crypto_tfm_alg_name(&tfm->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) struct crypto_skcipher *blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) blk = crypto_alloc_skcipher(name, 0, CRYPTO_ALG_NEED_FALLBACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) if (IS_ERR(blk))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) return PTR_ERR(blk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) ctx->fallback = blk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) crypto_skcipher_set_reqsize(tfm, sizeof(struct omap_aes_reqctx) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) crypto_skcipher_reqsize(blk));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) ctx->enginectx.op.prepare_request = omap_aes_prepare_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) ctx->enginectx.op.unprepare_request = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) ctx->enginectx.op.do_one_request = omap_aes_crypt_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) static void omap_aes_exit_tfm(struct crypto_skcipher *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) struct omap_aes_ctx *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) if (ctx->fallback)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) crypto_free_skcipher(ctx->fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) ctx->fallback = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /* ********************** ALGS ************************************ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static struct skcipher_alg algs_ecb_cbc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) .base.cra_name = "ecb(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) .base.cra_driver_name = "ecb-aes-omap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) .base.cra_priority = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) .base.cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) .setkey = omap_aes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) .encrypt = omap_aes_ecb_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) .decrypt = omap_aes_ecb_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) .init = omap_aes_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) .exit = omap_aes_exit_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) .base.cra_name = "cbc(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) .base.cra_driver_name = "cbc-aes-omap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) .base.cra_priority = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) .base.cra_blocksize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) .setkey = omap_aes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) .encrypt = omap_aes_cbc_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) .decrypt = omap_aes_cbc_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) .init = omap_aes_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) .exit = omap_aes_exit_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) static struct skcipher_alg algs_ctr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) .base.cra_name = "ctr(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) .base.cra_driver_name = "ctr-aes-omap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) .base.cra_priority = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) .base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) CRYPTO_ALG_NEED_FALLBACK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) .base.cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) .base.cra_ctxsize = sizeof(struct omap_aes_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) .base.cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) .ivsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) .setkey = omap_aes_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) .encrypt = omap_aes_ctr_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) .decrypt = omap_aes_ctr_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) .init = omap_aes_init_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) .exit = omap_aes_exit_tfm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) .algs_list = algs_ecb_cbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) .size = ARRAY_SIZE(algs_ecb_cbc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) static struct aead_alg algs_aead_gcm[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) .cra_name = "gcm(aes)",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) .cra_driver_name = "gcm-aes-omap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) .cra_priority = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) CRYPTO_ALG_KERN_DRIVER_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) .cra_alignmask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) .init = omap_aes_gcm_cra_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) .ivsize = GCM_AES_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) .setkey = omap_aes_gcm_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) .setauthsize = omap_aes_gcm_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) .encrypt = omap_aes_gcm_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) .decrypt = omap_aes_gcm_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) .base = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) .cra_name = "rfc4106(gcm(aes))",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) .cra_driver_name = "rfc4106-gcm-aes-omap",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) .cra_priority = 300,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) .cra_flags = CRYPTO_ALG_ASYNC |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) CRYPTO_ALG_KERN_DRIVER_ONLY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) .cra_blocksize = 1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) .cra_ctxsize = sizeof(struct omap_aes_gcm_ctx),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) .cra_alignmask = 0xf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) .cra_module = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) .init = omap_aes_gcm_cra_init,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) .maxauthsize = AES_BLOCK_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) .ivsize = GCM_RFC4106_IV_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) .setkey = omap_aes_4106gcm_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) .setauthsize = omap_aes_4106gcm_setauthsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) .encrypt = omap_aes_4106gcm_encrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) .decrypt = omap_aes_4106gcm_decrypt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) static struct omap_aes_aead_algs omap_aes_aead_info = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) .algs_list = algs_aead_gcm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) .size = ARRAY_SIZE(algs_aead_gcm),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static const struct omap_aes_pdata omap_aes_pdata_omap2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) .algs_info = omap_aes_algs_info_ecb_cbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) .trigger = omap_aes_dma_trigger_omap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) .key_ofs = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) .iv_ofs = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) .ctrl_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) .data_ofs = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) .rev_ofs = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) .mask_ofs = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) .dma_enable_in = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) .dma_enable_out = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) .dma_start = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) .major_mask = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) .major_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) .minor_mask = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) .minor_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #ifdef CONFIG_OF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) static struct omap_aes_algs_info omap_aes_algs_info_ecb_cbc_ctr[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) .algs_list = algs_ecb_cbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) .size = ARRAY_SIZE(algs_ecb_cbc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) .algs_list = algs_ctr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) .size = ARRAY_SIZE(algs_ctr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) static const struct omap_aes_pdata omap_aes_pdata_omap3 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) .trigger = omap_aes_dma_trigger_omap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) .key_ofs = 0x1c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) .iv_ofs = 0x20,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) .ctrl_ofs = 0x30,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) .data_ofs = 0x34,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) .rev_ofs = 0x44,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) .mask_ofs = 0x48,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) .dma_enable_in = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) .dma_enable_out = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) .dma_start = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) .major_mask = 0xf0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) .major_shift = 4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) .minor_mask = 0x0f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) .minor_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) static const struct omap_aes_pdata omap_aes_pdata_omap4 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) .algs_info = omap_aes_algs_info_ecb_cbc_ctr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) .algs_info_size = ARRAY_SIZE(omap_aes_algs_info_ecb_cbc_ctr),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) .aead_algs_info = &omap_aes_aead_info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) .trigger = omap_aes_dma_trigger_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) .key_ofs = 0x3c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) .iv_ofs = 0x40,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) .ctrl_ofs = 0x50,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) .data_ofs = 0x60,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) .rev_ofs = 0x80,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) .mask_ofs = 0x84,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) .irq_status_ofs = 0x8c,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) .irq_enable_ofs = 0x90,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) .dma_enable_in = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) .dma_enable_out = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) .major_mask = 0x0700,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) .major_shift = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) .minor_mask = 0x003f,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) .minor_shift = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) static irqreturn_t omap_aes_irq(int irq, void *dev_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) struct omap_aes_dev *dd = dev_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) u32 status, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) u32 *src, *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) status = omap_aes_read(dd, AES_REG_IRQ_STATUS(dd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) if (status & AES_REG_IRQ_DATA_IN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) BUG_ON(!dd->in_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) BUG_ON(_calc_walked(in) > dd->in_sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) src = sg_virt(dd->in_sg) + _calc_walked(in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) for (i = 0; i < AES_BLOCK_WORDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) omap_aes_write(dd, AES_REG_DATA_N(dd, i), *src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) scatterwalk_advance(&dd->in_walk, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) if (dd->in_sg->length == _calc_walked(in)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) dd->in_sg = sg_next(dd->in_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) if (dd->in_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) scatterwalk_start(&dd->in_walk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) dd->in_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) src = sg_virt(dd->in_sg) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) _calc_walked(in);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) /* Clear IRQ status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) status &= ~AES_REG_IRQ_DATA_IN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) /* Enable DATA_OUT interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) } else if (status & AES_REG_IRQ_DATA_OUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) BUG_ON(!dd->out_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) BUG_ON(_calc_walked(out) > dd->out_sg->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) dst = sg_virt(dd->out_sg) + _calc_walked(out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) for (i = 0; i < AES_BLOCK_WORDS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) *dst = omap_aes_read(dd, AES_REG_DATA_N(dd, i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) scatterwalk_advance(&dd->out_walk, 4);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) if (dd->out_sg->length == _calc_walked(out)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) dd->out_sg = sg_next(dd->out_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) if (dd->out_sg) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) scatterwalk_start(&dd->out_walk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) dd->out_sg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) dst = sg_virt(dd->out_sg) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) _calc_walked(out);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) dd->total -= min_t(size_t, AES_BLOCK_SIZE, dd->total);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) /* Clear IRQ status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) status &= ~AES_REG_IRQ_DATA_OUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) omap_aes_write(dd, AES_REG_IRQ_STATUS(dd), status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (!dd->total)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) /* All bytes read! */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) tasklet_schedule(&dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) /* Enable DATA_IN interrupt for next block */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) omap_aes_write(dd, AES_REG_IRQ_ENABLE(dd), 0x2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) static const struct of_device_id omap_aes_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) .compatible = "ti,omap2-aes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) .data = &omap_aes_pdata_omap2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) .compatible = "ti,omap3-aes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) .data = &omap_aes_pdata_omap3,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) .compatible = "ti,omap4-aes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) .data = &omap_aes_pdata_omap4,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) MODULE_DEVICE_TABLE(of, omap_aes_of_match);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) static int omap_aes_get_res_of(struct omap_aes_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) struct device *dev, struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) struct device_node *node = dev->of_node;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) dd->pdata = of_device_get_match_data(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) if (!dd->pdata) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) dev_err(dev, "no compatible OF match\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) err = of_address_to_resource(node, 0, res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) dev_err(dev, "can't translate OF node address\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) err = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static const struct of_device_id omap_aes_of_match[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) static int omap_aes_get_res_of(struct omap_aes_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) struct device *dev, struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) static int omap_aes_get_res_pdev(struct omap_aes_dev *dd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) struct platform_device *pdev, struct resource *res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) struct resource *r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) /* Get the base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) r = platform_get_resource(pdev, IORESOURCE_MEM, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) if (!r) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) dev_err(dev, "no MEM resource info\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) memcpy(res, r, sizeof(*res));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) /* Only OMAP2/3 can be non-DT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) dd->pdata = &omap_aes_pdata_omap2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) static ssize_t fallback_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) return sprintf(buf, "%d\n", aes_fallback_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) static ssize_t fallback_store(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) const char *buf, size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) ssize_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) status = kstrtol(buf, 0, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) /* HW accelerator only works with buffers > 9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) if (value < 9) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) dev_err(dev, "minimum fallback size 9\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) aes_fallback_sz = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) static ssize_t queue_len_show(struct device *dev, struct device_attribute *attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) char *buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) struct omap_aes_dev *dd = dev_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) return sprintf(buf, "%d\n", dd->engine->queue.max_qlen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static ssize_t queue_len_store(struct device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) struct device_attribute *attr, const char *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) size_t size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) struct omap_aes_dev *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) ssize_t status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) long value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) status = kstrtol(buf, 0, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) if (status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) return status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) if (value < 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) * Changing the queue size in fly is safe, if size becomes smaller
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) * than current size, it will just not accept new entries until
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) * it has shrank enough.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) spin_lock_bh(&list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) list_for_each_entry(dd, &dev_list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) spin_lock_irqsave(&dd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dd->engine->queue.max_qlen = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) dd->aead_queue.base.max_qlen = value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) spin_unlock_irqrestore(&dd->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) spin_unlock_bh(&list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) static DEVICE_ATTR_RW(queue_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) static DEVICE_ATTR_RW(fallback);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) static struct attribute *omap_aes_attrs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) &dev_attr_queue_len.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) &dev_attr_fallback.attr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) NULL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) static struct attribute_group omap_aes_attr_group = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) .attrs = omap_aes_attrs,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) static int omap_aes_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) struct omap_aes_dev *dd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) struct skcipher_alg *algp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) struct aead_alg *aalg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106) struct resource res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) int err = -ENOMEM, i, j, irq = -1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) u32 reg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) dd = devm_kzalloc(dev, sizeof(struct omap_aes_dev), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) if (dd == NULL) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) dev_err(dev, "unable to alloc data struct.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) goto err_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) dd->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) platform_set_drvdata(pdev, dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) aead_init_queue(&dd->aead_queue, OMAP_AES_QUEUE_LENGTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) err = (dev->of_node) ? omap_aes_get_res_of(dd, dev, &res) :
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) omap_aes_get_res_pdev(dd, pdev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) goto err_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) dd->io_base = devm_ioremap_resource(dev, &res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) if (IS_ERR(dd->io_base)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) err = PTR_ERR(dd->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) goto err_res;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) dd->phys_base = res.start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) pm_runtime_use_autosuspend(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) pm_runtime_set_autosuspend_delay(dev, DEFAULT_AUTOSUSPEND_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) pm_runtime_enable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) err = pm_runtime_resume_and_get(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) dev_err(dev, "%s: failed to get_sync(%d)\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) __func__, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) goto err_pm_disable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) omap_aes_dma_stop(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) reg = omap_aes_read(dd, AES_REG_REV(dd));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) dev_info(dev, "OMAP AES hw accel rev: %u.%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) (reg & dd->pdata->major_mask) >> dd->pdata->major_shift,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) (reg & dd->pdata->minor_mask) >> dd->pdata->minor_shift);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) tasklet_init(&dd->done_task, omap_aes_done_task, (unsigned long)dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) err = omap_aes_dma_init(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) if (err == -EPROBE_DEFER) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) } else if (err && AES_REG_IRQ_STATUS(dd) && AES_REG_IRQ_ENABLE(dd)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) dd->pio_only = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) irq = platform_get_irq(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (irq < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) err = irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) err = devm_request_irq(dev, irq, omap_aes_irq, 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) dev_name(dev), dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) dev_err(dev, "Unable to grab omap-aes IRQ\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) goto err_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) spin_lock_init(&dd->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) INIT_LIST_HEAD(&dd->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) spin_lock_bh(&list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) list_add_tail(&dd->list, &dev_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) spin_unlock_bh(&list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) /* Initialize crypto engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) dd->engine = crypto_engine_alloc_init(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) if (!dd->engine) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) goto err_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) err = crypto_engine_start(dd->engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) goto err_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) for (i = 0; i < dd->pdata->algs_info_size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (!dd->pdata->algs_info[i].registered) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) for (j = 0; j < dd->pdata->algs_info[i].size; j++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) algp = &dd->pdata->algs_info[i].algs_list[j];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) pr_debug("reg alg: %s\n", algp->base.cra_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) err = crypto_register_skcipher(algp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) goto err_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) dd->pdata->algs_info[i].registered++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) if (dd->pdata->aead_algs_info &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) !dd->pdata->aead_algs_info->registered) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) for (i = 0; i < dd->pdata->aead_algs_info->size; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) aalg = &dd->pdata->aead_algs_info->algs_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) pr_debug("reg alg: %s\n", aalg->base.cra_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) err = crypto_register_aead(aalg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) goto err_aead_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) dd->pdata->aead_algs_info->registered++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) err = sysfs_create_group(&dev->kobj, &omap_aes_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226) dev_err(dev, "could not create sysfs device attrs\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) goto err_aead_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) err_aead_algs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) aalg = &dd->pdata->aead_algs_info->algs_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) crypto_unregister_aead(aalg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) err_algs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) crypto_unregister_skcipher(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) &dd->pdata->algs_info[i].algs_list[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) err_engine:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) if (dd->engine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) crypto_engine_exit(dd->engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) omap_aes_dma_cleanup(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) err_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) tasklet_kill(&dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) err_pm_disable:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) pm_runtime_disable(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) err_res:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) dd = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) err_data:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) dev_err(dev, "initialization failed.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) static int omap_aes_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) struct omap_aes_dev *dd = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261) struct aead_alg *aalg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) int i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) if (!dd)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) spin_lock_bh(&list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) list_del(&dd->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) spin_unlock_bh(&list_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) for (i = dd->pdata->algs_info_size - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) for (j = dd->pdata->algs_info[i].registered - 1; j >= 0; j--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) crypto_unregister_skcipher(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) &dd->pdata->algs_info[i].algs_list[j]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275) dd->pdata->algs_info[i].registered--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) for (i = dd->pdata->aead_algs_info->registered - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) aalg = &dd->pdata->aead_algs_info->algs_list[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) crypto_unregister_aead(aalg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281) dd->pdata->aead_algs_info->registered--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) crypto_engine_exit(dd->engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) tasklet_kill(&dd->done_task);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) omap_aes_dma_cleanup(dd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) pm_runtime_disable(dd->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) sysfs_remove_group(&dd->dev->kobj, &omap_aes_attr_group);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) #ifdef CONFIG_PM_SLEEP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) static int omap_aes_suspend(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) pm_runtime_put_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) static int omap_aes_resume(struct device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) pm_runtime_get_sync(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) static SIMPLE_DEV_PM_OPS(omap_aes_pm_ops, omap_aes_suspend, omap_aes_resume);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) static struct platform_driver omap_aes_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313) .probe = omap_aes_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) .remove = omap_aes_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) .name = "omap-aes",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) .pm = &omap_aes_pm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) .of_match_table = omap_aes_of_match,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) module_platform_driver(omap_aes_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) MODULE_DESCRIPTION("OMAP AES hw acceleration support.");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) MODULE_AUTHOR("Dmitry Kasatkin");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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