Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Support for MediaTek cryptographic accelerator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (c) 2016 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * Author: Ryder Lee <ryder.lee@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #ifndef __MTK_REGS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define __MTK_REGS_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) /* HIA, Command Descriptor Ring Manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CDR_BASE_ADDR_LO(x)		(0x0 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CDR_BASE_ADDR_HI(x)		(0x4 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CDR_DATA_BASE_ADDR_LO(x)	(0x8 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CDR_DATA_BASE_ADDR_HI(x)	(0xC + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CDR_ACD_BASE_ADDR_LO(x)		(0x10 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CDR_ACD_BASE_ADDR_HI(x)		(0x14 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CDR_RING_SIZE(x)		(0x18 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define CDR_DESC_SIZE(x)		(0x1C + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CDR_CFG(x)			(0x20 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CDR_DMA_CFG(x)			(0x24 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CDR_THRESH(x)			(0x28 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CDR_PREP_COUNT(x)		(0x2C + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CDR_PROC_COUNT(x)		(0x30 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CDR_PREP_PNTR(x)		(0x34 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CDR_PROC_PNTR(x)		(0x38 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define CDR_STAT(x)			(0x3C + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* HIA, Result Descriptor Ring Manager */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define RDR_BASE_ADDR_LO(x)		(0x800 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define RDR_BASE_ADDR_HI(x)		(0x804 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define RDR_DATA_BASE_ADDR_LO(x)	(0x808 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define RDR_DATA_BASE_ADDR_HI(x)	(0x80C + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define RDR_ACD_BASE_ADDR_LO(x)		(0x810 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define RDR_ACD_BASE_ADDR_HI(x)		(0x814 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define RDR_RING_SIZE(x)		(0x818 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define RDR_DESC_SIZE(x)		(0x81C + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define RDR_CFG(x)			(0x820 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define RDR_DMA_CFG(x)			(0x824 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define RDR_THRESH(x)			(0x828 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define RDR_PREP_COUNT(x)		(0x82C + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define RDR_PROC_COUNT(x)		(0x830 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define RDR_PREP_PNTR(x)		(0x834 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define RDR_PROC_PNTR(x)		(0x838 + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define RDR_STAT(x)			(0x83C + ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) /* HIA, Ring AIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define AIC_POL_CTRL(x)			(0xE000 - ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define	AIC_TYPE_CTRL(x)		(0xE004 - ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define	AIC_ENABLE_CTRL(x)		(0xE008 - ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define	AIC_RAW_STAL(x)			(0xE00C - ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define	AIC_ENABLE_SET(x)		(0xE00C - ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define	AIC_ENABLED_STAT(x)		(0xE010 - ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define	AIC_ACK(x)			(0xE010 - ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define	AIC_ENABLE_CLR(x)		(0xE014 - ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define	AIC_OPTIONS(x)			(0xE018 - ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define	AIC_VERSION(x)			(0xE01C - ((x) << 12))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* HIA, Global AIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define AIC_G_POL_CTRL			0xF800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define AIC_G_TYPE_CTRL			0xF804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define AIC_G_ENABLE_CTRL		0xF808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define AIC_G_RAW_STAT			0xF80C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define AIC_G_ENABLE_SET		0xF80C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define AIC_G_ENABLED_STAT		0xF810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define AIC_G_ACK			0xF810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define AIC_G_ENABLE_CLR		0xF814
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define AIC_G_OPTIONS			0xF818
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define AIC_G_VERSION			0xF81C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* HIA, Data Fetch Engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define DFE_CFG				0xF000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define DFE_PRIO_0			0xF010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define DFE_PRIO_1			0xF014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define DFE_PRIO_2			0xF018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define DFE_PRIO_3			0xF01C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) /* HIA, Data Fetch Engine access monitoring for CDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define DFE_RING_REGION_LO(x)		(0xF080 + ((x) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define DFE_RING_REGION_HI(x)		(0xF084 + ((x) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* HIA, Data Fetch Engine thread control and status for thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define DFE_THR_CTRL			0xF200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define DFE_THR_STAT			0xF204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define DFE_THR_DESC_CTRL		0xF208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define DFE_THR_DESC_DPTR_LO		0xF210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define DFE_THR_DESC_DPTR_HI		0xF214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define DFE_THR_DESC_ACDPTR_LO		0xF218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define DFE_THR_DESC_ACDPTR_HI		0xF21C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) /* HIA, Data Store Engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define DSE_CFG				0xF400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define DSE_PRIO_0			0xF410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define DSE_PRIO_1			0xF414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define DSE_PRIO_2			0xF418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define DSE_PRIO_3			0xF41C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* HIA, Data Store Engine access monitoring for RDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DSE_RING_REGION_LO(x)		(0xF480 + ((x) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DSE_RING_REGION_HI(x)		(0xF484 + ((x) << 3))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* HIA, Data Store Engine thread control and status for thread */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DSE_THR_CTRL			0xF600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DSE_THR_STAT			0xF604
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DSE_THR_DESC_CTRL		0xF608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DSE_THR_DESC_DPTR_LO		0xF610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DSE_THR_DESC_DPTR_HI		0xF614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DSE_THR_DESC_S_DPTR_LO		0xF618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DSE_THR_DESC_S_DPTR_HI		0xF61C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define DSE_THR_ERROR_STAT		0xF620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* HIA Global */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HIA_MST_CTRL			0xFFF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HIA_OPTIONS			0xFFF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HIA_VERSION			0xFFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) /* Processing Engine Input Side, Processing Engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PE_IN_DBUF_THRESH		0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PE_IN_TBUF_THRESH		0x10100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Packet Engine Configuration / Status Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PE_TOKEN_CTRL_STAT		0x11000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PE_FUNCTION_EN			0x11004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PE_CONTEXT_CTRL			0x11008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PE_INTERRUPT_CTRL_STAT		0x11010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PE_CONTEXT_STAT			0x1100C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PE_OUT_TRANS_CTRL_STAT		0x11018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PE_OUT_BUF_CTRL			0x1101C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* Packet Engine PRNG Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PE_PRNG_STAT			0x11040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PE_PRNG_CTRL			0x11044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PE_PRNG_SEED_L			0x11048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PE_PRNG_SEED_H			0x1104C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PE_PRNG_KEY_0_L			0x11050
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define PE_PRNG_KEY_0_H			0x11054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define PE_PRNG_KEY_1_L			0x11058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define PE_PRNG_KEY_1_H			0x1105C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define PE_PRNG_RES_0			0x11060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define PE_PRNG_RES_1			0x11064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define PE_PRNG_RES_2			0x11068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define PE_PRNG_RES_3			0x1106C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define PE_PRNG_LFSR_L			0x11070
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define PE_PRNG_LFSR_H			0x11074
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) /* Packet Engine AIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define PE_EIP96_AIC_POL_CTRL		0x113C0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define PE_EIP96_AIC_TYPE_CTRL		0x113C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define PE_EIP96_AIC_ENABLE_CTRL	0x113C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define PE_EIP96_AIC_RAW_STAT		0x113CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define PE_EIP96_AIC_ENABLE_SET		0x113CC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define PE_EIP96_AIC_ENABLED_STAT	0x113D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define PE_EIP96_AIC_ACK		0x113D0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define PE_EIP96_AIC_ENABLE_CLR		0x113D4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define PE_EIP96_AIC_OPTIONS		0x113D8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define PE_EIP96_AIC_VERSION		0x113DC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* Packet Engine Options & Version Registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define PE_EIP96_OPTIONS		0x113F8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define PE_EIP96_VERSION		0x113FC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* Processing Engine Output Side */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define PE_OUT_DBUF_THRESH		0x11C00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define PE_OUT_TBUF_THRESH		0x11D00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Processing Engine Local AIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define PE_AIC_POL_CTRL			0x11F00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define PE_AIC_TYPE_CTRL		0x11F04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define PE_AIC_ENABLE_CTRL		0x11F08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define PE_AIC_RAW_STAT			0x11F0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define PE_AIC_ENABLE_SET		0x11F0C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define PE_AIC_ENABLED_STAT		0x11F10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PE_AIC_ENABLE_CLR		0x11F14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define PE_AIC_OPTIONS			0x11F18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define PE_AIC_VERSION			0x11F1C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Processing Engine General Configuration and Version */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PE_IN_FLIGHT			0x11FF0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define PE_OPTIONS			0x11FF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define PE_VERSION			0x11FFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* EIP-97 - Global */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define EIP97_CLOCK_STATE		0x1FFE4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define EIP97_FORCE_CLOCK_ON		0x1FFE8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define EIP97_FORCE_CLOCK_OFF		0x1FFEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define EIP97_MST_CTRL			0x1FFF4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define EIP97_OPTIONS			0x1FFF8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define EIP97_VERSION			0x1FFFC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #endif /* __MTK_REGS_H__ */