^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Driver for EIP97 cryptographic accelerator.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (c) 2016 Ryder Lee <ryder.lee@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/clk.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/init.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/platform_device.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/pm_runtime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include "mtk-platform.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define MTK_BURST_SIZE_MSK GENMASK(7, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define MTK_BURST_SIZE(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define MTK_DESC_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MTK_DESC_OFFSET(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MTK_DESC_FETCH_SIZE(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MTK_DESC_FETCH_THRESH(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MTK_DESC_OVL_IRQ_EN BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MTK_DESC_ATP_PRESENT BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MTK_DFSE_IDLE GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MTK_DFSE_THR_CTRL_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MTK_DFSE_THR_CTRL_RESET BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MTK_DFSE_RING_ID(x) (((x) >> 12) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MTK_DFSE_MIN_DATA(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MTK_DFSE_MAX_DATA(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MTK_DFE_MIN_CTRL(x) ((x) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MTK_DFE_MAX_CTRL(x) ((x) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MTK_IN_BUF_MIN_THRESH(x) ((x) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MTK_IN_BUF_MAX_THRESH(x) ((x) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MTK_OUT_BUF_MIN_THRESH(x) ((x) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MTK_OUT_BUF_MAX_THRESH(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MTK_IN_TBUF_SIZE(x) (((x) >> 4) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MTK_IN_DBUF_SIZE(x) (((x) >> 8) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MTK_OUT_DBUF_SIZE(x) (((x) >> 16) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MTK_CMD_FIFO_SIZE(x) (((x) >> 8) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MTK_RES_FIFO_SIZE(x) (((x) >> 12) & GENMASK(3, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MTK_PE_TK_LOC_AVL BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MTK_PE_PROC_HELD BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MTK_PE_TK_TIMEOUT_EN BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MTK_PE_INPUT_DMA_ERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MTK_PE_OUTPUT_DMA_ERR BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MTK_PE_PKT_PORC_ERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MTK_PE_PKT_TIMEOUT BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MTK_PE_FATAL_ERR BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MTK_PE_INPUT_DMA_ERR_EN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MTK_PE_OUTPUT_DMA_ERR_EN BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MTK_PE_PKT_PORC_ERR_EN BIT(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MTK_PE_PKT_TIMEOUT_EN BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MTK_PE_FATAL_ERR_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MTK_PE_INT_OUT_EN BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MTK_HIA_SIGNATURE ((u16)0x35ca)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define MTK_HIA_DATA_WIDTH(x) (((x) >> 25) & GENMASK(1, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MTK_HIA_DMA_LENGTH(x) (((x) >> 20) & GENMASK(4, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define MTK_CDR_STAT_CLR GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define MTK_RDR_STAT_CLR GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define MTK_AIC_INT_MSK GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define MTK_AIC_VER_MSK (GENMASK(15, 0) | GENMASK(27, 20))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define MTK_AIC_VER11 0x011036c9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define MTK_AIC_VER12 0x012036c9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define MTK_AIC_G_CLR GENMASK(30, 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * EIP97 is an integrated security subsystem to accelerate cryptographic
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * functions and protocols to offload the host processor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * Some important hardware modules are briefly introduced below:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * Host Interface Adapter(HIA) - the main interface between the host
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * system and the hardware subsystem. It is responsible for attaching
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * processing engine to the specific host bus interface and provides a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * standardized software view for off loading tasks to the engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * Command Descriptor Ring Manager(CDR Manager) - keeps track of how many
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * CD the host has prepared in the CDR. It monitors the fill level of its
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * CD-FIFO and if there's sufficient space for the next block of descriptors,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * then it fires off a DMA request to fetch a block of CDs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * Data fetch engine(DFE) - It is responsible for parsing the CD and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * setting up the required control and packet data DMA transfers from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * system memory to the processing engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * Result Descriptor Ring Manager(RDR Manager) - same as CDR Manager,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * but target is result descriptors, Moreover, it also handles the RD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * updates under control of the DSE. For each packet data segment
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * processed, the DSE triggers the RDR Manager to write the updated RD.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * If triggered to update, the RDR Manager sets up a DMA operation to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * copy the RD from the DSE to the correct location in the RDR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * Data Store Engine(DSE) - It is responsible for parsing the prepared RD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * and setting up the required control and packet data DMA transfers from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * the processing engine to system memory.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * Advanced Interrupt Controllers(AICs) - receive interrupt request signals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * from various sources and combine them into one interrupt output.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * The AICs are used by:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * - One for the HIA global and processing engine interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * - The others for the descriptor ring interrupts.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* Cryptographic engine capabilities */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) struct mtk_sys_cap {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* host interface adapter */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) u32 hia_ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) u32 hia_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) /* packet engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) u32 pkt_eng_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* global hardware */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) u32 hw_opt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) static void mtk_desc_ring_link(struct mtk_cryp *cryp, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) /* Assign rings to DFE/DSE thread and enable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DFE_THR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DSE_THR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) static void mtk_dfe_dse_buf_setup(struct mtk_cryp *cryp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) struct mtk_sys_cap *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) u32 width = MTK_HIA_DATA_WIDTH(cap->hia_opt) + 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) u32 len = MTK_HIA_DMA_LENGTH(cap->hia_opt) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) u32 ipbuf = min((u32)MTK_IN_DBUF_SIZE(cap->hw_opt) + width, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) u32 opbuf = min((u32)MTK_OUT_DBUF_SIZE(cap->hw_opt) + width, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) u32 itbuf = min((u32)MTK_IN_TBUF_SIZE(cap->hw_opt) + width, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) writel(MTK_DFSE_MIN_DATA(ipbuf - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) MTK_DFSE_MAX_DATA(ipbuf) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) MTK_DFE_MIN_CTRL(itbuf - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) MTK_DFE_MAX_CTRL(itbuf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) cryp->base + DFE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) writel(MTK_DFSE_MIN_DATA(opbuf - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) MTK_DFSE_MAX_DATA(opbuf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) cryp->base + DSE_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) writel(MTK_IN_BUF_MIN_THRESH(ipbuf - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) MTK_IN_BUF_MAX_THRESH(ipbuf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) cryp->base + PE_IN_DBUF_THRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) writel(MTK_IN_BUF_MIN_THRESH(itbuf - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) MTK_IN_BUF_MAX_THRESH(itbuf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) cryp->base + PE_IN_TBUF_THRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) writel(MTK_OUT_BUF_MIN_THRESH(opbuf - 1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) MTK_OUT_BUF_MAX_THRESH(opbuf),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) cryp->base + PE_OUT_DBUF_THRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) writel(0, cryp->base + PE_OUT_TBUF_THRESH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) writel(0, cryp->base + PE_OUT_BUF_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) static int mtk_dfe_dse_state_check(struct mtk_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) int ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* Check for completion of all DMA transfers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) val = readl(cryp->base + DFE_THR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) if (MTK_DFSE_RING_ID(val) == MTK_DFSE_IDLE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) val = readl(cryp->base + DSE_THR_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) if (MTK_DFSE_RING_ID(val) == MTK_DFSE_IDLE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) if (!ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* Take DFE/DSE thread out of reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) writel(0, cryp->base + DFE_THR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) writel(0, cryp->base + DSE_THR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) static int mtk_dfe_dse_reset(struct mtk_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* Reset DSE/DFE and correct system priorities for all rings. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DFE_THR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) writel(0, cryp->base + DFE_PRIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) writel(0, cryp->base + DFE_PRIO_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) writel(0, cryp->base + DFE_PRIO_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) writel(0, cryp->base + DFE_PRIO_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DSE_THR_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) writel(0, cryp->base + DSE_PRIO_0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) writel(0, cryp->base + DSE_PRIO_1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) writel(0, cryp->base + DSE_PRIO_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) writel(0, cryp->base + DSE_PRIO_3);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) return mtk_dfe_dse_state_check(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) static void mtk_cmd_desc_ring_setup(struct mtk_cryp *cryp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) int i, struct mtk_sys_cap *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Full descriptor that fits FIFO minus one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) u32 count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ((1 << MTK_CMD_FIFO_SIZE(cap->hia_opt)) / MTK_DESC_SZ) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Temporarily disable external triggering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) writel(0, cryp->base + CDR_CFG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* Clear CDR count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) writel(MTK_CNT_RST, cryp->base + CDR_PREP_COUNT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) writel(MTK_CNT_RST, cryp->base + CDR_PROC_COUNT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) writel(0, cryp->base + CDR_PREP_PNTR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) writel(0, cryp->base + CDR_PROC_PNTR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) writel(0, cryp->base + CDR_DMA_CFG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) /* Configure CDR host address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) writel(0, cryp->base + CDR_BASE_ADDR_HI(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) writel(cryp->ring[i]->cmd_dma, cryp->base + CDR_BASE_ADDR_LO(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) writel(MTK_DESC_RING_SZ, cryp->base + CDR_RING_SIZE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* Clear and disable all CDR interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) writel(MTK_CDR_STAT_CLR, cryp->base + CDR_STAT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * Set command descriptor offset and enable additional
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * token present in descriptor.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) writel(MTK_DESC_SIZE(MTK_DESC_SZ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) MTK_DESC_OFFSET(MTK_DESC_OFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) MTK_DESC_ATP_PRESENT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) cryp->base + CDR_DESC_SIZE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) writel(MTK_DESC_FETCH_SIZE(count * MTK_DESC_OFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) MTK_DESC_FETCH_THRESH(count * MTK_DESC_SZ),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) cryp->base + CDR_CFG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) static void mtk_res_desc_ring_setup(struct mtk_cryp *cryp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) int i, struct mtk_sys_cap *cap)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) u32 rndup = 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) u32 count = ((1 << MTK_RES_FIFO_SIZE(cap->hia_opt)) / rndup) - 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* Temporarily disable external triggering */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) writel(0, cryp->base + RDR_CFG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* Clear RDR count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) writel(MTK_CNT_RST, cryp->base + RDR_PREP_COUNT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) writel(MTK_CNT_RST, cryp->base + RDR_PROC_COUNT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) writel(0, cryp->base + RDR_PREP_PNTR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) writel(0, cryp->base + RDR_PROC_PNTR(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) writel(0, cryp->base + RDR_DMA_CFG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* Configure RDR host address space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) writel(0, cryp->base + RDR_BASE_ADDR_HI(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) writel(cryp->ring[i]->res_dma, cryp->base + RDR_BASE_ADDR_LO(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) writel(MTK_DESC_RING_SZ, cryp->base + RDR_RING_SIZE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) writel(MTK_RDR_STAT_CLR, cryp->base + RDR_STAT(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * RDR manager generates update interrupts on a per-completed-packet,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * and the rd_proc_thresh_irq interrupt is fired when proc_pkt_count
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * for the RDR exceeds the number of packets.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) writel(MTK_RDR_PROC_THRESH | MTK_RDR_PROC_MODE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) cryp->base + RDR_THRESH(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * Configure a threshold and time-out value for the processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * result descriptors (or complete packets) that are written to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * the RDR.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) writel(MTK_DESC_SIZE(MTK_DESC_SZ) | MTK_DESC_OFFSET(MTK_DESC_OFF),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) cryp->base + RDR_DESC_SIZE(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * Configure HIA fetch size and fetch threshold that are used to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * fetch blocks of multiple descriptors.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) writel(MTK_DESC_FETCH_SIZE(count * MTK_DESC_OFF) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) MTK_DESC_FETCH_THRESH(count * rndup) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) MTK_DESC_OVL_IRQ_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) cryp->base + RDR_CFG(i));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) static int mtk_packet_engine_setup(struct mtk_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) struct mtk_sys_cap cap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) cap.hia_ver = readl(cryp->base + HIA_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) cap.hia_opt = readl(cryp->base + HIA_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) cap.hw_opt = readl(cryp->base + EIP97_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) if (!(((u16)cap.hia_ver) == MTK_HIA_SIGNATURE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* Configure endianness conversion method for master (DMA) interface */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) writel(0, cryp->base + EIP97_MST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Set HIA burst size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) val = readl(cryp->base + HIA_MST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) val &= ~MTK_BURST_SIZE_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) val |= MTK_BURST_SIZE(5);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) writel(val, cryp->base + HIA_MST_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) err = mtk_dfe_dse_reset(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) dev_err(cryp->dev, "Failed to reset DFE and DSE.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) mtk_dfe_dse_buf_setup(cryp, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* Enable the 4 rings for the packet engines. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) mtk_desc_ring_link(cryp, 0xf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) for (i = 0; i < MTK_RING_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) mtk_cmd_desc_ring_setup(cryp, i, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) mtk_res_desc_ring_setup(cryp, i, &cap);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) writel(MTK_PE_TK_LOC_AVL | MTK_PE_PROC_HELD | MTK_PE_TK_TIMEOUT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) cryp->base + PE_TOKEN_CTRL_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) /* Clear all pending interrupts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) writel(MTK_AIC_G_CLR, cryp->base + AIC_G_ACK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) writel(MTK_PE_INPUT_DMA_ERR | MTK_PE_OUTPUT_DMA_ERR |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) MTK_PE_PKT_PORC_ERR | MTK_PE_PKT_TIMEOUT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) MTK_PE_FATAL_ERR | MTK_PE_INPUT_DMA_ERR_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) MTK_PE_OUTPUT_DMA_ERR_EN | MTK_PE_PKT_PORC_ERR_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) MTK_PE_PKT_TIMEOUT_EN | MTK_PE_FATAL_ERR_EN |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) MTK_PE_INT_OUT_EN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) cryp->base + PE_INTERRUPT_CTRL_STAT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) static int mtk_aic_cap_check(struct mtk_cryp *cryp, int hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) if (hw == MTK_RING_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) val = readl(cryp->base + AIC_G_VERSION);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) val = readl(cryp->base + AIC_VERSION(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) val &= MTK_AIC_VER_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) if (val != MTK_AIC_VER11 && val != MTK_AIC_VER12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) if (hw == MTK_RING_MAX)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) val = readl(cryp->base + AIC_G_OPTIONS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) val = readl(cryp->base + AIC_OPTIONS(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) val &= MTK_AIC_INT_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) if (!val || val > 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) return -ENXIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static int mtk_aic_init(struct mtk_cryp *cryp, int hw)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) err = mtk_aic_cap_check(cryp, hw);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* Disable all interrupts and set initial configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) if (hw == MTK_RING_MAX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) writel(0, cryp->base + AIC_G_ENABLE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) writel(0, cryp->base + AIC_G_POL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) writel(0, cryp->base + AIC_G_TYPE_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) writel(0, cryp->base + AIC_G_ENABLE_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) writel(0, cryp->base + AIC_ENABLE_CTRL(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) writel(0, cryp->base + AIC_POL_CTRL(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) writel(0, cryp->base + AIC_TYPE_CTRL(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) writel(0, cryp->base + AIC_ENABLE_SET(hw));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) static int mtk_accelerator_init(struct mtk_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /* Initialize advanced interrupt controller(AIC) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) for (i = 0; i < MTK_IRQ_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) err = mtk_aic_init(cryp, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) dev_err(cryp->dev, "Failed to initialize AIC.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) /* Initialize packet engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) err = mtk_packet_engine_setup(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) dev_err(cryp->dev, "Failed to configure packet engine.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) static void mtk_desc_dma_free(struct mtk_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) for (i = 0; i < MTK_RING_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) cryp->ring[i]->res_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) cryp->ring[i]->res_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) cryp->ring[i]->cmd_base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) cryp->ring[i]->cmd_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) kfree(cryp->ring[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) static int mtk_desc_ring_alloc(struct mtk_cryp *cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) struct mtk_ring **ring = cryp->ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) for (i = 0; i < MTK_RING_MAX; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) ring[i] = kzalloc(sizeof(**ring), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if (!ring[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) goto err_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) ring[i]->cmd_base = dma_alloc_coherent(cryp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) MTK_DESC_RING_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) &ring[i]->cmd_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) if (!ring[i]->cmd_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) goto err_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) ring[i]->res_base = dma_alloc_coherent(cryp->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) MTK_DESC_RING_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) &ring[i]->res_dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) if (!ring[i]->res_base)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) goto err_cleanup;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) ring[i]->cmd_next = ring[i]->cmd_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) ring[i]->res_next = ring[i]->res_base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) err_cleanup:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) do {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) ring[i]->res_base, ring[i]->res_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) dma_free_coherent(cryp->dev, MTK_DESC_RING_SZ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) ring[i]->cmd_base, ring[i]->cmd_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) kfree(ring[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) } while (i--);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) static int mtk_crypto_probe(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) struct mtk_cryp *cryp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) cryp = devm_kzalloc(&pdev->dev, sizeof(*cryp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) if (!cryp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) cryp->base = devm_platform_ioremap_resource(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) if (IS_ERR(cryp->base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) return PTR_ERR(cryp->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) for (i = 0; i < MTK_IRQ_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) cryp->irq[i] = platform_get_irq(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) if (cryp->irq[i] < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) return cryp->irq[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) cryp->clk_cryp = devm_clk_get(&pdev->dev, "cryp");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) if (IS_ERR(cryp->clk_cryp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) return -EPROBE_DEFER;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) cryp->dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) pm_runtime_enable(cryp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) pm_runtime_get_sync(cryp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) err = clk_prepare_enable(cryp->clk_cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) goto err_clk_cryp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /* Allocate four command/result descriptor rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) err = mtk_desc_ring_alloc(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) dev_err(cryp->dev, "Unable to allocate descriptor rings.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) goto err_resource;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) /* Initialize hardware modules */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) err = mtk_accelerator_init(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) dev_err(cryp->dev, "Failed to initialize cryptographic engine.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) goto err_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) err = mtk_cipher_alg_register(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) dev_err(cryp->dev, "Unable to register cipher algorithm.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) goto err_cipher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) err = mtk_hash_alg_register(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) dev_err(cryp->dev, "Unable to register hash algorithm.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) goto err_hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) platform_set_drvdata(pdev, cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) err_hash:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) mtk_cipher_alg_release(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) err_cipher:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) mtk_dfe_dse_reset(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) err_engine:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) mtk_desc_dma_free(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) err_resource:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) clk_disable_unprepare(cryp->clk_cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) err_clk_cryp:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) pm_runtime_put_sync(cryp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) pm_runtime_disable(cryp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) static int mtk_crypto_remove(struct platform_device *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct mtk_cryp *cryp = platform_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) mtk_hash_alg_release(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) mtk_cipher_alg_release(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) mtk_desc_dma_free(cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) clk_disable_unprepare(cryp->clk_cryp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) pm_runtime_put_sync(cryp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) pm_runtime_disable(cryp->dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) platform_set_drvdata(pdev, NULL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) static const struct of_device_id of_crypto_id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) { .compatible = "mediatek,eip97-crypto" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) {},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) MODULE_DEVICE_TABLE(of, of_crypto_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) static struct platform_driver mtk_crypto_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) .probe = mtk_crypto_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) .remove = mtk_crypto_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) .driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) .name = "mtk-crypto",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) .of_match_table = of_crypto_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) module_platform_driver(mtk_crypto_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) MODULE_AUTHOR("Ryder Lee <ryder.lee@mediatek.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) MODULE_DESCRIPTION("Cryptographic accelerator driver for EIP97");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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