^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #ifndef __MARVELL_CESA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define __MARVELL_CESA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <crypto/internal/hash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <crypto/internal/skcipher.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/dma-direction.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/dmapool.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CESA_ENGINE_OFF(i) (((i) * 0x2000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CESA_TDMA_BYTE_CNT 0x800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CESA_TDMA_SRC_ADDR 0x810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CESA_TDMA_DST_ADDR 0x820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CESA_TDMA_NEXT_ADDR 0x830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CESA_TDMA_CONTROL 0x840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CESA_TDMA_DST_BURST GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CESA_TDMA_DST_BURST_32B 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CESA_TDMA_DST_BURST_128B 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CESA_TDMA_OUT_RD_EN BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CESA_TDMA_SRC_BURST GENMASK(8, 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CESA_TDMA_SRC_BURST_32B (3 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CESA_TDMA_SRC_BURST_128B (4 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CESA_TDMA_CHAIN BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CESA_TDMA_BYTE_SWAP BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CESA_TDMA_NO_BYTE_SWAP BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CESA_TDMA_EN BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CESA_TDMA_FETCH_ND BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CESA_TDMA_ACT BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CESA_TDMA_CUR 0x870
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CESA_TDMA_ERROR_CAUSE 0x8c8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CESA_TDMA_ERROR_MSK 0x8cc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CESA_TDMA_WINDOW_BASE(x) (((x) * 0x8) + 0xa00)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CESA_TDMA_WINDOW_CTRL(x) (((x) * 0x8) + 0xa04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CESA_IVDIG(x) (0xdd00 + ((x) * 4) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) (((x) < 5) ? 0 : 0x14))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CESA_SA_CMD 0xde00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CESA_SA_CMD_EN_CESA_SA_ACCL0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CESA_SA_CMD_EN_CESA_SA_ACCL1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CESA_SA_CMD_DISABLE_SEC BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CESA_SA_DESC_P0 0xde04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CESA_SA_DESC_P1 0xde14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CESA_SA_CFG 0xde08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CESA_SA_CFG_STOP_DIG_ERR GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CESA_SA_CFG_DIG_ERR_CONT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CESA_SA_CFG_DIG_ERR_SKIP 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CESA_SA_CFG_DIG_ERR_STOP 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CESA_SA_CFG_CH0_W_IDMA BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CESA_SA_CFG_CH1_W_IDMA BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CESA_SA_CFG_ACT_CH0_IDMA BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CESA_SA_CFG_ACT_CH1_IDMA BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CESA_SA_CFG_MULTI_PKT BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CESA_SA_CFG_PARA_DIS BIT(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CESA_SA_ACCEL_STATUS 0xde0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CESA_SA_ST_ACT_0 BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CESA_SA_ST_ACT_1 BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * CESA_SA_FPGA_INT_STATUS looks like a FPGA leftover and is documented only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * in Errata 4.12. It looks like that it was part of an IRQ-controller in FPGA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * and someone forgot to remove it while switching to the core and moving to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * CESA_SA_INT_STATUS.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CESA_SA_FPGA_INT_STATUS 0xdd68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CESA_SA_INT_STATUS 0xde20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CESA_SA_INT_AUTH_DONE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CESA_SA_INT_DES_E_DONE BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CESA_SA_INT_AES_E_DONE BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CESA_SA_INT_AES_D_DONE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CESA_SA_INT_ENC_DONE BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CESA_SA_INT_ACCEL0_DONE BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CESA_SA_INT_ACCEL1_DONE BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CESA_SA_INT_ACC0_IDMA_DONE BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CESA_SA_INT_ACC1_IDMA_DONE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CESA_SA_INT_IDMA_DONE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CESA_SA_INT_IDMA_OWN_ERR BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CESA_SA_INT_MSK 0xde24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CESA_SA_DESC_CFG_OP_MAC_ONLY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CESA_SA_DESC_CFG_OP_CRYPT_ONLY 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CESA_SA_DESC_CFG_OP_MAC_CRYPT 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CESA_SA_DESC_CFG_OP_CRYPT_MAC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CESA_SA_DESC_CFG_OP_MSK GENMASK(1, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CESA_SA_DESC_CFG_MACM_SHA256 (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CESA_SA_DESC_CFG_MACM_HMAC_SHA256 (3 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CESA_SA_DESC_CFG_MACM_MD5 (4 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CESA_SA_DESC_CFG_MACM_SHA1 (5 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CESA_SA_DESC_CFG_MACM_HMAC_MD5 (6 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CESA_SA_DESC_CFG_MACM_HMAC_SHA1 (7 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CESA_SA_DESC_CFG_MACM_MSK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CESA_SA_DESC_CFG_CRYPTM_DES (1 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CESA_SA_DESC_CFG_CRYPTM_3DES (2 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CESA_SA_DESC_CFG_CRYPTM_AES (3 << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CESA_SA_DESC_CFG_CRYPTM_MSK GENMASK(9, 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CESA_SA_DESC_CFG_DIR_ENC (0 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CESA_SA_DESC_CFG_DIR_DEC (1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CESA_SA_DESC_CFG_CRYPTCM_ECB (0 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CESA_SA_DESC_CFG_CRYPTCM_CBC (1 << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CESA_SA_DESC_CFG_CRYPTCM_MSK BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CESA_SA_DESC_CFG_3DES_EEE (0 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CESA_SA_DESC_CFG_3DES_EDE (1 << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CESA_SA_DESC_CFG_AES_LEN_128 (0 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CESA_SA_DESC_CFG_AES_LEN_192 (1 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CESA_SA_DESC_CFG_AES_LEN_256 (2 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CESA_SA_DESC_CFG_AES_LEN_MSK GENMASK(25, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CESA_SA_DESC_CFG_NOT_FRAG (0 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CESA_SA_DESC_CFG_FIRST_FRAG (1 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CESA_SA_DESC_CFG_LAST_FRAG (2 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CESA_SA_DESC_CFG_MID_FRAG (3 << 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CESA_SA_DESC_CFG_FRAG_MSK GENMASK(31, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * /-----------\ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) * | ACCEL CFG | 4 * 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * |-----------| 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * | CRYPT KEY | 8 * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * |-----------| 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * | IV IN | 4 * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * |-----------| 0x40 (inplace)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * | IV BUF | 4 * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * |-----------| 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * | DATA IN | 16 * x (max ->max_req_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * |-----------| 0x80 (inplace operation)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * | DATA OUT | 16 * x (max ->max_req_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * \-----------/ SRAM size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * Hashing memory map:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * /-----------\ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * | ACCEL CFG | 4 * 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * |-----------| 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) * | Inner IV | 8 * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * |-----------| 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * | Outer IV | 8 * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * |-----------| 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * | Output BUF| 8 * 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * |-----------| 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * | DATA IN | 64 * x (max ->max_req_size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * \-----------/ SRAM size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CESA_SA_CFG_SRAM_OFFSET 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CESA_SA_DATA_SRAM_OFFSET 0x80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CESA_SA_CRYPT_KEY_SRAM_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CESA_SA_CRYPT_IV_SRAM_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CESA_SA_MAC_IIV_SRAM_OFFSET 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CESA_SA_MAC_OIV_SRAM_OFFSET 0x40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CESA_SA_MAC_DIG_SRAM_OFFSET 0x60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CESA_SA_DESC_CRYPT_DATA(offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) cpu_to_le32((CESA_SA_DATA_SRAM_OFFSET + (offset)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) ((CESA_SA_DATA_SRAM_OFFSET + (offset)) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CESA_SA_DESC_CRYPT_IV(offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) cpu_to_le32((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) ((CESA_SA_CRYPT_IV_SRAM_OFFSET + (offset)) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CESA_SA_DESC_CRYPT_KEY(offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) cpu_to_le32(CESA_SA_CRYPT_KEY_SRAM_OFFSET + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CESA_SA_DESC_MAC_DATA(offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) cpu_to_le32(CESA_SA_DATA_SRAM_OFFSET + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CESA_SA_DESC_MAC_DATA_MSK cpu_to_le32(GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CESA_SA_DESC_MAC_TOTAL_LEN(total_len) cpu_to_le32((total_len) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CESA_SA_DESC_MAC_TOTAL_LEN_MSK cpu_to_le32(GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CESA_SA_DESC_MAC_SRC_TOTAL_LEN_MAX 0xffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CESA_SA_DESC_MAC_DIGEST(offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) cpu_to_le32(CESA_SA_MAC_DIG_SRAM_OFFSET + (offset))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CESA_SA_DESC_MAC_DIGEST_MSK cpu_to_le32(GENMASK(15, 0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CESA_SA_DESC_MAC_FRAG_LEN(frag_len) cpu_to_le32((frag_len) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CESA_SA_DESC_MAC_FRAG_LEN_MSK cpu_to_le32(GENMASK(31, 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CESA_SA_DESC_MAC_IV(offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) cpu_to_le32((CESA_SA_MAC_IIV_SRAM_OFFSET + (offset)) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) ((CESA_SA_MAC_OIV_SRAM_OFFSET + (offset)) << 16))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CESA_SA_SRAM_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CESA_SA_SRAM_PAYLOAD_SIZE (cesa_dev->sram_size - \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) CESA_SA_DATA_SRAM_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CESA_SA_DEFAULT_SRAM_SIZE 2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CESA_SA_MIN_SRAM_SIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CESA_SA_SRAM_MSK (2048 - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CESA_MAX_HASH_BLOCK_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CESA_HASH_BLOCK_SIZE_MSK (CESA_MAX_HASH_BLOCK_SIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * struct mv_cesa_sec_accel_desc - security accelerator descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @config: engine config
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @enc_p: input and output data pointers for a cipher operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @enc_len: cipher operation length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @enc_key_p: cipher key pointer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * @enc_iv: cipher IV pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @mac_src_p: input pointer and total hash length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @mac_digest: digest pointer and hash operation length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @mac_iv: hmac IV pointers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * Structure passed to the CESA engine to describe the crypto operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * to be executed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) struct mv_cesa_sec_accel_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) __le32 config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) __le32 enc_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) __le32 enc_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) __le32 enc_key_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) __le32 enc_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) __le32 mac_src_p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) __le32 mac_digest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) __le32 mac_iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * struct mv_cesa_skcipher_op_ctx - cipher operation context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) * @key: cipher key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @iv: cipher IV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * Context associated to a cipher operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) struct mv_cesa_skcipher_op_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __le32 key[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) u32 iv[4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * struct mv_cesa_hash_op_ctx - hash or hmac operation context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @key: cipher key
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * @iv: cipher IV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * Context associated to an hash or hmac operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) struct mv_cesa_hash_op_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) u32 iv[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) __le32 hash[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * struct mv_cesa_op_ctx - crypto operation context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @desc: CESA descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @ctx: context associated to the crypto operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * Context associated to a crypto operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) struct mv_cesa_op_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) struct mv_cesa_sec_accel_desc desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) struct mv_cesa_skcipher_op_ctx skcipher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) struct mv_cesa_hash_op_ctx hash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) } ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* TDMA descriptor flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CESA_TDMA_DST_IN_SRAM BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CESA_TDMA_SRC_IN_SRAM BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CESA_TDMA_END_OF_REQ BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CESA_TDMA_BREAK_CHAIN BIT(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CESA_TDMA_SET_STATE BIT(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CESA_TDMA_TYPE_MSK GENMASK(26, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CESA_TDMA_DUMMY 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CESA_TDMA_DATA 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CESA_TDMA_OP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CESA_TDMA_RESULT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * struct mv_cesa_tdma_desc - TDMA descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * @byte_cnt: number of bytes to transfer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * @src: DMA address of the source
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * @dst: DMA address of the destination
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * @next_dma: DMA address of the next TDMA descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * @cur_dma: DMA address of this TDMA descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * @next: pointer to the next TDMA descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * @op: CESA operation attached to this TDMA descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @data: raw data attached to this TDMA descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) * @flags: flags describing the TDMA transfer. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * "TDMA descriptor flags" section above
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * TDMA descriptor used to create a transfer chain describing a crypto
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) struct mv_cesa_tdma_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) __le32 byte_cnt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) __le32 src;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) u32 src_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) __le32 dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) u32 dst_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) __le32 next_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* Software state */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) dma_addr_t cur_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) struct mv_cesa_tdma_desc *next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) struct mv_cesa_op_ctx *op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * struct mv_cesa_sg_dma_iter - scatter-gather iterator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * @dir: transfer direction
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * @sg: scatter list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * @offset: current position in the scatter list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * @op_offset: current position in the crypto operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * Iterator used to iterate over a scatterlist while creating a TDMA chain for
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * a crypto operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) struct mv_cesa_sg_dma_iter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) enum dma_data_direction dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) struct scatterlist *sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) unsigned int op_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * struct mv_cesa_dma_iter - crypto operation iterator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * @len: the crypto operation length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * @offset: current position in the crypto operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * @op_len: sub-operation length (the crypto engine can only act on 2kb
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * chunks)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * Iterator used to create a TDMA chain for a given crypto operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) struct mv_cesa_dma_iter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) unsigned int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) unsigned int op_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * struct mv_cesa_tdma_chain - TDMA chain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * @first: first entry in the TDMA chain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * @last: last entry in the TDMA chain
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) * Stores a TDMA chain for a specific crypto operation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) struct mv_cesa_tdma_chain {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) struct mv_cesa_tdma_desc *first;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) struct mv_cesa_tdma_desc *last;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) struct mv_cesa_engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) * struct mv_cesa_caps - CESA device capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) * @engines: number of engines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) * @has_tdma: whether this device has a TDMA block
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) * @cipher_algs: supported cipher algorithms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) * @ncipher_algs: number of supported cipher algorithms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) * @ahash_algs: supported hash algorithms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) * @nahash_algs: number of supported hash algorithms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) * Structure used to describe CESA device capabilities.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct mv_cesa_caps {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) int nengines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) bool has_tdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) struct skcipher_alg **cipher_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) int ncipher_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) struct ahash_alg **ahash_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) int nahash_algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) * struct mv_cesa_dev_dma - DMA pools
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) * @tdma_desc_pool: TDMA desc pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) * @op_pool: crypto operation pool
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) * @cache_pool: data cache pool (used by hash implementation when the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) * hash request is smaller than the hash block size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) * @padding_pool: padding pool (used by hash implementation when hardware
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) * padding cannot be used)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) * Structure containing the different DMA pools used by this driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) struct mv_cesa_dev_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) struct dma_pool *tdma_desc_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct dma_pool *op_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) struct dma_pool *cache_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) struct dma_pool *padding_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) * struct mv_cesa_dev - CESA device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) * @caps: device capabilities
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) * @regs: device registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) * @sram_size: usable SRAM size
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) * @lock: device lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) * @engines: array of engines
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) * @dma: dma pools
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) * Structure storing CESA device information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) struct mv_cesa_dev {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) const struct mv_cesa_caps *caps;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned int sram_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) struct mv_cesa_engine *engines;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) struct mv_cesa_dev_dma *dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) * struct mv_cesa_engine - CESA engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) * @id: engine id
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) * @regs: engine registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) * @sram: SRAM memory region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) * @sram_dma: DMA address of the SRAM memory region
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) * @lock: engine lock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) * @req: current crypto request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) * @clk: engine clk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) * @zclk: engine zclk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) * @max_req_len: maximum chunk length (useful to create the TDMA chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) * @int_mask: interrupt mask cache
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) * @pool: memory pool pointing to the memory region reserved in
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) * SRAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) * @queue: fifo of the pending crypto requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) * @load: engine load counter, useful for load balancing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) * @chain: list of the current tdma descriptors being processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) * by this engine.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) * @complete_queue: fifo of the processed requests by the engine
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) * Structure storing CESA engine information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) struct mv_cesa_engine {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) int id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) void __iomem *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) void __iomem *sram;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) dma_addr_t sram_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) struct crypto_async_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) struct clk *zclk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) size_t max_req_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) u32 int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) struct gen_pool *pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) struct crypto_queue queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) atomic_t load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) struct mv_cesa_tdma_chain chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) struct list_head complete_queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) * struct mv_cesa_req_ops - CESA request operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * @process: process a request chunk result (should return 0 if the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) * operation, -EINPROGRESS if it needs more steps or an error
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) * code)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) * @step: launch the crypto operation on the next chunk
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) * @cleanup: cleanup the crypto request (release associated data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) * @complete: complete the request, i.e copy result or context from sram when
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) * needed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) struct mv_cesa_req_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) int (*process)(struct crypto_async_request *req, u32 status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) void (*step)(struct crypto_async_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) void (*cleanup)(struct crypto_async_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) void (*complete)(struct crypto_async_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) * struct mv_cesa_ctx - CESA operation context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) * @ops: crypto operations
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) * Base context structure inherited by operation specific ones.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) struct mv_cesa_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) const struct mv_cesa_req_ops *ops;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) * struct mv_cesa_hash_ctx - CESA hash operation context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) * @base: base context structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) * Hash context structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) struct mv_cesa_hash_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct mv_cesa_ctx base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) * struct mv_cesa_hash_ctx - CESA hmac operation context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) * @base: base context structure
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) * @iv: initialization vectors
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) * HMAC context structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) struct mv_cesa_hmac_ctx {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) struct mv_cesa_ctx base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) __be32 iv[16];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) * enum mv_cesa_req_type - request type definitions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) * @CESA_STD_REQ: standard request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) * @CESA_DMA_REQ: DMA request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) enum mv_cesa_req_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) CESA_STD_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) CESA_DMA_REQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) * struct mv_cesa_req - CESA request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) * @engine: engine associated with this request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) * @chain: list of tdma descriptors associated with this request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) struct mv_cesa_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) struct mv_cesa_engine *engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) struct mv_cesa_tdma_chain chain;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) * struct mv_cesa_sg_std_iter - CESA scatter-gather iterator for standard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) * requests
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) * @iter: sg mapping iterator
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) * @offset: current offset in the SG entry mapped in memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) struct mv_cesa_sg_std_iter {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) struct sg_mapping_iter iter;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) * struct mv_cesa_skcipher_std_req - cipher standard request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) * @op: operation context
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) * @offset: current operation offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * @size: size of the crypto operation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) struct mv_cesa_skcipher_std_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) struct mv_cesa_op_ctx op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) unsigned int size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) bool skip_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) * struct mv_cesa_skcipher_req - cipher request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) * @req: type specific request information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) * @src_nents: number of entries in the src sg list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) * @dst_nents: number of entries in the dest sg list
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) struct mv_cesa_skcipher_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) struct mv_cesa_req base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) struct mv_cesa_skcipher_std_req std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) int src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) int dst_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) * struct mv_cesa_ahash_std_req - standard hash request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) * @offset: current operation offset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) struct mv_cesa_ahash_std_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) * struct mv_cesa_ahash_dma_req - DMA hash request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) * @padding: padding buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) * @padding_dma: DMA address of the padding buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) * @cache_dma: DMA address of the cache buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) struct mv_cesa_ahash_dma_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) u8 *padding;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) dma_addr_t padding_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u8 *cache;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) dma_addr_t cache_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) * struct mv_cesa_ahash_req - hash request
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) * @req: type specific request information
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) * @cache: cache buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) * @cache_ptr: write pointer in the cache buffer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) * @len: hash total length
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) * @src_nents: number of entries in the scatterlist
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) * @last_req: define whether the current operation is the last one
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) * or not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) * @state: hash state
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) struct mv_cesa_ahash_req {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) struct mv_cesa_req base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct mv_cesa_ahash_dma_req dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct mv_cesa_ahash_std_req std;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) } req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) struct mv_cesa_op_ctx op_tmpl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) u8 cache[CESA_MAX_HASH_BLOCK_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) unsigned int cache_ptr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) u64 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) int src_nents;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) bool last_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) bool algo_le;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u32 state[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /* CESA functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) extern struct mv_cesa_dev *cesa_dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) mv_cesa_engine_enqueue_complete_request(struct mv_cesa_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) struct crypto_async_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) list_add_tail(&req->list, &engine->complete_queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) static inline struct crypto_async_request *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) mv_cesa_engine_dequeue_complete_request(struct mv_cesa_engine *engine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) struct crypto_async_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) req = list_first_entry_or_null(&engine->complete_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) struct crypto_async_request,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) if (req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) list_del(&req->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) return req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) static inline enum mv_cesa_req_type
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) mv_cesa_req_get_type(struct mv_cesa_req *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) return req->chain.first ? CESA_DMA_REQ : CESA_STD_REQ;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) static inline void mv_cesa_update_op_cfg(struct mv_cesa_op_ctx *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) u32 cfg, u32 mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) op->desc.config &= cpu_to_le32(~mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) op->desc.config |= cpu_to_le32(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) static inline u32 mv_cesa_get_op_cfg(const struct mv_cesa_op_ctx *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) return le32_to_cpu(op->desc.config);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static inline void mv_cesa_set_op_cfg(struct mv_cesa_op_ctx *op, u32 cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) op->desc.config = cpu_to_le32(cfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) static inline void mv_cesa_adjust_op(struct mv_cesa_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) struct mv_cesa_op_ctx *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) u32 offset = engine->sram_dma & CESA_SA_SRAM_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) op->desc.enc_p = CESA_SA_DESC_CRYPT_DATA(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) op->desc.enc_key_p = CESA_SA_DESC_CRYPT_KEY(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) op->desc.enc_iv = CESA_SA_DESC_CRYPT_IV(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_DATA_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) op->desc.mac_src_p |= CESA_SA_DESC_MAC_DATA(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) op->desc.mac_digest &= ~CESA_SA_DESC_MAC_DIGEST_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) op->desc.mac_digest |= CESA_SA_DESC_MAC_DIGEST(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) op->desc.mac_iv = CESA_SA_DESC_MAC_IV(offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) static inline void mv_cesa_set_crypt_op_len(struct mv_cesa_op_ctx *op, int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) op->desc.enc_len = cpu_to_le32(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) static inline void mv_cesa_set_mac_op_total_len(struct mv_cesa_op_ctx *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) op->desc.mac_src_p &= ~CESA_SA_DESC_MAC_TOTAL_LEN_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) op->desc.mac_src_p |= CESA_SA_DESC_MAC_TOTAL_LEN(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) static inline void mv_cesa_set_mac_op_frag_len(struct mv_cesa_op_ctx *op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) op->desc.mac_digest &= ~CESA_SA_DESC_MAC_FRAG_LEN_MSK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) op->desc.mac_digest |= CESA_SA_DESC_MAC_FRAG_LEN(len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) static inline void mv_cesa_set_int_mask(struct mv_cesa_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) u32 int_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) if (int_mask == engine->int_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) writel_relaxed(int_mask, engine->regs + CESA_SA_INT_MSK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) engine->int_mask = int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) static inline u32 mv_cesa_get_int_mask(struct mv_cesa_engine *engine)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) return engine->int_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) static inline bool mv_cesa_mac_op_is_first_frag(const struct mv_cesa_op_ctx *op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) return (mv_cesa_get_op_cfg(op) & CESA_SA_DESC_CFG_FRAG_MSK) ==
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) CESA_SA_DESC_CFG_FIRST_FRAG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) int mv_cesa_queue_req(struct crypto_async_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) struct mv_cesa_req *creq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) struct crypto_async_request *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) struct crypto_async_request **backlog);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) static inline struct mv_cesa_engine *mv_cesa_select_engine(int weight)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) u32 min_load = U32_MAX;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) struct mv_cesa_engine *selected = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) for (i = 0; i < cesa_dev->caps->nengines; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) struct mv_cesa_engine *engine = cesa_dev->engines + i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) u32 load = atomic_read(&engine->load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (load < min_load) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) min_load = load;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) selected = engine;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) atomic_add(weight, &selected->load);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) return selected;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) * Helper function that indicates whether a crypto request needs to be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) * cleaned up or not after being enqueued using mv_cesa_queue_req().
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) static inline int mv_cesa_req_needs_cleanup(struct crypto_async_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) int ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) * The queue still had some space, the request was queued
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) * normally, so there's no need to clean it up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) if (ret == -EINPROGRESS)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) * The queue had not space left, but since the request is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) * flagged with CRYPTO_TFM_REQ_MAY_BACKLOG, it was added to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) * the backlog and will be processed later. There's no need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) * clean it up.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) if (ret == -EBUSY)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /* Request wasn't queued, we need to clean it up */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /* TDMA functions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) static inline void mv_cesa_req_dma_iter_init(struct mv_cesa_dma_iter *iter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) iter->len = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) iter->op_len = min(len, CESA_SA_SRAM_PAYLOAD_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) iter->offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) static inline void mv_cesa_sg_dma_iter_init(struct mv_cesa_sg_dma_iter *iter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) struct scatterlist *sg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) enum dma_data_direction dir)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) iter->op_offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) iter->offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) iter->sg = sg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) iter->dir = dir;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) static inline unsigned int
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) mv_cesa_req_dma_iter_transfer_len(struct mv_cesa_dma_iter *iter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) struct mv_cesa_sg_dma_iter *sgiter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) return min(iter->op_len - sgiter->op_offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) sg_dma_len(sgiter->sg) - sgiter->offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) bool mv_cesa_req_dma_iter_next_transfer(struct mv_cesa_dma_iter *chain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct mv_cesa_sg_dma_iter *sgiter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) unsigned int len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) static inline bool mv_cesa_req_dma_iter_next_op(struct mv_cesa_dma_iter *iter)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) iter->offset += iter->op_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) iter->op_len = min(iter->len - iter->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) CESA_SA_SRAM_PAYLOAD_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) return iter->op_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) void mv_cesa_dma_step(struct mv_cesa_req *dreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) static inline int mv_cesa_dma_process(struct mv_cesa_req *dreq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) u32 status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) if (!(status & CESA_SA_INT_ACC0_IDMA_DONE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) return -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) if (status & CESA_SA_INT_IDMA_OWN_ERR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) void mv_cesa_dma_prepare(struct mv_cesa_req *dreq,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct mv_cesa_engine *engine);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) void mv_cesa_dma_cleanup(struct mv_cesa_req *dreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) void mv_cesa_tdma_chain(struct mv_cesa_engine *engine,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) struct mv_cesa_req *dreq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) static inline void
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) mv_cesa_tdma_desc_iter_init(struct mv_cesa_tdma_chain *chain)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) memset(chain, 0, sizeof(*chain));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) int mv_cesa_dma_add_result_op(struct mv_cesa_tdma_chain *chain, dma_addr_t src,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) u32 size, u32 flags, gfp_t gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) struct mv_cesa_op_ctx *mv_cesa_dma_add_op(struct mv_cesa_tdma_chain *chain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) const struct mv_cesa_op_ctx *op_templ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) bool skip_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) int mv_cesa_dma_add_data_transfer(struct mv_cesa_tdma_chain *chain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) dma_addr_t dst, dma_addr_t src, u32 size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u32 flags, gfp_t gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) int mv_cesa_dma_add_dummy_launch(struct mv_cesa_tdma_chain *chain, gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) int mv_cesa_dma_add_dummy_end(struct mv_cesa_tdma_chain *chain, gfp_t flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) int mv_cesa_dma_add_op_transfers(struct mv_cesa_tdma_chain *chain,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct mv_cesa_dma_iter *dma_iter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) struct mv_cesa_sg_dma_iter *sgiter,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) gfp_t gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /* Algorithm definitions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) extern struct ahash_alg mv_md5_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) extern struct ahash_alg mv_sha1_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) extern struct ahash_alg mv_sha256_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) extern struct ahash_alg mv_ahmac_md5_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) extern struct ahash_alg mv_ahmac_sha1_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) extern struct ahash_alg mv_ahmac_sha256_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) extern struct skcipher_alg mv_cesa_ecb_des_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) extern struct skcipher_alg mv_cesa_cbc_des_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) extern struct skcipher_alg mv_cesa_ecb_des3_ede_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) extern struct skcipher_alg mv_cesa_cbc_des3_ede_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) extern struct skcipher_alg mv_cesa_ecb_aes_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) extern struct skcipher_alg mv_cesa_cbc_aes_alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) #endif /* __MARVELL_CESA_H__ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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