^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 Marvell
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Antoine Tenart <antoine.tenart@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __SAFEXCEL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __SAFEXCEL_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <crypto/aead.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <crypto/algapi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <crypto/internal/hash.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <crypto/sha.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <crypto/sha3.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <crypto/skcipher.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/types.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define EIP197_HIA_VERSION_BE 0xca35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define EIP197_HIA_VERSION_LE 0x35ca
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define EIP97_VERSION_LE 0x9e61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define EIP196_VERSION_LE 0x3bc4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define EIP197_VERSION_LE 0x3ac5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define EIP96_VERSION_LE 0x9f60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define EIP201_VERSION_LE 0x36c9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define EIP206_VERSION_LE 0x31ce
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EIP207_VERSION_LE 0x30cf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EIP197_REG_LO16(reg) (reg & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define EIP197_REG_HI16(reg) ((reg >> 16) & 0xffff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EIP197_VERSION_MASK(reg) ((reg >> 16) & 0xfff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define EIP197_VERSION_SWAP(reg) (((reg & 0xf0) << 4) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) ((reg >> 4) & 0xf0) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) ((reg >> 12) & 0xf))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) /* EIP197 HIA OPTIONS ENCODING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define EIP197_HIA_OPT_HAS_PE_ARB BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) /* EIP206 OPTIONS ENCODING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define EIP206_OPT_ICE_TYPE(n) ((n>>8)&3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define EIP206_OPT_OCE_TYPE(n) ((n>>10)&3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) /* EIP197 OPTIONS ENCODING */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define EIP197_OPT_HAS_TRC BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) /* Static configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define EIP197_DEFAULT_RING_SIZE 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define EIP197_EMB_TOKENS 4 /* Pad CD to 16 dwords */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define EIP197_MAX_TOKENS 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define EIP197_MAX_RINGS 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define EIP197_FETCH_DEPTH 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define EIP197_MAX_BATCH_SZ 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define EIP197_MAX_RING_AIC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define EIP197_GFP_FLAGS(base) ((base).flags & CRYPTO_TFM_REQ_MAY_SLEEP ? \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) GFP_KERNEL : GFP_ATOMIC)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) /* Custom on-stack requests (for invalidation) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define EIP197_SKCIPHER_REQ_SIZE sizeof(struct skcipher_request) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) sizeof(struct safexcel_cipher_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define EIP197_AHASH_REQ_SIZE sizeof(struct ahash_request) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) sizeof(struct safexcel_ahash_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define EIP197_AEAD_REQ_SIZE sizeof(struct aead_request) + \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) sizeof(struct safexcel_cipher_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define EIP197_REQUEST_ON_STACK(name, type, size) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) char __##name##_desc[size] CRYPTO_MINALIGN_ATTR; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) struct type##_request *name = (void *)__##name##_desc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) /* Xilinx dev board base offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define EIP197_XLX_GPIO_BASE 0x200000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define EIP197_XLX_IRQ_BLOCK_ID_ADDR 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define EIP197_XLX_IRQ_BLOCK_ID_VALUE 0x1fc2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define EIP197_XLX_USER_INT_ENB_MSK 0x2004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define EIP197_XLX_USER_INT_ENB_SET 0x2008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define EIP197_XLX_USER_INT_ENB_CLEAR 0x200c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define EIP197_XLX_USER_INT_BLOCK 0x2040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define EIP197_XLX_USER_INT_PEND 0x2048
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define EIP197_XLX_USER_VECT_LUT0_ADDR 0x2080
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define EIP197_XLX_USER_VECT_LUT0_IDENT 0x03020100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define EIP197_XLX_USER_VECT_LUT1_ADDR 0x2084
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define EIP197_XLX_USER_VECT_LUT1_IDENT 0x07060504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define EIP197_XLX_USER_VECT_LUT2_ADDR 0x2088
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define EIP197_XLX_USER_VECT_LUT2_IDENT 0x0b0a0908
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define EIP197_XLX_USER_VECT_LUT3_ADDR 0x208c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define EIP197_XLX_USER_VECT_LUT3_IDENT 0x0f0e0d0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) /* Helper defines for probe function */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define EIP197_IRQ_NUMBER(i, is_pci) (i + is_pci)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) /* Register base offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define EIP197_HIA_AIC(priv) ((priv)->base + (priv)->offsets.hia_aic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define EIP197_HIA_AIC_G(priv) ((priv)->base + (priv)->offsets.hia_aic_g)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define EIP197_HIA_AIC_R(priv) ((priv)->base + (priv)->offsets.hia_aic_r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define EIP197_HIA_AIC_xDR(priv) ((priv)->base + (priv)->offsets.hia_aic_xdr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define EIP197_HIA_DFE(priv) ((priv)->base + (priv)->offsets.hia_dfe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define EIP197_HIA_DFE_THR(priv) ((priv)->base + (priv)->offsets.hia_dfe_thr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define EIP197_HIA_DSE(priv) ((priv)->base + (priv)->offsets.hia_dse)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define EIP197_HIA_DSE_THR(priv) ((priv)->base + (priv)->offsets.hia_dse_thr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define EIP197_HIA_GEN_CFG(priv) ((priv)->base + (priv)->offsets.hia_gen_cfg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define EIP197_PE(priv) ((priv)->base + (priv)->offsets.pe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define EIP197_GLOBAL(priv) ((priv)->base + (priv)->offsets.global)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* EIP197 base offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define EIP197_HIA_AIC_BASE 0x90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define EIP197_HIA_AIC_G_BASE 0x90000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define EIP197_HIA_AIC_R_BASE 0x90800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define EIP197_HIA_AIC_xDR_BASE 0x80000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define EIP197_HIA_DFE_BASE 0x8c000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define EIP197_HIA_DFE_THR_BASE 0x8c040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define EIP197_HIA_DSE_BASE 0x8d000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define EIP197_HIA_DSE_THR_BASE 0x8d040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define EIP197_HIA_GEN_CFG_BASE 0xf0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define EIP197_PE_BASE 0xa0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define EIP197_GLOBAL_BASE 0xf0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* EIP97 base offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define EIP97_HIA_AIC_BASE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define EIP97_HIA_AIC_G_BASE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define EIP97_HIA_AIC_R_BASE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define EIP97_HIA_AIC_xDR_BASE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define EIP97_HIA_DFE_BASE 0xf000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define EIP97_HIA_DFE_THR_BASE 0xf200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define EIP97_HIA_DSE_BASE 0xf400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define EIP97_HIA_DSE_THR_BASE 0xf600
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define EIP97_HIA_GEN_CFG_BASE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define EIP97_PE_BASE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define EIP97_GLOBAL_BASE 0x10000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* CDR/RDR register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define EIP197_HIA_xDR_OFF(priv, r) (EIP197_HIA_AIC_xDR(priv) + (r) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define EIP197_HIA_CDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define EIP197_HIA_RDR(priv, r) (EIP197_HIA_xDR_OFF(priv, r) + 0x800)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define EIP197_HIA_xDR_RING_BASE_ADDR_LO 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define EIP197_HIA_xDR_RING_BASE_ADDR_HI 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define EIP197_HIA_xDR_RING_SIZE 0x0018
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define EIP197_HIA_xDR_DESC_SIZE 0x001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define EIP197_HIA_xDR_CFG 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define EIP197_HIA_xDR_DMA_CFG 0x0024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define EIP197_HIA_xDR_THRESH 0x0028
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define EIP197_HIA_xDR_PREP_COUNT 0x002c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define EIP197_HIA_xDR_PROC_COUNT 0x0030
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define EIP197_HIA_xDR_PREP_PNTR 0x0034
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define EIP197_HIA_xDR_PROC_PNTR 0x0038
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define EIP197_HIA_xDR_STAT 0x003c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) /* register offsets */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define EIP197_HIA_DFE_CFG(n) (0x0000 + (128 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define EIP197_HIA_DFE_THR_CTRL(n) (0x0000 + (128 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define EIP197_HIA_DFE_THR_STAT(n) (0x0004 + (128 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define EIP197_HIA_DSE_CFG(n) (0x0000 + (128 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define EIP197_HIA_DSE_THR_CTRL(n) (0x0000 + (128 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define EIP197_HIA_DSE_THR_STAT(n) (0x0004 + (128 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define EIP197_HIA_RA_PE_CTRL(n) (0x0010 + (8 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define EIP197_HIA_RA_PE_STAT 0x0014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define EIP197_HIA_AIC_R_OFF(r) ((r) * 0x1000)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define EIP197_HIA_AIC_R_ENABLE_CTRL(r) (0xe008 - EIP197_HIA_AIC_R_OFF(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define EIP197_HIA_AIC_R_ENABLED_STAT(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define EIP197_HIA_AIC_R_ACK(r) (0xe010 - EIP197_HIA_AIC_R_OFF(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define EIP197_HIA_AIC_R_ENABLE_CLR(r) (0xe014 - EIP197_HIA_AIC_R_OFF(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define EIP197_HIA_AIC_R_VERSION(r) (0xe01c - EIP197_HIA_AIC_R_OFF(r))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define EIP197_HIA_AIC_G_ENABLE_CTRL 0xf808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define EIP197_HIA_AIC_G_ENABLED_STAT 0xf810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define EIP197_HIA_AIC_G_ACK 0xf810
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define EIP197_HIA_MST_CTRL 0xfff4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define EIP197_HIA_OPTIONS 0xfff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define EIP197_HIA_VERSION 0xfffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define EIP197_PE_IN_DBUF_THRES(n) (0x0000 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define EIP197_PE_IN_TBUF_THRES(n) (0x0100 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define EIP197_PE_ICE_SCRATCH_RAM(n) (0x0800 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define EIP197_PE_ICE_PUE_CTRL(n) (0x0c80 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define EIP197_PE_ICE_PUTF_CTRL(n) (0x0d00 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define EIP197_PE_ICE_SCRATCH_CTRL(n) (0x0d04 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define EIP197_PE_ICE_FPP_CTRL(n) (0x0d80 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define EIP197_PE_ICE_PPTF_CTRL(n) (0x0e00 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define EIP197_PE_ICE_RAM_CTRL(n) (0x0ff0 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define EIP197_PE_ICE_VERSION(n) (0x0ffc + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define EIP197_PE_EIP96_TOKEN_CTRL(n) (0x1000 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define EIP197_PE_EIP96_FUNCTION_EN(n) (0x1004 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define EIP197_PE_EIP96_CONTEXT_CTRL(n) (0x1008 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define EIP197_PE_EIP96_CONTEXT_STAT(n) (0x100c + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define EIP197_PE_EIP96_TOKEN_CTRL2(n) (0x102c + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define EIP197_PE_EIP96_FUNCTION2_EN(n) (0x1030 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define EIP197_PE_EIP96_OPTIONS(n) (0x13f8 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define EIP197_PE_EIP96_VERSION(n) (0x13fc + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define EIP197_PE_OCE_VERSION(n) (0x1bfc + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define EIP197_PE_OUT_DBUF_THRES(n) (0x1c00 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define EIP197_PE_OUT_TBUF_THRES(n) (0x1d00 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define EIP197_PE_PSE_VERSION(n) (0x1efc + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define EIP197_PE_DEBUG(n) (0x1ff4 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define EIP197_PE_OPTIONS(n) (0x1ff8 + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define EIP197_PE_VERSION(n) (0x1ffc + (0x2000 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define EIP197_MST_CTRL 0xfff4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define EIP197_OPTIONS 0xfff8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define EIP197_VERSION 0xfffc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* EIP197-specific registers, no indirection */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define EIP197_CLASSIFICATION_RAMS 0xe0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define EIP197_TRC_CTRL 0xf0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define EIP197_TRC_LASTRES 0xf0804
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define EIP197_TRC_REGINDEX 0xf0808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define EIP197_TRC_PARAMS 0xf0820
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define EIP197_TRC_FREECHAIN 0xf0824
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define EIP197_TRC_PARAMS2 0xf0828
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define EIP197_TRC_ECCCTRL 0xf0830
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define EIP197_TRC_ECCSTAT 0xf0834
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define EIP197_TRC_ECCADMINSTAT 0xf0838
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define EIP197_TRC_ECCDATASTAT 0xf083c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define EIP197_TRC_ECCDATA 0xf0840
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define EIP197_STRC_CONFIG 0xf43f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define EIP197_FLUE_CACHEBASE_LO(n) (0xf6000 + (32 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define EIP197_FLUE_CACHEBASE_HI(n) (0xf6004 + (32 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define EIP197_FLUE_CONFIG(n) (0xf6010 + (32 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define EIP197_FLUE_OFFSETS 0xf6808
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define EIP197_FLUE_ARC4_OFFSET 0xf680c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define EIP197_FLUE_IFC_LUT(n) (0xf6820 + (4 * (n)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define EIP197_CS_RAM_CTRL 0xf7ff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* EIP197_HIA_xDR_DESC_SIZE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define EIP197_xDR_DESC_MODE_64BIT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define EIP197_CDR_DESC_MODE_ADCP BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) /* EIP197_HIA_xDR_DMA_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define EIP197_HIA_xDR_WR_RES_BUF BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define EIP197_HIA_xDR_WR_CTRL_BUF BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define EIP197_HIA_xDR_WR_OWN_BUF BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define EIP197_HIA_xDR_CFG_WR_CACHE(n) (((n) & 0x7) << 25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define EIP197_HIA_xDR_CFG_RD_CACHE(n) (((n) & 0x7) << 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* EIP197_HIA_CDR_THRESH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define EIP197_HIA_CDR_THRESH_PROC_PKT(n) (n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define EIP197_HIA_CDR_THRESH_PROC_MODE BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define EIP197_HIA_CDR_THRESH_PKT_MODE BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define EIP197_HIA_CDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) /* EIP197_HIA_RDR_THRESH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define EIP197_HIA_RDR_THRESH_PROC_PKT(n) (n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define EIP197_HIA_RDR_THRESH_PKT_MODE BIT(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define EIP197_HIA_RDR_THRESH_TIMEOUT(n) ((n) << 24) /* x256 clk cycles */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* EIP197_HIA_xDR_PREP_COUNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define EIP197_xDR_PREP_CLR_COUNT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* EIP197_HIA_xDR_PROC_COUNT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define EIP197_xDR_PROC_xD_PKT_OFFSET 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define EIP197_xDR_PROC_xD_PKT_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define EIP197_xDR_PROC_xD_PKT(n) ((n) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define EIP197_xDR_PROC_CLR_COUNT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) /* EIP197_HIA_xDR_STAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define EIP197_xDR_DMA_ERR BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define EIP197_xDR_PREP_CMD_THRES BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define EIP197_xDR_ERR BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define EIP197_xDR_THRESH BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define EIP197_xDR_TIMEOUT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define EIP197_HIA_RA_PE_CTRL_RESET BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define EIP197_HIA_RA_PE_CTRL_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* EIP197_HIA_OPTIONS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define EIP197_N_RINGS_OFFSET 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define EIP197_N_RINGS_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define EIP197_N_PES_OFFSET 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define EIP197_N_PES_MASK GENMASK(4, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define EIP97_N_PES_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define EIP197_HWDATAW_OFFSET 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define EIP197_HWDATAW_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define EIP97_HWDATAW_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define EIP197_CFSIZE_OFFSET 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define EIP197_CFSIZE_ADJUST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define EIP97_CFSIZE_OFFSET 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define EIP197_CFSIZE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define EIP97_CFSIZE_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define EIP197_RFSIZE_OFFSET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define EIP197_RFSIZE_ADJUST 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define EIP97_RFSIZE_OFFSET 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define EIP197_RFSIZE_MASK GENMASK(2, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define EIP97_RFSIZE_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) /* EIP197_HIA_AIC_R_ENABLE_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define EIP197_CDR_IRQ(n) BIT((n) * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define EIP197_RDR_IRQ(n) BIT((n) * 2 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) /* EIP197_HIA_DFE/DSE_CFG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define EIP197_HIA_DxE_CFG_MIN_DATA_SIZE(n) ((n) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define EIP197_HIA_DxE_CFG_DATA_CACHE_CTRL(n) (((n) & 0x7) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define EIP197_HIA_DxE_CFG_MAX_DATA_SIZE(n) ((n) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define EIP197_HIA_DSE_CFG_ALWAYS_BUFFERABLE GENMASK(15, 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define EIP197_HIA_DxE_CFG_MIN_CTRL_SIZE(n) ((n) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define EIP197_HIA_DxE_CFG_CTRL_CACHE_CTRL(n) (((n) & 0x7) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define EIP197_HIA_DxE_CFG_MAX_CTRL_SIZE(n) ((n) << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define EIP197_HIA_DFE_CFG_DIS_DEBUG GENMASK(31, 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define EIP197_HIA_DSE_CFG_EN_SINGLE_WR BIT(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define EIP197_HIA_DSE_CFG_DIS_DEBUG GENMASK(31, 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) /* EIP197_HIA_DFE/DSE_THR_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define EIP197_DxE_THR_CTRL_EN BIT(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define EIP197_DxE_THR_CTRL_RESET_PE BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* EIP197_PE_ICE_PUE/FPP_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define EIP197_PE_ICE_UENG_START_OFFSET(n) ((n) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define EIP197_PE_ICE_UENG_INIT_ALIGN_MASK 0x7ff0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define EIP197_PE_ICE_UENG_DEBUG_RESET BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) /* EIP197_HIA_AIC_G_ENABLED_STAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define EIP197_G_IRQ_DFE(n) BIT((n) << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define EIP197_G_IRQ_DSE(n) BIT(((n) << 1) + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define EIP197_G_IRQ_RING BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define EIP197_G_IRQ_PE(n) BIT((n) + 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* EIP197_HIA_MST_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define RD_CACHE_3BITS 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define WR_CACHE_3BITS 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define RD_CACHE_4BITS (RD_CACHE_3BITS << 1 | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define WR_CACHE_4BITS (WR_CACHE_3BITS << 1 | BIT(0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define EIP197_MST_CTRL_RD_CACHE(n) (((n) & 0xf) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define EIP197_MST_CTRL_WD_CACHE(n) (((n) & 0xf) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define EIP197_MST_CTRL_TX_MAX_CMD(n) (((n) & 0xf) << 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define EIP197_MST_CTRL_BYTE_SWAP BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define EIP197_MST_CTRL_NO_BYTE_SWAP BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define EIP197_MST_CTRL_BYTE_SWAP_BITS GENMASK(25, 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* EIP197_PE_IN_DBUF/TBUF_THRES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define EIP197_PE_IN_xBUF_THRES_MIN(n) ((n) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define EIP197_PE_IN_xBUF_THRES_MAX(n) ((n) << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* EIP197_PE_OUT_DBUF_THRES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define EIP197_PE_OUT_DBUF_THRES_MIN(n) ((n) << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define EIP197_PE_OUT_DBUF_THRES_MAX(n) ((n) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* EIP197_PE_ICE_SCRATCH_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_TIMER BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define EIP197_PE_ICE_SCRATCH_CTRL_TIMER_EN BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define EIP197_PE_ICE_SCRATCH_CTRL_CHANGE_ACCESS BIT(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define EIP197_PE_ICE_SCRATCH_CTRL_SCRATCH_ACCESS BIT(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* EIP197_PE_ICE_SCRATCH_RAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define EIP197_NUM_OF_SCRATCH_BLOCKS 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* EIP197_PE_ICE_PUE/FPP_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define EIP197_PE_ICE_x_CTRL_SW_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define EIP197_PE_ICE_x_CTRL_CLR_ECC_NON_CORR BIT(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define EIP197_PE_ICE_x_CTRL_CLR_ECC_CORR BIT(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) /* EIP197_PE_ICE_RAM_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define EIP197_PE_ICE_RAM_CTRL_PUE_PROG_EN BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define EIP197_PE_ICE_RAM_CTRL_FPP_PROG_EN BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) /* EIP197_PE_EIP96_TOKEN_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define EIP197_PE_EIP96_TOKEN_CTRL_CTX_UPDATES BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define EIP197_PE_EIP96_TOKEN_CTRL_NO_TOKEN_WAIT BIT(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define EIP197_PE_EIP96_TOKEN_CTRL_ENABLE_TIMEOUT BIT(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /* EIP197_PE_EIP96_FUNCTION_EN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define EIP197_FUNCTION_ALL 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) /* EIP197_PE_EIP96_CONTEXT_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define EIP197_CONTEXT_SIZE(n) (n)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define EIP197_ADDRESS_MODE BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define EIP197_CONTROL_MODE BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /* EIP197_PE_EIP96_TOKEN_CTRL2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define EIP197_PE_EIP96_TOKEN_CTRL2_CTX_DONE BIT(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* EIP197_PE_DEBUG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define EIP197_DEBUG_OCE_BYPASS BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* EIP197_STRC_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define EIP197_STRC_CONFIG_INIT BIT(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define EIP197_STRC_CONFIG_LARGE_REC(s) (s<<8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define EIP197_STRC_CONFIG_SMALL_REC(s) (s<<0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* EIP197_FLUE_CONFIG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define EIP197_FLUE_CONFIG_MAGIC 0xc7000004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* Context Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct safexcel_context_record {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) __le32 control0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) __le32 control1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) __le32 data[40];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* control0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define CONTEXT_CONTROL_TYPE_NULL_OUT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define CONTEXT_CONTROL_TYPE_NULL_IN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define CONTEXT_CONTROL_TYPE_HASH_OUT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define CONTEXT_CONTROL_TYPE_HASH_IN 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define CONTEXT_CONTROL_TYPE_CRYPTO_OUT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define CONTEXT_CONTROL_TYPE_CRYPTO_IN 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define CONTEXT_CONTROL_TYPE_ENCRYPT_HASH_OUT 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define CONTEXT_CONTROL_TYPE_DECRYPT_HASH_IN 0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define CONTEXT_CONTROL_TYPE_HASH_ENCRYPT_OUT 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define CONTEXT_CONTROL_TYPE_HASH_DECRYPT_IN 0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define CONTEXT_CONTROL_RESTART_HASH BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define CONTEXT_CONTROL_NO_FINISH_HASH BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define CONTEXT_CONTROL_SIZE(n) ((n) << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define CONTEXT_CONTROL_KEY_EN BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define CONTEXT_CONTROL_CRYPTO_ALG_DES (0x0 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define CONTEXT_CONTROL_CRYPTO_ALG_3DES (0x2 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define CONTEXT_CONTROL_CRYPTO_ALG_AES128 (0x5 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define CONTEXT_CONTROL_CRYPTO_ALG_AES192 (0x6 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define CONTEXT_CONTROL_CRYPTO_ALG_AES256 (0x7 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define CONTEXT_CONTROL_CRYPTO_ALG_CHACHA20 (0x8 << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define CONTEXT_CONTROL_CRYPTO_ALG_SM4 (0xd << 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define CONTEXT_CONTROL_DIGEST_INITIAL (0x0 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define CONTEXT_CONTROL_DIGEST_PRECOMPUTED (0x1 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define CONTEXT_CONTROL_DIGEST_XCM (0x2 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define CONTEXT_CONTROL_DIGEST_HMAC (0x3 << 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define CONTEXT_CONTROL_CRYPTO_ALG_MD5 (0x0 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define CONTEXT_CONTROL_CRYPTO_ALG_CRC32 (0x0 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define CONTEXT_CONTROL_CRYPTO_ALG_SHA1 (0x2 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define CONTEXT_CONTROL_CRYPTO_ALG_SHA224 (0x4 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define CONTEXT_CONTROL_CRYPTO_ALG_SHA256 (0x3 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define CONTEXT_CONTROL_CRYPTO_ALG_SHA384 (0x6 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define CONTEXT_CONTROL_CRYPTO_ALG_SHA512 (0x5 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define CONTEXT_CONTROL_CRYPTO_ALG_GHASH (0x4 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC128 (0x1 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC192 (0x2 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define CONTEXT_CONTROL_CRYPTO_ALG_XCBC256 (0x3 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define CONTEXT_CONTROL_CRYPTO_ALG_SM3 (0x7 << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_256 (0xb << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_224 (0xc << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_512 (0xd << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define CONTEXT_CONTROL_CRYPTO_ALG_SHA3_384 (0xe << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define CONTEXT_CONTROL_CRYPTO_ALG_POLY1305 (0xf << 23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define CONTEXT_CONTROL_INV_FR (0x5 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define CONTEXT_CONTROL_INV_TR (0x6 << 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) /* control1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define CONTEXT_CONTROL_CRYPTO_MODE_ECB (0 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define CONTEXT_CONTROL_CRYPTO_MODE_CBC (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define CONTEXT_CONTROL_CHACHA20_MODE_256_32 (2 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define CONTEXT_CONTROL_CRYPTO_MODE_OFB (4 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define CONTEXT_CONTROL_CRYPTO_MODE_CFB (5 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define CONTEXT_CONTROL_CRYPTO_MODE_CTR_LOAD (6 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define CONTEXT_CONTROL_CRYPTO_MODE_XTS (7 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define CONTEXT_CONTROL_CRYPTO_MODE_XCM ((6 << 0) | BIT(17))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define CONTEXT_CONTROL_CHACHA20_MODE_CALC_OTK (12 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define CONTEXT_CONTROL_IV0 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define CONTEXT_CONTROL_IV1 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define CONTEXT_CONTROL_IV2 BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define CONTEXT_CONTROL_IV3 BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define CONTEXT_CONTROL_DIGEST_CNT BIT(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define CONTEXT_CONTROL_COUNTER_MODE BIT(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define CONTEXT_CONTROL_CRYPTO_STORE BIT(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define CONTEXT_CONTROL_HASH_STORE BIT(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define EIP197_XCM_MODE_GCM 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define EIP197_XCM_MODE_CCM 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define EIP197_AEAD_TYPE_IPSEC_ESP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define EIP197_AEAD_TYPE_IPSEC_ESP_GMAC 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define EIP197_AEAD_IPSEC_IV_SIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define EIP197_AEAD_IPSEC_NONCE_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define EIP197_AEAD_IPSEC_COUNTER_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define EIP197_AEAD_IPSEC_CCM_NONCE_SIZE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* The hash counter given to the engine in the context has a granularity of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) * 64 bits.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define EIP197_COUNTER_BLOCK_SIZE 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) /* EIP197_CS_RAM_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define EIP197_TRC_ENABLE_0 BIT(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define EIP197_TRC_ENABLE_1 BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define EIP197_TRC_ENABLE_2 BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define EIP197_TRC_ENABLE_MASK GENMASK(6, 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define EIP197_CS_BANKSEL_MASK GENMASK(14, 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define EIP197_CS_BANKSEL_OFS 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) /* EIP197_TRC_PARAMS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define EIP197_TRC_PARAMS_SW_RESET BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define EIP197_TRC_PARAMS_DATA_ACCESS BIT(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define EIP197_TRC_PARAMS_HTABLE_SZ(x) ((x) << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define EIP197_TRC_PARAMS_BLK_TIMER_SPEED(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define EIP197_TRC_PARAMS_RC_SZ_LARGE(n) ((n) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /* EIP197_TRC_FREECHAIN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define EIP197_TRC_FREECHAIN_HEAD_PTR(p) (p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define EIP197_TRC_FREECHAIN_TAIL_PTR(p) ((p) << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /* EIP197_TRC_PARAMS2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define EIP197_TRC_PARAMS2_HTABLE_PTR(p) (p)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define EIP197_TRC_PARAMS2_RC_SZ_SMALL(n) ((n) << 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /* Cache helpers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define EIP197_MIN_DSIZE 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define EIP197_MIN_ASIZE 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define EIP197_CS_TRC_REC_WC 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define EIP197_CS_RC_SIZE (4 * sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define EIP197_CS_RC_NEXT(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define EIP197_CS_RC_PREV(x) ((x) << 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define EIP197_RC_NULL 0x3ff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) /* Result data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) struct result_data_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) u32 packet_length:17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) u32 error_code:15;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) u8 bypass_length:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) u8 e15:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) u16 rsvd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) u8 hash_bytes:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) u8 hash_length:6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) u8 generic_bytes:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) u8 checksum:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) u8 next_header:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) u8 length:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) u16 application_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) u16 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) u32 rsvd2[5];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) /* Basic Result Descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) struct safexcel_result_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) u32 particle_size:17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) u8 rsvd0:3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) u8 descriptor_overflow:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) u8 buffer_overflow:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) u8 last_seg:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) u8 first_seg:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) u16 result_size:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) u32 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) u32 data_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) u32 data_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) * The EIP(1)97 only needs to fetch the descriptor part of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) * the result descriptor, not the result token part!
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define EIP197_RD64_FETCH_SIZE (sizeof(struct safexcel_result_desc) /\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define EIP197_RD64_RESULT_SIZE (sizeof(struct result_data_desc) /\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) struct safexcel_token {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) u32 packet_length:17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) u8 stat:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u16 instructions:9;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) u8 opcode:4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define EIP197_TOKEN_HASH_RESULT_VERIFY BIT(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define EIP197_TOKEN_CTX_OFFSET(x) (x)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define EIP197_TOKEN_DIRECTION_EXTERNAL BIT(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define EIP197_TOKEN_EXEC_IF_SUCCESSFUL (0x1 << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define EIP197_TOKEN_STAT_LAST_HASH BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define EIP197_TOKEN_STAT_LAST_PACKET BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define EIP197_TOKEN_OPCODE_DIRECTION 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define EIP197_TOKEN_OPCODE_INSERT 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define EIP197_TOKEN_OPCODE_NOOP EIP197_TOKEN_OPCODE_INSERT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define EIP197_TOKEN_OPCODE_RETRIEVE 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define EIP197_TOKEN_OPCODE_INSERT_REMRES 0xa
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define EIP197_TOKEN_OPCODE_VERIFY 0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define EIP197_TOKEN_OPCODE_CTX_ACCESS 0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define EIP197_TOKEN_OPCODE_BYPASS GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) static inline void eip197_noop_token(struct safexcel_token *token)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) token->opcode = EIP197_TOKEN_OPCODE_NOOP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) token->packet_length = BIT(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) token->stat = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) token->instructions = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* Instructions */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define EIP197_TOKEN_INS_INSERT_HASH_DIGEST 0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define EIP197_TOKEN_INS_ORIGIN_IV0 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define EIP197_TOKEN_INS_ORIGIN_TOKEN 0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define EIP197_TOKEN_INS_ORIGIN_LEN(x) ((x) << 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define EIP197_TOKEN_INS_TYPE_OUTPUT BIT(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define EIP197_TOKEN_INS_TYPE_HASH BIT(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define EIP197_TOKEN_INS_TYPE_CRYPTO BIT(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define EIP197_TOKEN_INS_LAST BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /* Processing Engine Control Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) struct safexcel_control_data_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) u32 packet_length:17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) u16 options:13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) u8 type:2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) u16 application_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) u16 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) u32 context_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) u32 context_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) u32 control0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) u32 control1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) u32 token[EIP197_EMB_TOKENS];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define EIP197_OPTION_MAGIC_VALUE BIT(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define EIP197_OPTION_64BIT_CTX BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define EIP197_OPTION_RC_AUTO (0x2 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define EIP197_OPTION_CTX_CTRL_IN_CMD BIT(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define EIP197_OPTION_2_TOKEN_IV_CMD GENMASK(11, 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define EIP197_OPTION_4_TOKEN_IV_CMD GENMASK(11, 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define EIP197_TYPE_BCLA 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define EIP197_TYPE_EXTENDED 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define EIP197_CONTEXT_SMALL 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define EIP197_CONTEXT_SIZE_MASK 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /* Basic Command Descriptor format */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct safexcel_command_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u32 particle_size:17;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) u8 rsvd0:5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) u8 last_seg:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) u8 first_seg:1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) u8 additional_cdata_size:8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u32 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u32 data_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) u32 data_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) u32 atok_lo;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) u32 atok_hi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) struct safexcel_control_data_desc control_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) } __packed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define EIP197_CD64_FETCH_SIZE (sizeof(struct safexcel_command_desc) /\
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) sizeof(u32))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) * Internal structures & functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) #define EIP197_FW_TERMINAL_NOPS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define EIP197_FW_START_POLLCNT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) #define EIP197_FW_PUE_READY 0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define EIP197_FW_FPP_READY 0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) enum eip197_fw {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) FW_IFPP = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) FW_IPUE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) FW_NB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct safexcel_desc_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) void *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) void *shbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) void *base_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) void *shbase_end;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) dma_addr_t base_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) dma_addr_t shbase_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) /* write and read pointers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) void *write;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) void *shwrite;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) void *read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /* descriptor element offset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) unsigned int offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) unsigned int shoffset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) enum safexcel_alg_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) SAFEXCEL_ALG_TYPE_SKCIPHER,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) SAFEXCEL_ALG_TYPE_AEAD,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) SAFEXCEL_ALG_TYPE_AHASH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) struct safexcel_config {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) u32 pes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) u32 rings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) u32 cd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) u32 cd_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) u32 cdsh_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) u32 rd_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) u32 rd_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) u32 res_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) struct safexcel_work_data {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) struct work_struct work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) struct safexcel_crypto_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) int ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) struct safexcel_ring {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) struct workqueue_struct *workqueue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) struct safexcel_work_data work_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /* command/result rings */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) struct safexcel_desc_ring cdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) struct safexcel_desc_ring rdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /* result ring crypto API request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) struct crypto_async_request **rdr_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) /* queue */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) struct crypto_queue queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) spinlock_t queue_lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) /* Number of requests in the engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) int requests;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /* The ring is currently handling at least one request */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) bool busy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* Store for current requests when bailing out of the dequeueing
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) * function when no enough resources are available.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) struct crypto_async_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) struct crypto_async_request *backlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) /* irq of this ring */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) /* EIP integration context flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) enum safexcel_eip_version {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) /* Platform (EIP integration context) specifier */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) EIP97IES_MRVL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) EIP197B_MRVL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) EIP197D_MRVL,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) EIP197_DEVBRD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /* Priority we use for advertising our algorithms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define SAFEXCEL_CRA_PRIORITY 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) /* SM3 digest result for zero length message */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) #define EIP197_SM3_ZEROM_HASH "\x1A\xB2\x1D\x83\x55\xCF\xA1\x7F" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) "\x8E\x61\x19\x48\x31\xE8\x1A\x8F" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) "\x22\xBE\xC8\xC7\x28\xFE\xFB\x74" \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) "\x7E\xD0\x35\xEB\x50\x82\xAA\x2B"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) /* EIP algorithm presence flags */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) enum safexcel_eip_algorithms {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) SAFEXCEL_ALG_BC0 = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) SAFEXCEL_ALG_SM4 = BIT(6),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) SAFEXCEL_ALG_SM3 = BIT(7),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) SAFEXCEL_ALG_CHACHA20 = BIT(8),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) SAFEXCEL_ALG_POLY1305 = BIT(9),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) SAFEXCEL_SEQMASK_256 = BIT(10),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) SAFEXCEL_SEQMASK_384 = BIT(11),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) SAFEXCEL_ALG_AES = BIT(12),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) SAFEXCEL_ALG_AES_XFB = BIT(13),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) SAFEXCEL_ALG_DES = BIT(15),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) SAFEXCEL_ALG_DES_XFB = BIT(16),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) SAFEXCEL_ALG_ARC4 = BIT(18),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) SAFEXCEL_ALG_AES_XTS = BIT(20),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) SAFEXCEL_ALG_WIRELESS = BIT(21),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) SAFEXCEL_ALG_MD5 = BIT(22),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) SAFEXCEL_ALG_SHA1 = BIT(23),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) SAFEXCEL_ALG_SHA2_256 = BIT(25),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) SAFEXCEL_ALG_SHA2_512 = BIT(26),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) SAFEXCEL_ALG_XCBC_MAC = BIT(27),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) SAFEXCEL_ALG_CBC_MAC_ALL = BIT(29),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) SAFEXCEL_ALG_GHASH = BIT(30),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) SAFEXCEL_ALG_SHA3 = BIT(31),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) struct safexcel_register_offsets {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) u32 hia_aic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) u32 hia_aic_g;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) u32 hia_aic_r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) u32 hia_aic_xdr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) u32 hia_dfe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) u32 hia_dfe_thr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) u32 hia_dse;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) u32 hia_dse_thr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) u32 hia_gen_cfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) u32 pe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) u32 global;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) enum safexcel_flags {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) EIP197_TRC_CACHE = BIT(0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) SAFEXCEL_HW_EIP197 = BIT(1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) EIP197_PE_ARB = BIT(2),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) EIP197_ICE = BIT(3),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) EIP197_SIMPLE_TRC = BIT(4),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) EIP197_OCE = BIT(5),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) struct safexcel_hwconfig {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) enum safexcel_eip_algorithms algo_flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) int hwver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) int hiaver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) int ppver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) int icever;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) int pever;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) int ocever;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int psever;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) int hwdataw;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) int hwcfsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int hwrfsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) int hwnumpes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) int hwnumrings;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) int hwnumraic;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) struct safexcel_crypto_priv {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) void __iomem *base;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) struct clk *clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) struct clk *reg_clk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) struct safexcel_config config;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) enum safexcel_eip_version version;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) struct safexcel_register_offsets offsets;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) struct safexcel_hwconfig hwconfig;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) /* context DMA pool */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) struct dma_pool *context_pool;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) atomic_t ring_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) struct safexcel_ring *ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) struct safexcel_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) int (*send)(struct crypto_async_request *req, int ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) int *commands, int *results);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) int (*handle_result)(struct safexcel_crypto_priv *priv, int ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) struct crypto_async_request *req, bool *complete,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) int *ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) struct safexcel_context_record *ctxr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) struct safexcel_crypto_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) dma_addr_t ctxr_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) __le32 le[SHA3_512_BLOCK_SIZE / 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) __be32 be[SHA3_512_BLOCK_SIZE / 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) u32 word[SHA3_512_BLOCK_SIZE / 4];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) u8 byte[SHA3_512_BLOCK_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) } ipad, opad;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) int ring;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) bool needs_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) bool exit_inv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) #define HASH_CACHE_SIZE SHA512_BLOCK_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) struct safexcel_ahash_export_state {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) u64 len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) u64 processed;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) u32 digest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) u32 state[SHA512_DIGEST_SIZE / sizeof(u32)];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) u8 cache[HASH_CACHE_SIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) * Template structure to describe the algorithms in order to register them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) * It also has the purpose to contain our private structure and is actually
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) * the only way I know in this framework to avoid having global pointers...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) struct safexcel_alg_template {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) struct safexcel_crypto_priv *priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) enum safexcel_alg_type type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) enum safexcel_eip_algorithms algo_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) union {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) struct skcipher_alg skcipher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) struct aead_alg aead;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) struct ahash_alg ahash;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) } alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) struct safexcel_inv_result {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) struct completion completion;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) int error;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) void safexcel_dequeue(struct safexcel_crypto_priv *priv, int ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) int safexcel_rdesc_check_errors(struct safexcel_crypto_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) void *rdp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) void safexcel_complete(struct safexcel_crypto_priv *priv, int ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) int safexcel_invalidate_cache(struct crypto_async_request *async,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) struct safexcel_crypto_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) dma_addr_t ctxr_dma, int ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) int safexcel_init_ring_descriptors(struct safexcel_crypto_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) struct safexcel_desc_ring *cdr,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) struct safexcel_desc_ring *rdr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) int safexcel_select_ring(struct safexcel_crypto_priv *priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) void *safexcel_ring_next_rptr(struct safexcel_crypto_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) struct safexcel_desc_ring *ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) void *safexcel_ring_first_rptr(struct safexcel_crypto_priv *priv, int ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) void safexcel_ring_rollback_wptr(struct safexcel_crypto_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct safexcel_desc_ring *ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) struct safexcel_command_desc *safexcel_add_cdesc(struct safexcel_crypto_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) int ring_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) bool first, bool last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dma_addr_t data, u32 len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) u32 full_data_len,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) dma_addr_t context,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) struct safexcel_token **atoken);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) struct safexcel_result_desc *safexcel_add_rdesc(struct safexcel_crypto_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) int ring_id,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) bool first, bool last,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) dma_addr_t data, u32 len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) int safexcel_ring_first_rdr_index(struct safexcel_crypto_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) int ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) int safexcel_ring_rdr_rdesc_index(struct safexcel_crypto_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) int ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) struct safexcel_result_desc *rdesc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) void safexcel_rdr_req_set(struct safexcel_crypto_priv *priv,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) int ring,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) struct safexcel_result_desc *rdesc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) struct crypto_async_request *req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) inline struct crypto_async_request *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) safexcel_rdr_req_get(struct safexcel_crypto_priv *priv, int ring);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) void safexcel_inv_complete(struct crypto_async_request *req, int error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) int safexcel_hmac_setkey(struct safexcel_context *base, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) unsigned int keylen, const char *alg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) unsigned int state_sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /* available algorithms */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) extern struct safexcel_alg_template safexcel_alg_ecb_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) extern struct safexcel_alg_template safexcel_alg_cbc_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) extern struct safexcel_alg_template safexcel_alg_ecb_des3_ede;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) extern struct safexcel_alg_template safexcel_alg_cbc_des3_ede;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) extern struct safexcel_alg_template safexcel_alg_ecb_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) extern struct safexcel_alg_template safexcel_alg_cbc_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) extern struct safexcel_alg_template safexcel_alg_cfb_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) extern struct safexcel_alg_template safexcel_alg_ofb_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) extern struct safexcel_alg_template safexcel_alg_ctr_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) extern struct safexcel_alg_template safexcel_alg_md5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) extern struct safexcel_alg_template safexcel_alg_sha1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) extern struct safexcel_alg_template safexcel_alg_sha224;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) extern struct safexcel_alg_template safexcel_alg_sha256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) extern struct safexcel_alg_template safexcel_alg_sha384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) extern struct safexcel_alg_template safexcel_alg_sha512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) extern struct safexcel_alg_template safexcel_alg_hmac_md5;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) extern struct safexcel_alg_template safexcel_alg_hmac_sha1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) extern struct safexcel_alg_template safexcel_alg_hmac_sha224;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) extern struct safexcel_alg_template safexcel_alg_hmac_sha256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) extern struct safexcel_alg_template safexcel_alg_hmac_sha384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) extern struct safexcel_alg_template safexcel_alg_hmac_sha512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des3_ede;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_ctr_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_ctr_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_ctr_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_ctr_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) extern struct safexcel_alg_template safexcel_alg_xts_aes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) extern struct safexcel_alg_template safexcel_alg_gcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) extern struct safexcel_alg_template safexcel_alg_ccm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) extern struct safexcel_alg_template safexcel_alg_crc32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) extern struct safexcel_alg_template safexcel_alg_cbcmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) extern struct safexcel_alg_template safexcel_alg_xcbcmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) extern struct safexcel_alg_template safexcel_alg_cmac;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) extern struct safexcel_alg_template safexcel_alg_chacha20;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) extern struct safexcel_alg_template safexcel_alg_chachapoly;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) extern struct safexcel_alg_template safexcel_alg_chachapoly_esp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) extern struct safexcel_alg_template safexcel_alg_sm3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) extern struct safexcel_alg_template safexcel_alg_hmac_sm3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) extern struct safexcel_alg_template safexcel_alg_ecb_sm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) extern struct safexcel_alg_template safexcel_alg_cbc_sm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) extern struct safexcel_alg_template safexcel_alg_ofb_sm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) extern struct safexcel_alg_template safexcel_alg_cfb_sm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) extern struct safexcel_alg_template safexcel_alg_ctr_sm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_sm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_cbc_sm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_ctr_sm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sm3_ctr_sm4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) extern struct safexcel_alg_template safexcel_alg_sha3_224;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) extern struct safexcel_alg_template safexcel_alg_sha3_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) extern struct safexcel_alg_template safexcel_alg_sha3_384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) extern struct safexcel_alg_template safexcel_alg_sha3_512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) extern struct safexcel_alg_template safexcel_alg_hmac_sha3_224;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) extern struct safexcel_alg_template safexcel_alg_hmac_sha3_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) extern struct safexcel_alg_template safexcel_alg_hmac_sha3_384;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) extern struct safexcel_alg_template safexcel_alg_hmac_sha3_512;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha1_cbc_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_des3_ede;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_des3_ede;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_des3_ede;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_des3_ede;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha256_cbc_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha224_cbc_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha512_cbc_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) extern struct safexcel_alg_template safexcel_alg_authenc_hmac_sha384_cbc_des;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) extern struct safexcel_alg_template safexcel_alg_rfc4106_gcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) extern struct safexcel_alg_template safexcel_alg_rfc4543_gcm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) extern struct safexcel_alg_template safexcel_alg_rfc4309_ccm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags