^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2019 HiSilicon Limited. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #include <asm/page.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #include <linux/acpi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #include <linux/aer.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #include <linux/bitmap.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/debugfs.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/idr.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/io.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/irqreturn.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/log2.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/seq_file.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/uacce.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/uaccess.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <uapi/misc/uacce/hisi_qm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include "qm.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* eq/aeq irq enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define QM_VF_AEQ_INT_SOURCE 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define QM_VF_AEQ_INT_MASK 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define QM_VF_EQ_INT_SOURCE 0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define QM_VF_EQ_INT_MASK 0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define QM_IRQ_NUM_V1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define QM_IRQ_NUM_PF_V2 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define QM_IRQ_NUM_VF_V2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define QM_EQ_EVENT_IRQ_VECTOR 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define QM_AEQ_EVENT_IRQ_VECTOR 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define QM_ABNORMAL_EVENT_IRQ_VECTOR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define QM_MB_CMD_SQC 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define QM_MB_CMD_CQC 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define QM_MB_CMD_EQC 0x2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define QM_MB_CMD_AEQC 0x3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define QM_MB_CMD_SQC_BT 0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define QM_MB_CMD_CQC_BT 0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define QM_MB_CMD_SQC_VFT_V2 0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define QM_MB_CMD_SEND_BASE 0x300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define QM_MB_EVENT_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define QM_MB_BUSY_SHIFT 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define QM_MB_OP_SHIFT 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define QM_MB_CMD_DATA_ADDR_L 0x304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define QM_MB_CMD_DATA_ADDR_H 0x308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) /* sqc shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define QM_SQ_HOP_NUM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define QM_SQ_PAGE_SIZE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define QM_SQ_BUF_SIZE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define QM_SQ_SQE_SIZE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define QM_SQ_PRIORITY_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define QM_SQ_ORDERS_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define QM_SQ_TYPE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define QM_SQ_TYPE_MASK GENMASK(3, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define QM_SQ_TAIL_IDX(sqc) ((le16_to_cpu((sqc)->w11) >> 6) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* cqc shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define QM_CQ_HOP_NUM_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define QM_CQ_PAGE_SIZE_SHIFT 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define QM_CQ_BUF_SIZE_SHIFT 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define QM_CQ_CQE_SIZE_SHIFT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define QM_CQ_PHASE_SHIFT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define QM_CQ_FLAG_SHIFT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define QM_CQE_PHASE(cqe) (le16_to_cpu((cqe)->w7) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define QM_QC_CQE_SIZE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define QM_CQ_TAIL_IDX(cqc) ((le16_to_cpu((cqc)->w11) >> 6) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) /* eqc shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define QM_EQE_AEQE_SIZE (2UL << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define QM_EQC_PHASE_SHIFT 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define QM_EQE_PHASE(eqe) ((le32_to_cpu((eqe)->dw0) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define QM_EQE_CQN_MASK GENMASK(15, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define QM_AEQE_PHASE(aeqe) ((le32_to_cpu((aeqe)->dw0) >> 16) & 0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define QM_AEQE_TYPE_SHIFT 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define QM_DOORBELL_CMD_SQ 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define QM_DOORBELL_CMD_CQ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define QM_DOORBELL_CMD_EQ 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define QM_DOORBELL_CMD_AEQ 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define QM_DOORBELL_BASE_V1 0x340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define QM_DB_CMD_SHIFT_V1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define QM_DB_INDEX_SHIFT_V1 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define QM_DB_PRIORITY_SHIFT_V1 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define QM_DOORBELL_SQ_CQ_BASE_V2 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define QM_DOORBELL_EQ_AEQ_BASE_V2 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define QM_DB_CMD_SHIFT_V2 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define QM_DB_RAND_SHIFT_V2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define QM_DB_INDEX_SHIFT_V2 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define QM_DB_PRIORITY_SHIFT_V2 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define QM_MEM_START_INIT 0x100040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define QM_MEM_INIT_DONE 0x100044
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define QM_VFT_CFG_RDY 0x10006c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define QM_VFT_CFG_OP_WR 0x100058
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define QM_VFT_CFG_TYPE 0x10005c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define QM_SQC_VFT 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define QM_CQC_VFT 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define QM_VFT_CFG 0x100060
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define QM_VFT_CFG_OP_ENABLE 0x100054
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define QM_VFT_CFG_DATA_L 0x100064
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define QM_VFT_CFG_DATA_H 0x100068
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define QM_SQC_VFT_BUF_SIZE (7ULL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define QM_SQC_VFT_SQC_SIZE (5ULL << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define QM_SQC_VFT_INDEX_NUMBER (1ULL << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define QM_SQC_VFT_START_SQN_SHIFT 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define QM_SQC_VFT_VALID (1ULL << 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define QM_SQC_VFT_SQN_SHIFT 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define QM_CQC_VFT_BUF_SIZE (7ULL << 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define QM_CQC_VFT_SQC_SIZE (5ULL << 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define QM_CQC_VFT_INDEX_NUMBER (1ULL << 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define QM_CQC_VFT_VALID (1ULL << 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define QM_SQC_VFT_BASE_SHIFT_V2 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define QM_SQC_VFT_BASE_MASK_V2 GENMASK(5, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define QM_SQC_VFT_NUM_SHIFT_V2 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define QM_SQC_VFT_NUM_MASK_v2 GENMASK(9, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define QM_DFX_CNT_CLR_CE 0x100118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define QM_ABNORMAL_INT_SOURCE 0x100000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define QM_ABNORMAL_INT_SOURCE_CLR GENMASK(12, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define QM_ABNORMAL_INT_MASK 0x100004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define QM_ABNORMAL_INT_MASK_VALUE 0x1fff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define QM_ABNORMAL_INT_STATUS 0x100008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define QM_ABNORMAL_INT_SET 0x10000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define QM_ABNORMAL_INF00 0x100010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define QM_FIFO_OVERFLOW_TYPE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define QM_FIFO_OVERFLOW_TYPE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define QM_FIFO_OVERFLOW_VF 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define QM_ABNORMAL_INF01 0x100014
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define QM_DB_TIMEOUT_TYPE 0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define QM_DB_TIMEOUT_TYPE_SHIFT 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define QM_DB_TIMEOUT_VF 0x3f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define QM_RAS_CE_ENABLE 0x1000ec
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define QM_RAS_FE_ENABLE 0x1000f0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define QM_RAS_NFE_ENABLE 0x1000f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define QM_RAS_CE_THRESHOLD 0x1000f8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define QM_RAS_CE_TIMES_PER_IRQ 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define QM_RAS_MSI_INT_SEL 0x1040f4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define QM_DEV_RESET_FLAG 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define QM_RESET_WAIT_TIMEOUT 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define QM_PEH_VENDOR_ID 0x1000d8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ACC_VENDOR_ID_VALUE 0x5a5a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define QM_PEH_DFX_INFO0 0x1000fc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ACC_PEH_SRIOV_CTRL_VF_MSE_SHIFT 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ACC_PEH_MSI_DISABLE GENMASK(31, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ACC_MASTER_GLOBAL_CTRL_SHUTDOWN 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ACC_MASTER_TRANS_RETURN_RW 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ACC_MASTER_TRANS_RETURN 0x300150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ACC_MASTER_GLOBAL_CTRL 0x300000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ACC_AM_CFG_PORT_WR_EN 0x30001c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define QM_RAS_NFE_MBIT_DISABLE ~QM_ECC_MBIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ACC_AM_ROB_ECC_INT_STS 0x300104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ACC_ROB_ECC_ERR_MULTPL BIT(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define POLL_PERIOD 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define POLL_TIMEOUT 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define WAIT_PERIOD_US_MAX 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define WAIT_PERIOD_US_MIN 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define MAX_WAIT_COUNTS 1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define QM_CACHE_WB_START 0x204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define QM_CACHE_WB_DONE 0x208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define PCI_BAR_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define QM_SQE_DATA_ALIGN_MASK GENMASK(6, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define QMC_ALIGN(sz) ALIGN(sz, 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define QM_DBG_READ_LEN 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define QM_DBG_WRITE_LEN 1024
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define QM_DBG_TMP_BUF_LEN 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define QM_PCI_COMMAND_INVALID ~0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define WAIT_PERIOD 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define REMOVE_WAIT_DELAY 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define QM_SQE_ADDR_MASK GENMASK(7, 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define QM_EQ_DEPTH (1024 * 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define QM_MK_CQC_DW3_V1(hop_num, pg_sz, buf_sz, cqe_sz) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) (((hop_num) << QM_CQ_HOP_NUM_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) ((pg_sz) << QM_CQ_PAGE_SIZE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) ((buf_sz) << QM_CQ_BUF_SIZE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define QM_MK_CQC_DW3_V2(cqe_sz) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) ((QM_Q_DEPTH - 1) | ((cqe_sz) << QM_CQ_CQE_SIZE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define QM_MK_SQC_W13(priority, orders, alg_type) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) (((priority) << QM_SQ_PRIORITY_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) ((orders) << QM_SQ_ORDERS_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) (((alg_type) & QM_SQ_TYPE_MASK) << QM_SQ_TYPE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define QM_MK_SQC_DW3_V1(hop_num, pg_sz, buf_sz, sqe_sz) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) (((hop_num) << QM_SQ_HOP_NUM_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) ((pg_sz) << QM_SQ_PAGE_SIZE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) ((buf_sz) << QM_SQ_BUF_SIZE_SHIFT) | \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) ((u32)ilog2(sqe_sz) << QM_SQ_SQE_SIZE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define QM_MK_SQC_DW3_V2(sqe_sz) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) ((QM_Q_DEPTH - 1) | ((u32)ilog2(sqe_sz) << QM_SQ_SQE_SIZE_SHIFT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define INIT_QC_COMMON(qc, base, pasid) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) (qc)->head = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) (qc)->tail = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) (qc)->base_l = cpu_to_le32(lower_32_bits(base)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) (qc)->base_h = cpu_to_le32(upper_32_bits(base)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) (qc)->dw3 = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) (qc)->w8 = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) (qc)->rsvd0 = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) (qc)->pasid = cpu_to_le16(pasid); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) (qc)->w11 = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) (qc)->rsvd1 = 0; \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) enum vft_type {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) SQC_VFT = 0,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) CQC_VFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) enum acc_err_result {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) ACC_ERR_NONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) ACC_ERR_NEED_RESET,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) ACC_ERR_RECOVERED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) struct qm_cqe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) __le32 rsvd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) __le16 cmd_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) __le16 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) __le16 sq_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) __le16 sq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) __le16 rsvd2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) __le16 w7;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) struct qm_eqe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) __le32 dw0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) struct qm_aeqe {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) __le32 dw0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) struct qm_sqc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) __le16 head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) __le16 tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) __le32 base_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) __le32 base_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) __le32 dw3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) __le16 w8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) __le16 rsvd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) __le16 pasid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) __le16 w11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) __le16 cq_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) __le16 w13;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) __le32 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) struct qm_cqc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) __le16 head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) __le16 tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) __le32 base_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) __le32 base_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) __le32 dw3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) __le16 w8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) __le16 rsvd0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) __le16 pasid;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) __le16 w11;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) __le32 dw6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) __le32 rsvd1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) struct qm_eqc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) __le16 head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) __le16 tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) __le32 base_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) __le32 base_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) __le32 dw3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) __le32 rsvd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) __le32 dw6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) struct qm_aeqc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) __le16 head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) __le16 tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) __le32 base_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) __le32 base_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) __le32 dw3;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) __le32 rsvd[2];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) __le32 dw6;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) struct qm_mailbox {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) __le16 w0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) __le16 queue_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) __le32 base_l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) __le32 base_h;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) __le32 rsvd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) struct qm_doorbell {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) __le16 queue_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) __le16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) __le16 index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) __le16 priority;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) struct hisi_qm_resource {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) struct hisi_qm *qm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) int distance;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) struct list_head list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) struct hisi_qm_hw_ops {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) void (*qm_db)(struct hisi_qm *qm, u16 qn,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) u8 cmd, u16 index, u8 priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) u32 (*get_irq_num)(struct hisi_qm *qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) int (*debug_init)(struct hisi_qm *qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) void (*hw_error_init)(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) void (*hw_error_uninit)(struct hisi_qm *qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) enum acc_err_result (*hw_error_handle)(struct hisi_qm *qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) struct qm_dfx_item {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) const char *name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) u32 offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) static struct qm_dfx_item qm_dfx_files[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) {"err_irq", offsetof(struct qm_dfx, err_irq_cnt)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) {"aeq_irq", offsetof(struct qm_dfx, aeq_irq_cnt)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) {"abnormal_irq", offsetof(struct qm_dfx, abnormal_irq_cnt)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) {"create_qp_err", offsetof(struct qm_dfx, create_qp_err_cnt)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) {"mb_err", offsetof(struct qm_dfx, mb_err_cnt)},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) static const char * const qm_debug_file_name[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) [CURRENT_Q] = "current_q",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) [CLEAR_ENABLE] = "clear_enable",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) struct hisi_qm_hw_error {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) u32 int_msk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) const char *msg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) static const struct hisi_qm_hw_error qm_hw_error[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) { .int_msk = BIT(0), .msg = "qm_axi_rresp" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) { .int_msk = BIT(1), .msg = "qm_axi_bresp" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) { .int_msk = BIT(2), .msg = "qm_ecc_mbit" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) { .int_msk = BIT(3), .msg = "qm_ecc_1bit" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) { .int_msk = BIT(4), .msg = "qm_acc_get_task_timeout" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) { .int_msk = BIT(5), .msg = "qm_acc_do_task_timeout" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) { .int_msk = BIT(6), .msg = "qm_acc_wb_not_ready_timeout" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) { .int_msk = BIT(7), .msg = "qm_sq_cq_vf_invalid" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) { .int_msk = BIT(8), .msg = "qm_cq_vf_invalid" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) { .int_msk = BIT(9), .msg = "qm_sq_vf_invalid" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) { .int_msk = BIT(10), .msg = "qm_db_timeout" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) { .int_msk = BIT(11), .msg = "qm_of_fifo_of" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) { .int_msk = BIT(12), .msg = "qm_db_random_invalid" },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) { /* sentinel */ }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) static const char * const qm_db_timeout[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) "sq", "cq", "eq", "aeq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) static const char * const qm_fifo_overflow[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) "cq", "eq", "aeq",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) static const char * const qm_s[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) "init", "start", "close", "stop",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) static const char * const qp_s[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) "none", "init", "start", "stop", "close",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) static bool qm_avail_state(struct hisi_qm *qm, enum qm_state new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) enum qm_state curr = atomic_read(&qm->status.flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) bool avail = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) switch (curr) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) case QM_INIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) if (new == QM_START || new == QM_CLOSE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) avail = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) case QM_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) if (new == QM_STOP)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) avail = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) case QM_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) if (new == QM_CLOSE || new == QM_START)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) avail = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) dev_dbg(&qm->pdev->dev, "change qm state from %s to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) qm_s[curr], qm_s[new]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) if (!avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) dev_warn(&qm->pdev->dev, "Can not change qm state from %s to %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) qm_s[curr], qm_s[new]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) return avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) static bool qm_qp_avail_state(struct hisi_qm *qm, struct hisi_qp *qp,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) enum qp_state new)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) enum qm_state qm_curr = atomic_read(&qm->status.flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) enum qp_state qp_curr = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) bool avail = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) if (qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) qp_curr = atomic_read(&qp->qp_status.flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) switch (new) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) case QP_INIT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) if (qm_curr == QM_START || qm_curr == QM_INIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) avail = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) case QP_START:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) if ((qm_curr == QM_START && qp_curr == QP_INIT) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) (qm_curr == QM_START && qp_curr == QP_STOP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) avail = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) case QP_STOP:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) if ((qm_curr == QM_START && qp_curr == QP_START) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) (qp_curr == QP_INIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) avail = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) case QP_CLOSE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) if ((qm_curr == QM_START && qp_curr == QP_INIT) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) (qm_curr == QM_START && qp_curr == QP_STOP) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) (qm_curr == QM_STOP && qp_curr == QP_STOP) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) (qm_curr == QM_STOP && qp_curr == QP_INIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) avail = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) dev_dbg(&qm->pdev->dev, "change qp state from %s to %s in QM %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) qp_s[qp_curr], qp_s[new], qm_s[qm_curr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) if (!avail)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) dev_warn(&qm->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) "Can not change qp state from %s to %s in QM %s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) qp_s[qp_curr], qp_s[new], qm_s[qm_curr]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) return avail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /* return 0 mailbox ready, -ETIMEDOUT hardware timeout */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) static int qm_wait_mb_ready(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) return readl_relaxed_poll_timeout(qm->io_base + QM_MB_CMD_SEND_BASE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) val, !((val >> QM_MB_BUSY_SHIFT) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) 0x1), 10, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /* 128 bit should be written to hardware at one time to trigger a mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) static void qm_mb_write(struct hisi_qm *qm, const void *src)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) unsigned long tmp0 = 0, tmp1 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) if (!IS_ENABLED(CONFIG_ARM64)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) memcpy_toio(fun_base, src, 16);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) wmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) asm volatile("ldp %0, %1, %3\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) "stp %0, %1, %2\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) "dsb sy\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) : "=&r" (tmp0),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) "=&r" (tmp1),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) "+Q" (*((char __iomem *)fun_base))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) : "Q" (*((char *)src))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) : "memory");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) static int qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) bool op)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) struct qm_mailbox mailbox;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) dev_dbg(&qm->pdev->dev, "QM mailbox request to q%u: %u-%llx\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) queue, cmd, (unsigned long long)dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) mailbox.w0 = cpu_to_le16(cmd |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) (op ? 0x1 << QM_MB_OP_SHIFT : 0) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) (0x1 << QM_MB_BUSY_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) mailbox.queue_num = cpu_to_le16(queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) mailbox.base_l = cpu_to_le32(lower_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) mailbox.base_h = cpu_to_le32(upper_32_bits(dma_addr));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) mailbox.rsvd = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) mutex_lock(&qm->mailbox_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) if (unlikely(qm_wait_mb_ready(qm))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) dev_err(&qm->pdev->dev, "QM mailbox is busy to start!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) goto busy_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) qm_mb_write(qm, &mailbox);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) if (unlikely(qm_wait_mb_ready(qm))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) dev_err(&qm->pdev->dev, "QM mailbox operation timeout!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) goto busy_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) busy_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) mutex_unlock(&qm->mailbox_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) atomic64_inc(&qm->debug.dfx.mb_err_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) static void qm_db_v1(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) u64 doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) ((u64)index << QM_DB_INDEX_SHIFT_V1) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) ((u64)priority << QM_DB_PRIORITY_SHIFT_V1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) writeq(doorbell, qm->io_base + QM_DOORBELL_BASE_V1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) static void qm_db_v2(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) u64 doorbell;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) u64 dbase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) u16 randata = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) if (cmd == QM_DOORBELL_CMD_SQ || cmd == QM_DOORBELL_CMD_CQ)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) dbase = QM_DOORBELL_SQ_CQ_BASE_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) dbase = QM_DOORBELL_EQ_AEQ_BASE_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) doorbell = qn | ((u64)cmd << QM_DB_CMD_SHIFT_V2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) ((u64)randata << QM_DB_RAND_SHIFT_V2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) ((u64)index << QM_DB_INDEX_SHIFT_V2) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) ((u64)priority << QM_DB_PRIORITY_SHIFT_V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) writeq(doorbell, qm->io_base + dbase);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) static void qm_db(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) dev_dbg(&qm->pdev->dev, "QM doorbell request: qn=%u, cmd=%u, index=%u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) qn, cmd, index);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) qm->ops->qm_db(qm, qn, cmd, index, priority);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) static int qm_dev_mem_reset(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) writel(0x1, qm->io_base + QM_MEM_START_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) val & BIT(0), 10, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) static u32 qm_get_irq_num_v1(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) return QM_IRQ_NUM_V1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) static u32 qm_get_irq_num_v2(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) if (qm->fun_type == QM_HW_PF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) return QM_IRQ_NUM_PF_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) return QM_IRQ_NUM_VF_V2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) static struct hisi_qp *qm_to_hisi_qp(struct hisi_qm *qm, struct qm_eqe *eqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) u16 cqn = le32_to_cpu(eqe->dw0) & QM_EQE_CQN_MASK;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) return &qm->qp_array[cqn];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) static void qm_cq_head_update(struct hisi_qp *qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) if (qp->qp_status.cq_head == QM_Q_DEPTH - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) qp->qp_status.cqc_phase = !qp->qp_status.cqc_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) qp->qp_status.cq_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) qp->qp_status.cq_head++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) static void qm_poll_qp(struct hisi_qp *qp, struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) if (qp->event_cb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) qp->event_cb(qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) if (qp->req_cb) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) struct qm_cqe *cqe = qp->cqe + qp->qp_status.cq_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) while (QM_CQE_PHASE(cqe) == qp->qp_status.cqc_phase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) dma_rmb();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) qp->req_cb(qp, qp->sqe + qm->sqe_size *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) le16_to_cpu(cqe->sq_head));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) qm_cq_head_update(qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) cqe = qp->cqe + qp->qp_status.cq_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) qp->qp_status.cq_head, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) atomic_dec(&qp->qp_status.used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) /* set c_flag */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) qp->qp_status.cq_head, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) static void qm_work_process(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) struct hisi_qm *qm = container_of(work, struct hisi_qm, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) struct qm_eqe *eqe = qm->eqe + qm->status.eq_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) struct hisi_qp *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int eqe_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) while (QM_EQE_PHASE(eqe) == qm->status.eqc_phase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) eqe_num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) qp = qm_to_hisi_qp(qm, eqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) qm_poll_qp(qp, qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) if (qm->status.eq_head == QM_EQ_DEPTH - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) qm->status.eqc_phase = !qm->status.eqc_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) eqe = qm->eqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) qm->status.eq_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) eqe++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) qm->status.eq_head++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) if (eqe_num == QM_EQ_DEPTH / 2 - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) eqe_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) static irqreturn_t do_qm_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) struct hisi_qm *qm = (struct hisi_qm *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) /* the workqueue created by device driver of QM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) if (qm->wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) queue_work(qm->wq, &qm->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) schedule_work(&qm->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) static irqreturn_t qm_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) struct hisi_qm *qm = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) if (readl(qm->io_base + QM_VF_EQ_INT_SOURCE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) return do_qm_irq(irq, data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) atomic64_inc(&qm->debug.dfx.err_irq_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) dev_err(&qm->pdev->dev, "invalid int source\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) static irqreturn_t qm_aeq_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) struct hisi_qm *qm = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) struct qm_aeqe *aeqe = qm->aeqe + qm->status.aeq_head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) u32 type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) atomic64_inc(&qm->debug.dfx.aeq_irq_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) if (!readl(qm->io_base + QM_VF_AEQ_INT_SOURCE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) while (QM_AEQE_PHASE(aeqe) == qm->status.aeqc_phase) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) type = le32_to_cpu(aeqe->dw0) >> QM_AEQE_TYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) if (type < ARRAY_SIZE(qm_fifo_overflow))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) dev_err(&qm->pdev->dev, "%s overflow\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) qm_fifo_overflow[type]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) dev_err(&qm->pdev->dev, "unknown error type %d\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) if (qm->status.aeq_head == QM_Q_DEPTH - 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) qm->status.aeqc_phase = !qm->status.aeqc_phase;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) aeqe = qm->aeqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) qm->status.aeq_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) aeqe++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) qm->status.aeq_head++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) static void qm_irq_unregister(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) free_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) if (qm->ver == QM_HW_V1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) free_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) if (qm->fun_type == QM_HW_PF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) free_irq(pci_irq_vector(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) QM_ABNORMAL_EVENT_IRQ_VECTOR), qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) static void qm_init_qp_status(struct hisi_qp *qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) struct hisi_qp_status *qp_status = &qp->qp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) qp_status->sq_tail = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) qp_status->cq_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) qp_status->cqc_phase = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) atomic_set(&qp_status->used, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) static void qm_vft_data_cfg(struct hisi_qm *qm, enum vft_type type, u32 base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) u32 number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) u64 tmp = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) if (number > 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) switch (type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) case SQC_VFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) if (qm->ver == QM_HW_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) tmp = QM_SQC_VFT_BUF_SIZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) QM_SQC_VFT_SQC_SIZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) QM_SQC_VFT_INDEX_NUMBER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) QM_SQC_VFT_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) (u64)base << QM_SQC_VFT_START_SQN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) tmp = (u64)base << QM_SQC_VFT_START_SQN_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) QM_SQC_VFT_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) (u64)(number - 1) << QM_SQC_VFT_SQN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) case CQC_VFT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) if (qm->ver == QM_HW_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) tmp = QM_CQC_VFT_BUF_SIZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) QM_CQC_VFT_SQC_SIZE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) QM_CQC_VFT_INDEX_NUMBER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) QM_CQC_VFT_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) tmp = QM_CQC_VFT_VALID;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) writel(lower_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_L);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) writel(upper_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_H);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) static int qm_set_vft_common(struct hisi_qm *qm, enum vft_type type,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) u32 fun_num, u32 base, u32 number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) val & BIT(0), 10, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) writel(type, qm->io_base + QM_VFT_CFG_TYPE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) writel(fun_num, qm->io_base + QM_VFT_CFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) qm_vft_data_cfg(qm, type, base, number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) val & BIT(0), 10, 1000);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) /* The config should be conducted after qm_dev_mem_reset() */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) static int qm_set_sqc_cqc_vft(struct hisi_qm *qm, u32 fun_num, u32 base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) u32 number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) for (i = SQC_VFT; i <= CQC_VFT; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) ret = qm_set_vft_common(qm, i, fun_num, base, number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) static int qm_get_vft_v2(struct hisi_qm *qm, u32 *base, u32 *number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) u64 sqc_vft;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) ret = qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) sqc_vft = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) *base = QM_SQC_VFT_BASE_MASK_V2 & (sqc_vft >> QM_SQC_VFT_BASE_SHIFT_V2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) *number = (QM_SQC_VFT_NUM_MASK_v2 &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) (sqc_vft >> QM_SQC_VFT_NUM_SHIFT_V2)) + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) static struct hisi_qm *file_to_qm(struct debugfs_file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) struct qm_debug *debug = file->debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) return container_of(debug, struct hisi_qm, debug);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) static u32 current_q_read(struct debugfs_file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) struct hisi_qm *qm = file_to_qm(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) return readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) >> QM_DFX_QN_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) static int current_q_write(struct debugfs_file *file, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) struct hisi_qm *qm = file_to_qm(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) u32 tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) if (val >= qm->debug.curr_qm_qp_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) tmp = val << QM_DFX_QN_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_FUN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) tmp = val << QM_DFX_QN_SHIFT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_FUN_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) static u32 clear_enable_read(struct debugfs_file *file)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) struct hisi_qm *qm = file_to_qm(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) return readl(qm->io_base + QM_DFX_CNT_CLR_CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) /* rd_clr_ctrl 1 enable read clear, otherwise 0 disable it */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) static int clear_enable_write(struct debugfs_file *file, u32 rd_clr_ctrl)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) struct hisi_qm *qm = file_to_qm(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) if (rd_clr_ctrl > 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) writel(rd_clr_ctrl, qm->io_base + QM_DFX_CNT_CLR_CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) static ssize_t qm_debug_read(struct file *filp, char __user *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) size_t count, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) struct debugfs_file *file = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) enum qm_debug_file index = file->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) char tbuf[QM_DBG_TMP_BUF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) mutex_lock(&file->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) case CURRENT_Q:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) val = current_q_read(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) case CLEAR_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) val = clear_enable_read(file);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) mutex_unlock(&file->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) mutex_unlock(&file->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932) ret = sprintf(tbuf, "%u\n", val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) return simple_read_from_buffer(buf, count, pos, tbuf, ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) static ssize_t qm_debug_write(struct file *filp, const char __user *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) size_t count, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) struct debugfs_file *file = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940) enum qm_debug_file index = file->index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) unsigned long val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942) char tbuf[QM_DBG_TMP_BUF_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) int len, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) if (*pos != 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948) if (count >= QM_DBG_TMP_BUF_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) len = simple_write_to_buffer(tbuf, QM_DBG_TMP_BUF_LEN - 1, pos, buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952) count);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) if (len < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) return len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) tbuf[len] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) if (kstrtoul(tbuf, 0, &val))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) mutex_lock(&file->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) switch (index) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) case CURRENT_Q:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963) ret = current_q_write(file, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) goto err_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) case CLEAR_ENABLE:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) ret = clear_enable_write(file, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) goto err_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) goto err_input;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976) mutex_unlock(&file->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) err_input:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981) mutex_unlock(&file->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) static const struct file_operations qm_debug_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) .open = simple_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) .read = qm_debug_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) .write = qm_debug_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) struct qm_dfx_registers {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) char *reg_name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) u64 reg_offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) #define CNT_CYC_REGS_NUM 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) static struct qm_dfx_registers qm_dfx_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) /* XXX_CNT are reading clear register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) {"QM_ECC_1BIT_CNT ", 0x104000ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) {"QM_ECC_MBIT_CNT ", 0x104008ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) {"QM_DFX_MB_CNT ", 0x104018ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) {"QM_DFX_DB_CNT ", 0x104028ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) {"QM_DFX_SQE_CNT ", 0x104038ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) {"QM_DFX_CQE_CNT ", 0x104048ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) {"QM_DFX_SEND_SQE_TO_ACC_CNT ", 0x104050ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) {"QM_DFX_WB_SQE_FROM_ACC_CNT ", 0x104058ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) {"QM_DFX_ACC_FINISH_CNT ", 0x104060ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) {"QM_DFX_CQE_ERR_CNT ", 0x1040b4ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) {"QM_DFX_FUNS_ACTIVE_ST ", 0x200ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) {"QM_ECC_1BIT_INF ", 0x104004ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) {"QM_ECC_MBIT_INF ", 0x10400cull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) {"QM_DFX_ACC_RDY_VLD0 ", 0x1040a0ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) {"QM_DFX_ACC_RDY_VLD1 ", 0x1040a4ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) {"QM_DFX_AXI_RDY_VLD ", 0x1040a8ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) {"QM_DFX_FF_ST0 ", 0x1040c8ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) {"QM_DFX_FF_ST1 ", 0x1040ccull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) {"QM_DFX_FF_ST2 ", 0x1040d0ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) {"QM_DFX_FF_ST3 ", 0x1040d4ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) {"QM_DFX_FF_ST4 ", 0x1040d8ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) {"QM_DFX_FF_ST5 ", 0x1040dcull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) {"QM_DFX_FF_ST6 ", 0x1040e0ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023) {"QM_IN_IDLE_ST ", 0x1040e4ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) { NULL, 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) static struct qm_dfx_registers qm_vf_dfx_regs[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) {"QM_DFX_FUNS_ACTIVE_ST ", 0x200ull},
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029) { NULL, 0}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) static int qm_regs_show(struct seq_file *s, void *unused)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) struct hisi_qm *qm = s->private;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) struct qm_dfx_registers *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) if (qm->fun_type == QM_HW_PF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) regs = qm_dfx_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041) regs = qm_vf_dfx_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) while (regs->reg_name) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) val = readl(qm->io_base + regs->reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) seq_printf(s, "%s= 0x%08x\n", regs->reg_name, val);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) regs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) DEFINE_SHOW_ATTRIBUTE(qm_regs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054) static ssize_t qm_cmd_read(struct file *filp, char __user *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) size_t count, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) char buf[QM_DBG_READ_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) int len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) len = scnprintf(buf, QM_DBG_READ_LEN, "%s\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061) "Please echo help to cmd to get help information");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) return simple_read_from_buffer(buffer, count, pos, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) static void *qm_ctx_alloc(struct hisi_qm *qm, size_t ctx_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067) dma_addr_t *dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070) void *ctx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) ctx_addr = kzalloc(ctx_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) if (!ctx_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) *dma_addr = dma_map_single(dev, ctx_addr, ctx_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) if (dma_mapping_error(dev, *dma_addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) dev_err(dev, "DMA mapping error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079) kfree(ctx_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) return ERR_PTR(-ENOMEM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) return ctx_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) static void qm_ctx_free(struct hisi_qm *qm, size_t ctx_size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) const void *ctx_addr, dma_addr_t *dma_addr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091) dma_unmap_single(dev, *dma_addr, ctx_size, DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) kfree(ctx_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) static int dump_show(struct hisi_qm *qm, void *info,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) unsigned int info_size, char *info_name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) u8 *info_buf, *info_curr = info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) #define BYTE_PER_DW 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) info_buf = kzalloc(info_size, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) if (!info_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) for (i = 0; i < info_size; i++, info_curr++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108) if (i % BYTE_PER_DW == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) info_buf[i + 3UL] = *info_curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) else if (i % BYTE_PER_DW == 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111) info_buf[i + 1UL] = *info_curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) else if (i % BYTE_PER_DW == 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) info_buf[i - 1] = *info_curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) else if (i % BYTE_PER_DW == 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) info_buf[i - 3] = *info_curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) dev_info(dev, "%s DUMP\n", info_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) for (i = 0; i < info_size; i += BYTE_PER_DW) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120) pr_info("DW%d: %02X%02X %02X%02X\n", i / BYTE_PER_DW,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) info_buf[i], info_buf[i + 1UL],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) info_buf[i + 2UL], info_buf[i + 3UL]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) kfree(info_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) static int qm_dump_sqc_raw(struct hisi_qm *qm, dma_addr_t dma_addr, u16 qp_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) return qm_mb(qm, QM_MB_CMD_SQC, dma_addr, qp_id, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) static int qm_dump_cqc_raw(struct hisi_qm *qm, dma_addr_t dma_addr, u16 qp_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) return qm_mb(qm, QM_MB_CMD_CQC, dma_addr, qp_id, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) static int qm_sqc_dump(struct hisi_qm *qm, const char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) struct qm_sqc *sqc, *sqc_curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144) dma_addr_t sqc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) u32 qp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) ret = kstrtou32(s, 0, &qp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) if (ret || qp_id >= qm->qp_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) dev_err(dev, "Please input qp num (0-%d)", qm->qp_num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) sqc = qm_ctx_alloc(qm, sizeof(*sqc), &sqc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) if (IS_ERR(sqc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) return PTR_ERR(sqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) ret = qm_dump_sqc_raw(qm, sqc_dma, qp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) down_read(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) if (qm->sqc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) sqc_curr = qm->sqc + qp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) ret = dump_show(qm, sqc_curr, sizeof(*sqc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) "SOFT SQC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) dev_info(dev, "Show soft sqc failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) up_read(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) goto err_free_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) ret = dump_show(qm, sqc, sizeof(*sqc), "SQC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) dev_info(dev, "Show hw sqc failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) err_free_ctx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) qm_ctx_free(qm, sizeof(*sqc), sqc, &sqc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) static int qm_cqc_dump(struct hisi_qm *qm, const char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) struct qm_cqc *cqc, *cqc_curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) dma_addr_t cqc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) u32 qp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) ret = kstrtou32(s, 0, &qp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) if (ret || qp_id >= qm->qp_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199) dev_err(dev, "Please input qp num (0-%d)", qm->qp_num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) cqc = qm_ctx_alloc(qm, sizeof(*cqc), &cqc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204) if (IS_ERR(cqc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) return PTR_ERR(cqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207) ret = qm_dump_cqc_raw(qm, cqc_dma, qp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) down_read(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) if (qm->cqc) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211) cqc_curr = qm->cqc + qp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) ret = dump_show(qm, cqc_curr, sizeof(*cqc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) "SOFT CQC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) dev_info(dev, "Show soft cqc failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) up_read(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220) goto err_free_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) ret = dump_show(qm, cqc, sizeof(*cqc), "CQC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) dev_info(dev, "Show hw cqc failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) err_free_ctx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) qm_ctx_free(qm, sizeof(*cqc), cqc, &cqc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) static int qm_eqc_aeqc_dump(struct hisi_qm *qm, char *s, size_t size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) int cmd, char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) dma_addr_t xeqc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237) void *xeqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240) if (strsep(&s, " ")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) dev_err(dev, "Please do not input extra characters!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) xeqc = qm_ctx_alloc(qm, size, &xeqc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246) if (IS_ERR(xeqc))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) return PTR_ERR(xeqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) ret = qm_mb(qm, cmd, xeqc_dma, 0, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) goto err_free_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253) ret = dump_show(qm, xeqc, size, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) dev_info(dev, "Show hw %s failed!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) err_free_ctx:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) qm_ctx_free(qm, size, xeqc, &xeqc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) static int q_dump_param_parse(struct hisi_qm *qm, char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) u32 *e_id, u32 *q_id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) unsigned int qp_num = qm->qp_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) char *presult;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) presult = strsep(&s, " ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) if (!presult) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) dev_err(dev, "Please input qp number!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) ret = kstrtou32(presult, 0, q_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) if (ret || *q_id >= qp_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) dev_err(dev, "Please input qp num (0-%d)", qp_num - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) presult = strsep(&s, " ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283) if (!presult) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) dev_err(dev, "Please input sqe number!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) ret = kstrtou32(presult, 0, e_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289) if (ret || *e_id >= QM_Q_DEPTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) dev_err(dev, "Please input sqe num (0-%d)", QM_Q_DEPTH - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) if (strsep(&s, " ")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) dev_err(dev, "Please do not input extra characters!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) static int qm_sq_dump(struct hisi_qm *qm, char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) void *sqe, *sqe_curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) struct hisi_qp *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) u32 qp_id, sqe_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) ret = q_dump_param_parse(qm, s, &sqe_id, &qp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) sqe = kzalloc(qm->sqe_size * QM_Q_DEPTH, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) if (!sqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) qp = &qm->qp_array[qp_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319) memcpy(sqe, qp->sqe, qm->sqe_size * QM_Q_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) sqe_curr = sqe + (u32)(sqe_id * qm->sqe_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) memset(sqe_curr + qm->debug.sqe_mask_offset, QM_SQE_ADDR_MASK,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) qm->debug.sqe_mask_len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) ret = dump_show(qm, sqe_curr, qm->sqe_size, "SQE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) dev_info(dev, "Show sqe failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) kfree(sqe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) static int qm_cq_dump(struct hisi_qm *qm, char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) struct qm_cqe *cqe_curr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337) struct hisi_qp *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) u32 qp_id, cqe_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341) ret = q_dump_param_parse(qm, s, &cqe_id, &qp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) qp = &qm->qp_array[qp_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) cqe_curr = qp->cqe + cqe_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) ret = dump_show(qm, cqe_curr, sizeof(struct qm_cqe), "CQE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) dev_info(dev, "Show cqe failed!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) static int qm_eq_aeq_dump(struct hisi_qm *qm, const char *s,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) size_t size, char *name)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) void *xeqe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359) u32 xeqe_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) ret = kstrtou32(s, 0, &xeqe_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369) if (!strcmp(name, "EQE") && xeqe_id >= QM_EQ_DEPTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) dev_err(dev, "Please input eqe num (0-%d)", QM_EQ_DEPTH - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) } else if (!strcmp(name, "AEQE") && xeqe_id >= QM_Q_DEPTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) dev_err(dev, "Please input aeqe num (0-%d)", QM_Q_DEPTH - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377) down_read(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) if (qm->eqe && !strcmp(name, "EQE")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) xeqe = qm->eqe + xeqe_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) } else if (qm->aeqe && !strcmp(name, "AEQE")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382) xeqe = qm->aeqe + xeqe_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) ret = dump_show(qm, xeqe, size, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) dev_info(dev, "Show %s failed!\n", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) up_read(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) static int qm_dbg_help(struct hisi_qm *qm, char *s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401) if (strsep(&s, " ")) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) dev_err(dev, "Please do not input extra characters!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406) dev_info(dev, "available commands:\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) dev_info(dev, "sqc <num>\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) dev_info(dev, "cqc <num>\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409) dev_info(dev, "eqc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) dev_info(dev, "aeqc\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) dev_info(dev, "sq <num> <e>\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) dev_info(dev, "cq <num> <e>\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) dev_info(dev, "eq <e>\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) dev_info(dev, "aeq <e>\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) static int qm_cmd_write_dump(struct hisi_qm *qm, const char *cmd_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) char *presult, *s, *s_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425) s = kstrdup(cmd_buf, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) if (!s)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) s_tmp = s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) presult = strsep(&s, " ");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) if (!presult) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) goto err_buffer_free;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) if (!strcmp(presult, "sqc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) ret = qm_sqc_dump(qm, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438) else if (!strcmp(presult, "cqc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) ret = qm_cqc_dump(qm, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) else if (!strcmp(presult, "eqc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) ret = qm_eqc_aeqc_dump(qm, s, sizeof(struct qm_eqc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) QM_MB_CMD_EQC, "EQC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) else if (!strcmp(presult, "aeqc"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) ret = qm_eqc_aeqc_dump(qm, s, sizeof(struct qm_aeqc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445) QM_MB_CMD_AEQC, "AEQC");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) else if (!strcmp(presult, "sq"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) ret = qm_sq_dump(qm, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) else if (!strcmp(presult, "cq"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) ret = qm_cq_dump(qm, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) else if (!strcmp(presult, "eq"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451) ret = qm_eq_aeq_dump(qm, s, sizeof(struct qm_eqe), "EQE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) else if (!strcmp(presult, "aeq"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453) ret = qm_eq_aeq_dump(qm, s, sizeof(struct qm_aeqe), "AEQE");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) else if (!strcmp(presult, "help"))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) ret = qm_dbg_help(qm, s);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) dev_info(dev, "Please echo help\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462) err_buffer_free:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) kfree(s_tmp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468) static ssize_t qm_cmd_write(struct file *filp, const char __user *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) size_t count, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) struct hisi_qm *qm = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) char *cmd_buf, *cmd_buf_tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) if (*pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) /* Judge if the instance is being reset. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) if (unlikely(atomic_read(&qm->status.flags) == QM_STOP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) if (count > QM_DBG_WRITE_LEN)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) return -ENOSPC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) cmd_buf = kzalloc(count + 1, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486) if (!cmd_buf)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) if (copy_from_user(cmd_buf, buffer, count)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) kfree(cmd_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) cmd_buf[count] = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) cmd_buf_tmp = strchr(cmd_buf, '\n');
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) if (cmd_buf_tmp) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) *cmd_buf_tmp = '\0';
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) count = cmd_buf_tmp - cmd_buf + 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) ret = qm_cmd_write_dump(qm, cmd_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) kfree(cmd_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) kfree(cmd_buf);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510) return count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) static const struct file_operations qm_cmd_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) .open = simple_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) .read = qm_cmd_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517) .write = qm_cmd_write,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520) static int qm_create_debugfs_file(struct hisi_qm *qm, enum qm_debug_file index)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) struct dentry *qm_d = qm->debug.qm_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523) struct debugfs_file *file = qm->debug.files + index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) debugfs_create_file(qm_debug_file_name[index], 0600, qm_d, file,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) &qm_debug_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) file->index = index;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) mutex_init(&file->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) file->debug = &qm->debug;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) static void qm_hw_error_init_v1(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) static void qm_hw_error_init_v2(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542) u32 irq_enable = ce | nfe | fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) u32 irq_unmask = ~irq_enable;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) qm->error_mask = ce | nfe | fe;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) /* clear QM hw residual error source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) writel(QM_ABNORMAL_INT_SOURCE_CLR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) qm->io_base + QM_ABNORMAL_INT_SOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) /* configure error type */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) writel(ce, qm->io_base + QM_RAS_CE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) writel(QM_RAS_CE_TIMES_PER_IRQ, qm->io_base + QM_RAS_CE_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) writel(nfe, qm->io_base + QM_RAS_NFE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) writel(fe, qm->io_base + QM_RAS_FE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) static void qm_hw_error_uninit_v2(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568) const struct hisi_qm_hw_error *err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) u32 reg_val, type, vf_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) for (i = 0; i < ARRAY_SIZE(qm_hw_error); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574) err = &qm_hw_error[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) if (!(err->int_msk & error_status))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) dev_err(dev, "%s [error status=0x%x] found\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579) err->msg, err->int_msk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) if (err->int_msk & QM_DB_TIMEOUT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) reg_val = readl(qm->io_base + QM_ABNORMAL_INF01);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) type = (reg_val & QM_DB_TIMEOUT_TYPE) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) QM_DB_TIMEOUT_TYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) vf_num = reg_val & QM_DB_TIMEOUT_VF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) dev_err(dev, "qm %s doorbell timeout in function %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) qm_db_timeout[type], vf_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) } else if (err->int_msk & QM_OF_FIFO_OF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) reg_val = readl(qm->io_base + QM_ABNORMAL_INF00);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590) type = (reg_val & QM_FIFO_OVERFLOW_TYPE) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) QM_FIFO_OVERFLOW_TYPE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) vf_num = reg_val & QM_FIFO_OVERFLOW_VF;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) if (type < ARRAY_SIZE(qm_fifo_overflow))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) dev_err(dev, "qm %s fifo overflow in function %u\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) qm_fifo_overflow[type], vf_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) dev_err(dev, "unknown error type\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) static enum acc_err_result qm_hw_error_handle_v2(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) u32 error_status, tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) /* read err sts */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608) tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) error_status = qm->error_mask & tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) if (error_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612) if (error_status & QM_ECC_MBIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) qm->err_status.is_qm_ecc_mbit = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615) qm_log_hw_error(qm, error_status);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) if (error_status == QM_DB_RANDOM_INVALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) writel(error_status, qm->io_base +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) QM_ABNORMAL_INT_SOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) return ACC_ERR_RECOVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622) return ACC_ERR_NEED_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625) return ACC_ERR_RECOVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628) static const struct hisi_qm_hw_ops qm_hw_ops_v1 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) .qm_db = qm_db_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) .get_irq_num = qm_get_irq_num_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) .hw_error_init = qm_hw_error_init_v1,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) static const struct hisi_qm_hw_ops qm_hw_ops_v2 = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) .get_vft = qm_get_vft_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) .qm_db = qm_db_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) .get_irq_num = qm_get_irq_num_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638) .hw_error_init = qm_hw_error_init_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) .hw_error_uninit = qm_hw_error_uninit_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) .hw_error_handle = qm_hw_error_handle_v2,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) static void *qm_get_avail_sqe(struct hisi_qp *qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645) struct hisi_qp_status *qp_status = &qp->qp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) u16 sq_tail = qp_status->sq_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648) if (unlikely(atomic_read(&qp->qp_status.used) == QM_Q_DEPTH - 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) return NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651) return qp->sqe + sq_tail * qp->qm->sqe_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) static struct hisi_qp *qm_create_qp_nolock(struct hisi_qm *qm, u8 alg_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) struct hisi_qp *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) int qp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) if (!qm_qp_avail_state(qm, NULL, QP_INIT))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) return ERR_PTR(-EPERM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) if (qm->qp_in_used == qm->qp_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) dev_info_ratelimited(dev, "All %u queues of QM are busy!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665) qm->qp_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) atomic64_inc(&qm->debug.dfx.create_qp_err_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) return ERR_PTR(-EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) qp_id = idr_alloc_cyclic(&qm->qp_idr, NULL, 0, qm->qp_num, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) if (qp_id < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) dev_info_ratelimited(dev, "All %u queues of QM are busy!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) qm->qp_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) atomic64_inc(&qm->debug.dfx.create_qp_err_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675) return ERR_PTR(-EBUSY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) qp = &qm->qp_array[qp_id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) memset(qp->cqe, 0, sizeof(struct qm_cqe) * QM_Q_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) qp->event_cb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) qp->req_cb = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) qp->qp_id = qp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685) qp->alg_type = alg_type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) qm->qp_in_used++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) atomic_set(&qp->qp_status.flags, QP_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) return qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693) * hisi_qm_create_qp() - Create a queue pair from qm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) * @qm: The qm we create a qp from.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) * @alg_type: Accelerator specific algorithm type in sqc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) * return created qp, -EBUSY if all qps in qm allocated, -ENOMEM if allocating
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) * qp memory fails.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700) struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) struct hisi_qp *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704) down_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) qp = qm_create_qp_nolock(qm, alg_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) return qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710) EXPORT_SYMBOL_GPL(hisi_qm_create_qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) * hisi_qm_release_qp() - Release a qp back to its qm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) * @qp: The qp we want to release.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) * This function releases the resource of a qp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) void hisi_qm_release_qp(struct hisi_qp *qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) struct hisi_qm *qm = qp->qm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) down_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) if (!qm_qp_avail_state(qm, qp, QP_CLOSE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) qm->qp_in_used--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) idr_remove(&qm->qp_idr, qp->qp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) EXPORT_SYMBOL_GPL(hisi_qm_release_qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) static int qm_qp_ctx_cfg(struct hisi_qp *qp, int qp_id, u32 pasid)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) struct hisi_qm *qm = qp->qm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) enum qm_hw_ver ver = qm->ver;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) struct qm_sqc *sqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) struct qm_cqc *cqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) dma_addr_t sqc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) dma_addr_t cqc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) qm_init_qp_status(qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749) sqc = kzalloc(sizeof(struct qm_sqc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) if (!sqc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) sqc_dma = dma_map_single(dev, sqc, sizeof(struct qm_sqc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (dma_mapping_error(dev, sqc_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) kfree(sqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759) INIT_QC_COMMON(sqc, qp->sqe_dma, pasid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) if (ver == QM_HW_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V1(0, 0, 0, qm->sqe_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) sqc->w8 = cpu_to_le16(QM_Q_DEPTH - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V2(qm->sqe_size));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) sqc->w8 = 0; /* rand_qc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) sqc->cq_num = cpu_to_le16(qp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) sqc->w13 = cpu_to_le16(QM_MK_SQC_W13(0, 1, qp->alg_type));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) ret = qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) dma_unmap_single(dev, sqc_dma, sizeof(struct qm_sqc), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) kfree(sqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776) cqc = kzalloc(sizeof(struct qm_cqc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) if (!cqc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) cqc_dma = dma_map_single(dev, cqc, sizeof(struct qm_cqc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) if (dma_mapping_error(dev, cqc_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) kfree(cqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) INIT_QC_COMMON(cqc, qp->cqe_dma, pasid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) if (ver == QM_HW_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788) cqc->dw3 = cpu_to_le32(QM_MK_CQC_DW3_V1(0, 0, 0, 4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) cqc->w8 = cpu_to_le16(QM_Q_DEPTH - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) cqc->dw3 = cpu_to_le32(QM_MK_CQC_DW3_V2(4));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) cqc->w8 = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) cqc->dw6 = cpu_to_le32(1 << QM_CQ_PHASE_SHIFT | 1 << QM_CQ_FLAG_SHIFT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) ret = qm_mb(qm, QM_MB_CMD_CQC, cqc_dma, qp_id, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) dma_unmap_single(dev, cqc_dma, sizeof(struct qm_cqc), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) kfree(cqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) static int qm_start_qp_nolock(struct hisi_qp *qp, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) struct hisi_qm *qm = qp->qm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) int qp_id = qp->qp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) u32 pasid = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) if (!qm_qp_avail_state(qm, qp, QP_START))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814) ret = qm_qp_ctx_cfg(qp, qp_id, pasid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) atomic_set(&qp->qp_status.flags, QP_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819) dev_dbg(dev, "queue %d started\n", qp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) * hisi_qm_start_qp() - Start a qp into running.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826) * @qp: The qp we want to start to run.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) * @arg: Accelerator specific argument.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) * After this function, qp can receive request from user. Return 0 if
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) * successful, Return -EBUSY if failed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) int hisi_qm_start_qp(struct hisi_qp *qp, unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) struct hisi_qm *qm = qp->qm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) down_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) ret = qm_start_qp_nolock(qp, arg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) EXPORT_SYMBOL_GPL(hisi_qm_start_qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) * Determine whether the queue is cleared by judging the tail pointers of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) * sq and cq.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) static int qm_drain_qp(struct hisi_qp *qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) size_t size = sizeof(struct qm_sqc) + sizeof(struct qm_cqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) struct hisi_qm *qm = qp->qm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854) struct qm_sqc *sqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) struct qm_cqc *cqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856) dma_addr_t dma_addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) int ret = 0, i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) void *addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) * No need to judge if ECC multi-bit error occurs because the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862) * master OOO will be blocked.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) if (qm->err_status.is_qm_ecc_mbit || qm->err_status.is_dev_ecc_mbit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867) addr = qm_ctx_alloc(qm, size, &dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) if (IS_ERR(addr)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) dev_err(dev, "Failed to alloc ctx for sqc and cqc!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873) while (++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) ret = qm_dump_sqc_raw(qm, dma_addr, qp->qp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) dev_err_ratelimited(dev, "Failed to dump sqc!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) sqc = addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) ret = qm_dump_cqc_raw(qm, (dma_addr + sizeof(struct qm_sqc)),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) qp->qp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) dev_err_ratelimited(dev, "Failed to dump cqc!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887) cqc = addr + sizeof(struct qm_sqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) if ((sqc->tail == cqc->tail) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) (QM_SQ_TAIL_IDX(sqc) == QM_CQ_TAIL_IDX(cqc)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) if (i == MAX_WAIT_COUNTS) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) dev_err(dev, "Fail to empty queue %u!\n", qp->qp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) usleep_range(WAIT_PERIOD_US_MIN, WAIT_PERIOD_US_MAX);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) qm_ctx_free(qm, size, addr, &dma_addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) static int qm_stop_qp_nolock(struct hisi_qp *qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) struct device *dev = &qp->qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) * It is allowed to stop and release qp when reset, If the qp is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) * stopped when reset but still want to be released then, the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) * is_resetting flag should be set negative so that this qp will not
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) * be restarted after reset.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) if (atomic_read(&qp->qp_status.flags) == QP_STOP) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919) qp->is_resetting = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) if (!qm_qp_avail_state(qp->qm, qp, QP_STOP))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) atomic_set(&qp->qp_status.flags, QP_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) ret = qm_drain_qp(qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) dev_err(dev, "Failed to drain out data for stopping!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) if (qp->qm->wq)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) flush_workqueue(qp->qm->wq);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) flush_work(&qp->qm->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) dev_dbg(dev, "stop queue %u!", qp->qp_id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) * hisi_qm_stop_qp() - Stop a qp in qm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) * @qp: The qp we want to stop.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) * This function is reverse of hisi_qm_start_qp. Return 0 if successful.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948) int hisi_qm_stop_qp(struct hisi_qp *qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952) down_write(&qp->qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) ret = qm_stop_qp_nolock(qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954) up_write(&qp->qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) EXPORT_SYMBOL_GPL(hisi_qm_stop_qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) * hisi_qp_send() - Queue up a task in the hardware queue.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) * @qp: The qp in which to put the message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) * @msg: The message.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) * This function will return -EBUSY if qp is currently full, and -EAGAIN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) * if qp related qm is resetting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) * Note: This function may run with qm_irq_thread and ACC reset at same time.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) * It has no race with qm_irq_thread. However, during hisi_qp_send, ACC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) * reset may happen, we have no lock here considering performance. This
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971) * causes current qm_db sending fail or can not receive sended sqe. QM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) * sync/async receive function should handle the error sqe. ACC reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973) * done function should clear used sqe to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) int hisi_qp_send(struct hisi_qp *qp, const void *msg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) struct hisi_qp_status *qp_status = &qp->qp_status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) u16 sq_tail = qp_status->sq_tail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979) u16 sq_tail_next = (sq_tail + 1) % QM_Q_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) void *sqe = qm_get_avail_sqe(qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) if (unlikely(atomic_read(&qp->qp_status.flags) == QP_STOP ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) atomic_read(&qp->qm->status.flags) == QM_STOP ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) qp->is_resetting)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985) dev_info_ratelimited(&qp->qm->pdev->dev, "QP is stopped or resetting\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) return -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) if (!sqe)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) memcpy(sqe, msg, qp->qm->sqe_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) qm_db(qp->qm, qp->qp_id, QM_DOORBELL_CMD_SQ, sq_tail_next, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) atomic_inc(&qp->qp_status.used);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996) qp_status->sq_tail = sq_tail_next;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) EXPORT_SYMBOL_GPL(hisi_qp_send);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) static void hisi_qm_cache_wb(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) unsigned int val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006) if (qm->ver == QM_HW_V1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) writel(0x1, qm->io_base + QM_CACHE_WB_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) val, val & BIT(0), 10, 1000))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) dev_err(&qm->pdev->dev, "QM writeback sqc cache fail!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) static void qm_qp_event_notifier(struct hisi_qp *qp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017) wake_up_interruptible(&qp->uacce_q->wait);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) static int hisi_qm_get_available_instances(struct uacce_device *uacce)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) return hisi_qm_get_free_qp_num(uacce->priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) static int hisi_qm_uacce_get_queue(struct uacce_device *uacce,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) unsigned long arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) struct uacce_queue *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) struct hisi_qm *qm = uacce->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030) struct hisi_qp *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) u8 alg_type = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) qp = hisi_qm_create_qp(qm, alg_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) if (IS_ERR(qp))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) return PTR_ERR(qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) q->priv = qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) q->uacce = uacce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039) qp->uacce_q = q;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) qp->event_cb = qm_qp_event_notifier;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) qp->pasid = arg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046) static void hisi_qm_uacce_put_queue(struct uacce_queue *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) struct hisi_qp *qp = q->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) hisi_qm_cache_wb(qp->qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) hisi_qm_release_qp(qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) /* map sq/cq/doorbell to user space */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055) static int hisi_qm_uacce_mmap(struct uacce_queue *q,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) struct vm_area_struct *vma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) struct uacce_qfile_region *qfr)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) struct hisi_qp *qp = q->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060) struct hisi_qm *qm = qp->qm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) size_t sz = vma->vm_end - vma->vm_start;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) unsigned long vm_pgoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) switch (qfr->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068) case UACCE_QFRT_MMIO:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) if (qm->ver == QM_HW_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) if (sz > PAGE_SIZE * QM_DOORBELL_PAGE_NR)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) if (sz > PAGE_SIZE * (QM_DOORBELL_PAGE_NR +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) QM_DOORBELL_SQ_CQ_BASE_V2 / PAGE_SIZE))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) vma->vm_flags |= VM_IO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) return remap_pfn_range(vma, vma->vm_start,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) qm->phys_base >> PAGE_SHIFT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082) sz, pgprot_noncached(vma->vm_page_prot));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) case UACCE_QFRT_DUS:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) if (sz != qp->qdma.size)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) * dma_mmap_coherent() requires vm_pgoff as 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) * restore vm_pfoff to initial value for mmap()
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) vm_pgoff = vma->vm_pgoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) vma->vm_pgoff = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) ret = dma_mmap_coherent(dev, vma, qp->qdma.va,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) qp->qdma.dma, sz);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) vma->vm_pgoff = vm_pgoff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) static int hisi_qm_uacce_start_queue(struct uacce_queue *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) struct hisi_qp *qp = q->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) return hisi_qm_start_qp(qp, qp->pasid);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) static void hisi_qm_uacce_stop_queue(struct uacce_queue *q)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) hisi_qm_stop_qp(q->priv);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) static int qm_set_sqctype(struct uacce_queue *q, u16 type)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) struct hisi_qm *qm = q->uacce->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) struct hisi_qp *qp = q->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) down_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) qp->alg_type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) static long hisi_qm_uacce_ioctl(struct uacce_queue *q, unsigned int cmd,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) unsigned long arg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) struct hisi_qp *qp = q->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) struct hisi_qp_ctx qp_ctx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133) if (cmd == UACCE_CMD_QM_SET_QP_CTX) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) if (copy_from_user(&qp_ctx, (void __user *)arg,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) sizeof(struct hisi_qp_ctx)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) if (qp_ctx.qc_type != 0 && qp_ctx.qc_type != 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) qm_set_sqctype(q, qp_ctx.qc_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) qp_ctx.id = qp->qp_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) if (copy_to_user((void __user *)arg, &qp_ctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) sizeof(struct hisi_qp_ctx)))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) static const struct uacce_ops uacce_qm_ops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) .get_available_instances = hisi_qm_get_available_instances,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) .get_queue = hisi_qm_uacce_get_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157) .put_queue = hisi_qm_uacce_put_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) .start_queue = hisi_qm_uacce_start_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) .stop_queue = hisi_qm_uacce_stop_queue,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) .mmap = hisi_qm_uacce_mmap,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) .ioctl = hisi_qm_uacce_ioctl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) static int qm_alloc_uacce(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) struct uacce_device *uacce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) unsigned long mmio_page_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) unsigned long dus_page_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) struct uacce_interface interface = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) .flags = UACCE_DEV_SVA,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) .ops = &uacce_qm_ops,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) ret = strscpy(interface.name, pdev->driver->name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) sizeof(interface.name));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) return -ENAMETOOLONG;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181) uacce = uacce_alloc(&pdev->dev, &interface);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) if (IS_ERR(uacce))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) return PTR_ERR(uacce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) if (uacce->flags & UACCE_DEV_SVA) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) qm->use_sva = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) /* only consider sva case */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) uacce_remove(uacce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) qm->uacce = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) uacce->is_vf = pdev->is_virtfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) uacce->priv = qm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) uacce->algs = qm->algs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) if (qm->ver == QM_HW_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) mmio_page_nr = QM_DOORBELL_PAGE_NR;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) uacce->api_ver = HISI_QM_API_VER_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) mmio_page_nr = QM_DOORBELL_PAGE_NR +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) QM_DOORBELL_SQ_CQ_BASE_V2 / PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) uacce->api_ver = HISI_QM_API_VER2_BASE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) dus_page_nr = (PAGE_SIZE - 1 + qm->sqe_size * QM_Q_DEPTH +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) sizeof(struct qm_cqe) * QM_Q_DEPTH) >> PAGE_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) uacce->qf_pg_num[UACCE_QFRT_MMIO] = mmio_page_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) uacce->qf_pg_num[UACCE_QFRT_DUS] = dus_page_nr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) qm->uacce = uacce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) * qm_frozen() - Try to froze QM to cut continuous queue request. If
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) * there is user on the QM, return failure without doing anything.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) * @qm: The qm needed to be fronzen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) * This function frozes QM, then we can do SRIOV disabling.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) static int qm_frozen(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227) down_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) if (qm->is_frozen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234) if (!qm->qp_in_used) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) qm->qp_in_used = qm->qp_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) qm->is_frozen = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) static int qm_try_frozen_vfs(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) struct hisi_qm_list *qm_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) struct hisi_qm *qm, *vf_qm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) struct pci_dev *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) if (!qm_list || !pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) /* Try to frozen all the VFs as disable SRIOV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) mutex_lock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) list_for_each_entry(qm, &qm_list->list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) dev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) if (dev == pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) if (pci_physfn(dev) == pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) vf_qm = pci_get_drvdata(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) ret = qm_frozen(vf_qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) goto frozen_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) frozen_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) mutex_unlock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) * hisi_qm_wait_task_finish() - Wait until the task is finished
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) * when removing the driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) * @qm: The qm needed to wait for the task to finish.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280) * @qm_list: The list of all available devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) while (qm_frozen(qm) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) ((qm->fun_type == QM_HW_PF) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) qm_try_frozen_vfs(qm->pdev, qm_list))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) msleep(WAIT_PERIOD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) udelay(REMOVE_WAIT_DELAY);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) EXPORT_SYMBOL_GPL(hisi_qm_wait_task_finish);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) * hisi_qm_get_free_qp_num() - Get free number of qp in qm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) * @qm: The qm which want to get free qp.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) * This function return free number of qp in qm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) int hisi_qm_get_free_qp_num(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) down_read(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) ret = qm->qp_num - qm->qp_in_used;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) up_read(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) EXPORT_SYMBOL_GPL(hisi_qm_get_free_qp_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) static void hisi_qp_memory_uninit(struct hisi_qm *qm, int num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) struct qm_dma *qdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) for (i = num - 1; i >= 0; i--) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) qdma = &qm->qp_array[i].qdma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) dma_free_coherent(dev, qdma->size, qdma->va, qdma->dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) kfree(qm->qp_array);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) static int hisi_qp_memory_init(struct hisi_qm *qm, size_t dma_size, int id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) size_t off = qm->sqe_size * QM_Q_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) struct hisi_qp *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) qp = &qm->qp_array[id];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) qp->qdma.va = dma_alloc_coherent(dev, dma_size, &qp->qdma.dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) if (!qp->qdma.va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) qp->sqe = qp->qdma.va;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) qp->sqe_dma = qp->qdma.dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) qp->cqe = qp->qdma.va + off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) qp->cqe_dma = qp->qdma.dma + off;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) qp->qdma.size = dma_size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) qp->qm = qm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) qp->qp_id = id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) static int hisi_qm_memory_init(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) size_t qp_dma_size, off = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) int i, ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) #define QM_INIT_BUF(qm, type, num) do { \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) (qm)->type = ((qm)->qdma.va + (off)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) (qm)->type##_dma = (qm)->qdma.dma + (off); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) off += QMC_ALIGN(sizeof(struct qm_##type) * (num)); \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) } while (0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) idr_init(&qm->qp_idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) qm->qdma.size = QMC_ALIGN(sizeof(struct qm_eqe) * QM_EQ_DEPTH) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) QMC_ALIGN(sizeof(struct qm_aeqe) * QM_Q_DEPTH) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) QMC_ALIGN(sizeof(struct qm_sqc) * qm->qp_num) +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) QMC_ALIGN(sizeof(struct qm_cqc) * qm->qp_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) qm->qdma.va = dma_alloc_coherent(dev, qm->qdma.size, &qm->qdma.dma,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) dev_dbg(dev, "allocate qm dma buf size=%zx)\n", qm->qdma.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) if (!qm->qdma.va)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) QM_INIT_BUF(qm, eqe, QM_EQ_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) QM_INIT_BUF(qm, aeqe, QM_Q_DEPTH);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) QM_INIT_BUF(qm, sqc, qm->qp_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) QM_INIT_BUF(qm, cqc, qm->qp_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377) qm->qp_array = kcalloc(qm->qp_num, sizeof(struct hisi_qp), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) if (!qm->qp_array) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) ret = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380) goto err_alloc_qp_array;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383) /* one more page for device or qp statuses */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) qp_dma_size = qm->sqe_size * QM_Q_DEPTH +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) sizeof(struct qm_cqe) * QM_Q_DEPTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) qp_dma_size = PAGE_ALIGN(qp_dma_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) for (i = 0; i < qm->qp_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388) ret = hisi_qp_memory_init(qm, qp_dma_size, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) goto err_init_qp_mem;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392) dev_dbg(dev, "allocate qp dma buf size=%zx)\n", qp_dma_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) err_init_qp_mem:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) hisi_qp_memory_uninit(qm, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399) err_alloc_qp_array:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) dma_free_coherent(dev, qm->qdma.size, qm->qdma.va, qm->qdma.dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) static void hisi_qm_pre_init(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) if (qm->ver == QM_HW_V1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410) qm->ops = &qm_hw_ops_v1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) qm->ops = &qm_hw_ops_v2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) pci_set_drvdata(pdev, qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) mutex_init(&qm->mailbox_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416) init_rwsem(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) qm->qp_in_used = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) qm->is_frozen = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) * hisi_qm_uninit() - Uninitialize qm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423) * @qm: The qm needed uninit.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) * This function uninits qm related device resources.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) void hisi_qm_uninit(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) down_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434) if (!qm_avail_state(qm, QM_CLOSE)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) uacce_remove(qm->uacce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440) qm->uacce = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442) hisi_qp_memory_uninit(qm, qm->qp_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) idr_destroy(&qm->qp_idr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) if (qm->qdma.va) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) hisi_qm_cache_wb(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447) dma_free_coherent(dev, qm->qdma.size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) qm->qdma.va, qm->qdma.dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) memset(&qm->qdma, 0, sizeof(qm->qdma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) qm_irq_unregister(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) iounmap(qm->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) pci_release_mem_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) EXPORT_SYMBOL_GPL(hisi_qm_uninit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463) * hisi_qm_get_vft() - Get vft from a qm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) * @qm: The qm we want to get its vft.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) * @base: The base number of queue in vft.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) * @number: The number of queues in vft.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) * We can allocate multiple queues to a qm by configuring virtual function
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469) * table. We get related configures by this function. Normally, we call this
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) * function in VF driver to get the queue information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) * qm hw v1 does not support this interface.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474) int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) if (!base || !number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) if (!qm->ops->get_vft) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) dev_err(&qm->pdev->dev, "Don't support vft read!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) return qm->ops->get_vft(qm, base, number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) EXPORT_SYMBOL_GPL(hisi_qm_get_vft);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) * This function is alway called in PF driver, it is used to assign queues
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) * among PF and VFs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) * Assign queues A~B to PF: hisi_qm_set_vft(qm, 0, A, B - A + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493) * Assign queues A~B to VF: hisi_qm_set_vft(qm, 2, A, B - A + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) * (VF function number 0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) static int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) u32 number)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) u32 max_q_num = qm->ctrl_qp_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) if (base >= max_q_num || number > max_q_num ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502) (base + number) > max_q_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505) return qm_set_sqc_cqc_vft(qm, fun_num, base, number);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508) static void qm_init_eq_aeq_status(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) struct hisi_qm_status *status = &qm->status;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) status->eq_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) status->aeq_head = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) status->eqc_phase = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) status->aeqc_phase = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518) static int qm_eq_ctx_cfg(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) struct qm_eqc *eqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) struct qm_aeqc *aeqc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) dma_addr_t eqc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) dma_addr_t aeqc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527) qm_init_eq_aeq_status(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) eqc = kzalloc(sizeof(struct qm_eqc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530) if (!eqc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) eqc_dma = dma_map_single(dev, eqc, sizeof(struct qm_eqc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) if (dma_mapping_error(dev, eqc_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535) kfree(eqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539) eqc->base_l = cpu_to_le32(lower_32_bits(qm->eqe_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) eqc->base_h = cpu_to_le32(upper_32_bits(qm->eqe_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) if (qm->ver == QM_HW_V1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) eqc->dw3 = cpu_to_le32(QM_EQE_AEQE_SIZE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) eqc->dw6 = cpu_to_le32((QM_EQ_DEPTH - 1) | (1 << QM_EQC_PHASE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) ret = qm_mb(qm, QM_MB_CMD_EQC, eqc_dma, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) dma_unmap_single(dev, eqc_dma, sizeof(struct qm_eqc), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) kfree(eqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) aeqc = kzalloc(sizeof(struct qm_aeqc), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551) if (!aeqc)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) aeqc_dma = dma_map_single(dev, aeqc, sizeof(struct qm_aeqc),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555) if (dma_mapping_error(dev, aeqc_dma)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) kfree(aeqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) aeqc->base_l = cpu_to_le32(lower_32_bits(qm->aeqe_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) aeqc->base_h = cpu_to_le32(upper_32_bits(qm->aeqe_dma));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562) aeqc->dw6 = cpu_to_le32((QM_Q_DEPTH - 1) | (1 << QM_EQC_PHASE_SHIFT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) ret = qm_mb(qm, QM_MB_CMD_AEQC, aeqc_dma, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) dma_unmap_single(dev, aeqc_dma, sizeof(struct qm_aeqc), DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566) kfree(aeqc);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) static int __hisi_qm_start(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) WARN_ON(!qm->qdma.dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) if (qm->fun_type == QM_HW_PF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) ret = qm_dev_mem_reset(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) ret = hisi_qm_set_vft(qm, 0, qm->qp_base, qm->qp_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) ret = qm_eq_ctx_cfg(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) ret = qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595) ret = qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600) writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) * hisi_qm_start() - start qm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) * @qm: The qm to be started.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) * This function starts a qm, then we can allocate qp from this qm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) int hisi_qm_start(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) down_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) if (!qm_avail_state(qm, QM_START)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) dev_dbg(dev, "qm start with %d queue pairs\n", qm->qp_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) if (!qm->qp_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) dev_err(dev, "qp_num should not be 0\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) ret = -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) ret = __hisi_qm_start(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) if (!ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) atomic_set(&qm->status.flags, QM_START);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) EXPORT_SYMBOL_GPL(hisi_qm_start);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) static int qm_restart(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) struct hisi_qp *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) int ret, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647) ret = hisi_qm_start(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) down_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) for (i = 0; i < qm->qp_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653) qp = &qm->qp_array[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) if (atomic_read(&qp->qp_status.flags) == QP_STOP &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) qp->is_resetting == true) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) ret = qm_start_qp_nolock(qp, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) dev_err(dev, "Failed to start qp%d!\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) qp->is_resetting = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) /* Stop started qps in reset flow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) static int qm_stop_started_qp(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) struct hisi_qp *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) for (i = 0; i < qm->qp_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) qp = &qm->qp_array[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680) if (qp && atomic_read(&qp->qp_status.flags) == QP_START) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) qp->is_resetting = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) ret = qm_stop_qp_nolock(qp);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684) dev_err(dev, "Failed to stop qp%d!\n", i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) * This function clears all queues memory in a qm. Reset of accelerator can
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2695) * use this to clear queues.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2696) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2697) static void qm_clear_queues(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2698) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2699) struct hisi_qp *qp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2700) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2701)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2702) for (i = 0; i < qm->qp_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2703) qp = &qm->qp_array[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2704) if (qp->is_resetting)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2705) memset(qp->qdma.va, 0, qp->qdma.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2708) memset(qm->qdma.va, 0, qm->qdma.size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2711) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2712) * hisi_qm_stop() - Stop a qm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2713) * @qm: The qm which will be stopped.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2714) * @r: The reason to stop qm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2715) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2716) * This function stops qm and its qps, then qm can not accept request.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2717) * Related resources are not released at this state, we can use hisi_qm_start
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2718) * to let qm start again.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2719) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2720) int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2721) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2722) struct device *dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2723) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2724)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2725) down_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2727) qm->status.stop_reason = r;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2728) if (!qm_avail_state(qm, QM_STOP)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2729) ret = -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2730) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2731) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2733) if (qm->status.stop_reason == QM_SOFT_RESET ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2734) qm->status.stop_reason == QM_FLR) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2735) ret = qm_stop_started_qp(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2736) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2737) dev_err(dev, "Failed to stop started qp!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2738) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2739) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2742) /* Mask eq and aeq irq */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2743) writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2744) writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2746) if (qm->fun_type == QM_HW_PF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2747) ret = hisi_qm_set_vft(qm, 0, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2748) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2749) dev_err(dev, "Failed to set vft!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2750) ret = -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2751) goto err_unlock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2752) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2753) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2755) qm_clear_queues(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2756) atomic_set(&qm->status.flags, QM_STOP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2758) err_unlock:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2759) up_write(&qm->qps_lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2760) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2761) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2762) EXPORT_SYMBOL_GPL(hisi_qm_stop);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2763)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2764) static ssize_t qm_status_read(struct file *filp, char __user *buffer,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2765) size_t count, loff_t *pos)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2767) struct hisi_qm *qm = filp->private_data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2768) char buf[QM_DBG_READ_LEN];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2769) int val, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2771) val = atomic_read(&qm->status.flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2772) len = scnprintf(buf, QM_DBG_READ_LEN, "%s\n", qm_s[val]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2774) return simple_read_from_buffer(buffer, count, pos, buf, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2777) static const struct file_operations qm_status_fops = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2778) .owner = THIS_MODULE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2779) .open = simple_open,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2780) .read = qm_status_read,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2781) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2782)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2783) static int qm_debugfs_atomic64_set(void *data, u64 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2784) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2785) if (val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2786) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2787)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2788) atomic64_set((atomic64_t *)data, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2790) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2791) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2792)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2793) static int qm_debugfs_atomic64_get(void *data, u64 *val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2794) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2795) *val = atomic64_read((atomic64_t *)data);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2796)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2797) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2798) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2799)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2800) DEFINE_DEBUGFS_ATTRIBUTE(qm_atomic64_ops, qm_debugfs_atomic64_get,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2801) qm_debugfs_atomic64_set, "%llu\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2803) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2804) * hisi_qm_debug_init() - Initialize qm related debugfs files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2805) * @qm: The qm for which we want to add debugfs files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2806) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2807) * Create qm related debugfs files.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2808) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2809) int hisi_qm_debug_init(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2810) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2811) struct qm_dfx *dfx = &qm->debug.dfx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2812) struct dentry *qm_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2813) void *data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2814) int i, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2815)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2816) qm_d = debugfs_create_dir("qm", qm->debug.debug_root);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2817) qm->debug.qm_d = qm_d;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2818)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2819) /* only show this in PF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2820) if (qm->fun_type == QM_HW_PF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2821) for (i = CURRENT_Q; i < DEBUG_FILE_NUM; i++)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2822) if (qm_create_debugfs_file(qm, i)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2823) ret = -ENOENT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2824) goto failed_to_create;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2825) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2827) debugfs_create_file("regs", 0444, qm->debug.qm_d, qm, &qm_regs_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2829) debugfs_create_file("cmd", 0444, qm->debug.qm_d, qm, &qm_cmd_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2831) debugfs_create_file("status", 0444, qm->debug.qm_d, qm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2832) &qm_status_fops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2833) for (i = 0; i < ARRAY_SIZE(qm_dfx_files); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2834) data = (atomic64_t *)((uintptr_t)dfx + qm_dfx_files[i].offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2835) debugfs_create_file(qm_dfx_files[i].name,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2836) 0644,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2837) qm_d,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2838) data,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2839) &qm_atomic64_ops);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2840) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2841)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2842) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2844) failed_to_create:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2845) debugfs_remove_recursive(qm_d);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2846) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2848) EXPORT_SYMBOL_GPL(hisi_qm_debug_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2849)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2850) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2851) * hisi_qm_debug_regs_clear() - clear qm debug related registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2852) * @qm: The qm for which we want to clear its debug registers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2853) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2854) void hisi_qm_debug_regs_clear(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2855) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2856) struct qm_dfx_registers *regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2857) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2858)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2859) /* clear current_q */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2860) writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2861) writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2863) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2864) * these registers are reading and clearing, so clear them after
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2865) * reading them.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2866) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2867) writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2868)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2869) regs = qm_dfx_regs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2870) for (i = 0; i < CNT_CYC_REGS_NUM; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2871) readl(qm->io_base + regs->reg_offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2872) regs++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2873) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2875) writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2876) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2877) EXPORT_SYMBOL_GPL(hisi_qm_debug_regs_clear);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2879) static void qm_hw_error_init(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2881) const struct hisi_qm_err_info *err_info = &qm->err_ini->err_info;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2882)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2883) if (!qm->ops->hw_error_init) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2884) dev_err(&qm->pdev->dev, "QM doesn't support hw error handling!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2885) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2888) qm->ops->hw_error_init(qm, err_info->ce, err_info->nfe, err_info->fe);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2889) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2890)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2891) static void qm_hw_error_uninit(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2892) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2893) if (!qm->ops->hw_error_uninit) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2894) dev_err(&qm->pdev->dev, "Unexpected QM hw error uninit!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2895) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2896) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2897)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2898) qm->ops->hw_error_uninit(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2901) static enum acc_err_result qm_hw_error_handle(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2902) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2903) if (!qm->ops->hw_error_handle) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2904) dev_err(&qm->pdev->dev, "QM doesn't support hw error report!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2905) return ACC_ERR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2908) return qm->ops->hw_error_handle(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2909) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2910)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2911) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2912) * hisi_qm_dev_err_init() - Initialize device error configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2913) * @qm: The qm for which we want to do error initialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2914) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2915) * Initialize QM and device error related configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2916) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2917) void hisi_qm_dev_err_init(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2918) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2919) if (qm->fun_type == QM_HW_VF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2920) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2921)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2922) qm_hw_error_init(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2923)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2924) if (!qm->err_ini->hw_err_enable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2925) dev_err(&qm->pdev->dev, "Device doesn't support hw error init!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2926) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2928) qm->err_ini->hw_err_enable(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2929) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2930) EXPORT_SYMBOL_GPL(hisi_qm_dev_err_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2931)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2932) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2933) * hisi_qm_dev_err_uninit() - Uninitialize device error configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2934) * @qm: The qm for which we want to do error uninitialization.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2935) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2936) * Uninitialize QM and device error related configuration.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2937) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2938) void hisi_qm_dev_err_uninit(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2939) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2940) if (qm->fun_type == QM_HW_VF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2941) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2943) qm_hw_error_uninit(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2944)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2945) if (!qm->err_ini->hw_err_disable) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2946) dev_err(&qm->pdev->dev, "Unexpected device hw error uninit!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2947) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2948) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2949) qm->err_ini->hw_err_disable(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2950) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2951) EXPORT_SYMBOL_GPL(hisi_qm_dev_err_uninit);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2953) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2954) * hisi_qm_free_qps() - free multiple queue pairs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2955) * @qps: The queue pairs need to be freed.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2956) * @qp_num: The num of queue pairs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2957) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2958) void hisi_qm_free_qps(struct hisi_qp **qps, int qp_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2959) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2960) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2962) if (!qps || qp_num <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2963) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2964)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2965) for (i = qp_num - 1; i >= 0; i--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2966) hisi_qm_release_qp(qps[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2967) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2968) EXPORT_SYMBOL_GPL(hisi_qm_free_qps);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2969)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2970) static void free_list(struct list_head *head)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2971) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2972) struct hisi_qm_resource *res, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2974) list_for_each_entry_safe(res, tmp, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2975) list_del(&res->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2976) kfree(res);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2977) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2980) static int hisi_qm_sort_devices(int node, struct list_head *head,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2981) struct hisi_qm_list *qm_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2982) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2983) struct hisi_qm_resource *res, *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2984) struct hisi_qm *qm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2985) struct list_head *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2986) struct device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2987) int dev_node = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2989) list_for_each_entry(qm, &qm_list->list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2990) dev = &qm->pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2992) if (IS_ENABLED(CONFIG_NUMA)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2993) dev_node = dev_to_node(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2994) if (dev_node < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2995) dev_node = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2996) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2997)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2998) res = kzalloc(sizeof(*res), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2999) if (!res)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3000) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3001)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3002) res->qm = qm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3003) res->distance = node_distance(dev_node, node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3004) n = head;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3005) list_for_each_entry(tmp, head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3006) if (res->distance < tmp->distance) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3007) n = &tmp->list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3008) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3009) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3010) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3011) list_add_tail(&res->list, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3012) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3014) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3015) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3016)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3017) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3018) * hisi_qm_alloc_qps_node() - Create multiple queue pairs.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3019) * @qm_list: The list of all available devices.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3020) * @qp_num: The number of queue pairs need created.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3021) * @alg_type: The algorithm type.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3022) * @node: The numa node.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3023) * @qps: The queue pairs need created.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3024) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3025) * This function will sort all available device according to numa distance.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3026) * Then try to create all queue pairs from one device, if all devices do
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3027) * not meet the requirements will return error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3028) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3029) int hisi_qm_alloc_qps_node(struct hisi_qm_list *qm_list, int qp_num,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3030) u8 alg_type, int node, struct hisi_qp **qps)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3031) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3032) struct hisi_qm_resource *tmp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3033) int ret = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3034) LIST_HEAD(head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3035) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3037) if (!qps || !qm_list || qp_num <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3038) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3040) mutex_lock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3041) if (hisi_qm_sort_devices(node, &head, qm_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3042) mutex_unlock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3043) goto err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3044) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3045)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3046) list_for_each_entry(tmp, &head, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3047) for (i = 0; i < qp_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3048) qps[i] = hisi_qm_create_qp(tmp->qm, alg_type);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3049) if (IS_ERR(qps[i])) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3050) hisi_qm_free_qps(qps, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3051) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3052) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3053) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3055) if (i == qp_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3056) ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3057) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3058) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3061) mutex_unlock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3062) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3063) pr_info("Failed to create qps, node[%d], alg[%d], qp[%d]!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3064) node, alg_type, qp_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3066) err:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3067) free_list(&head);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3068) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3070) EXPORT_SYMBOL_GPL(hisi_qm_alloc_qps_node);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3071)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3072) static int qm_vf_q_assign(struct hisi_qm *qm, u32 num_vfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3073) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3074) u32 remain_q_num, q_num, i, j;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3075) u32 q_base = qm->qp_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3076) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3077)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3078) if (!num_vfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3079) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3080)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3081) remain_q_num = qm->ctrl_qp_num - qm->qp_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3083) /* If remain queues not enough, return error. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3084) if (qm->ctrl_qp_num < qm->qp_num || remain_q_num < num_vfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3085) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3086)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3087) q_num = remain_q_num / num_vfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3088) for (i = 1; i <= num_vfs; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3089) if (i == num_vfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3090) q_num += remain_q_num % num_vfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3091) ret = hisi_qm_set_vft(qm, i, q_base, q_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3092) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3093) for (j = i; j > 0; j--)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3094) hisi_qm_set_vft(qm, j, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3095) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3097) q_base += q_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3099)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3100) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3103) static int qm_clear_vft_config(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3104) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3105) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3106) u32 i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3107)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3108) for (i = 1; i <= qm->vfs_num; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3109) ret = hisi_qm_set_vft(qm, i, 0, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3110) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3111) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3112) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3113) qm->vfs_num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3115) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3116) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3118) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3119) * hisi_qm_sriov_enable() - enable virtual functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3120) * @pdev: the PCIe device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3121) * @max_vfs: the number of virtual functions to enable
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3122) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3123) * Returns the number of enabled VFs. If there are VFs enabled already or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3124) * max_vfs is more than the total number of device can be enabled, returns
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3125) * failure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3126) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3127) int hisi_qm_sriov_enable(struct pci_dev *pdev, int max_vfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3129) struct hisi_qm *qm = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3130) int pre_existing_vfs, num_vfs, total_vfs, ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3131)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3132) total_vfs = pci_sriov_get_totalvfs(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3133) pre_existing_vfs = pci_num_vf(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3134) if (pre_existing_vfs) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3135) pci_err(pdev, "%d VFs already enabled. Please disable pre-enabled VFs!\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3136) pre_existing_vfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3137) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3138) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3139)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3140) num_vfs = min_t(int, max_vfs, total_vfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3141) ret = qm_vf_q_assign(qm, num_vfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3142) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3143) pci_err(pdev, "Can't assign queues for VF!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3144) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3145) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3146)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3147) qm->vfs_num = num_vfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3148)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3149) ret = pci_enable_sriov(pdev, num_vfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3150) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3151) pci_err(pdev, "Can't enable VF!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3152) qm_clear_vft_config(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3153) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3154) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3155)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3156) pci_info(pdev, "VF enabled, vfs_num(=%d)!\n", num_vfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3158) return num_vfs;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3159) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3160) EXPORT_SYMBOL_GPL(hisi_qm_sriov_enable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3162) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3163) * hisi_qm_sriov_disable - disable virtual functions
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3164) * @pdev: the PCI device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3165) * @is_frozen: true when all the VFs are frozen.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3166) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3167) * Return failure if there are VFs assigned already or VF is in used.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3168) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3169) int hisi_qm_sriov_disable(struct pci_dev *pdev, bool is_frozen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3170) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3171) struct hisi_qm *qm = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3172)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3173) if (pci_vfs_assigned(pdev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3174) pci_err(pdev, "Failed to disable VFs as VFs are assigned!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3175) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3176) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3178) /* While VF is in used, SRIOV cannot be disabled. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3179) if (!is_frozen && qm_try_frozen_vfs(pdev, qm->qm_list)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3180) pci_err(pdev, "Task is using its VF!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3181) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3182) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3183)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3184) pci_disable_sriov(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3185) return qm_clear_vft_config(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3186) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3187) EXPORT_SYMBOL_GPL(hisi_qm_sriov_disable);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3188)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3189) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3190) * hisi_qm_sriov_configure - configure the number of VFs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3191) * @pdev: The PCI device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3192) * @num_vfs: The number of VFs need enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3193) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3194) * Enable SR-IOV according to num_vfs, 0 means disable.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3195) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3196) int hisi_qm_sriov_configure(struct pci_dev *pdev, int num_vfs)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3197) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3198) if (num_vfs == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3199) return hisi_qm_sriov_disable(pdev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3200) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3201) return hisi_qm_sriov_enable(pdev, num_vfs);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3202) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3203) EXPORT_SYMBOL_GPL(hisi_qm_sriov_configure);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3205) static enum acc_err_result qm_dev_err_handle(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3206) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3207) u32 err_sts;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3208)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3209) if (!qm->err_ini->get_dev_hw_err_status) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3210) dev_err(&qm->pdev->dev, "Device doesn't support get hw error status!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3211) return ACC_ERR_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3212) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3213)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3214) /* get device hardware error status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3215) err_sts = qm->err_ini->get_dev_hw_err_status(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3216) if (err_sts) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3217) if (err_sts & qm->err_ini->err_info.ecc_2bits_mask)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3218) qm->err_status.is_dev_ecc_mbit = true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3219)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3220) if (!qm->err_ini->log_dev_hw_err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3221) dev_err(&qm->pdev->dev, "Device doesn't support log hw error!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3222) return ACC_ERR_NEED_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3223) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3225) qm->err_ini->log_dev_hw_err(qm, err_sts);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3226) return ACC_ERR_NEED_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3227) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3228)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3229) return ACC_ERR_RECOVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3230) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3231)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3232) static enum acc_err_result qm_process_dev_error(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3234) enum acc_err_result qm_ret, dev_ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3236) /* log qm error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3237) qm_ret = qm_hw_error_handle(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3238)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3239) /* log device error */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3240) dev_ret = qm_dev_err_handle(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3241)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3242) return (qm_ret == ACC_ERR_NEED_RESET ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3243) dev_ret == ACC_ERR_NEED_RESET) ?
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3244) ACC_ERR_NEED_RESET : ACC_ERR_RECOVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3245) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3247) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3248) * hisi_qm_dev_err_detected() - Get device and qm error status then log it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3249) * @pdev: The PCI device which need report error.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3250) * @state: The connectivity between CPU and device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3251) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3252) * We register this function into PCIe AER handlers, It will report device or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3253) * qm hardware error status when error occur.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3254) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3255) pci_ers_result_t hisi_qm_dev_err_detected(struct pci_dev *pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3256) pci_channel_state_t state)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3257) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3258) struct hisi_qm *qm = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3259) enum acc_err_result ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3261) if (pdev->is_virtfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3262) return PCI_ERS_RESULT_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3264) pci_info(pdev, "PCI error detected, state(=%d)!!\n", state);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3265) if (state == pci_channel_io_perm_failure)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3266) return PCI_ERS_RESULT_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3267)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3268) ret = qm_process_dev_error(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3269) if (ret == ACC_ERR_NEED_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3270) return PCI_ERS_RESULT_NEED_RESET;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3271)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3272) return PCI_ERS_RESULT_RECOVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3273) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3274) EXPORT_SYMBOL_GPL(hisi_qm_dev_err_detected);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3276) static int qm_get_hw_error_status(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3277) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3278) return readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3279) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3281) static int qm_check_req_recv(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3282) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3283) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3284) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3285) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3286)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3287) writel(ACC_VENDOR_ID_VALUE, qm->io_base + QM_PEH_VENDOR_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3288) ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3289) (val == ACC_VENDOR_ID_VALUE),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3290) POLL_PERIOD, POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3291) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3292) dev_err(&pdev->dev, "Fails to read QM reg!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3293) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3294) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3295)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3296) writel(PCI_VENDOR_ID_HUAWEI, qm->io_base + QM_PEH_VENDOR_ID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3297) ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3298) (val == PCI_VENDOR_ID_HUAWEI),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3299) POLL_PERIOD, POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3300) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3301) dev_err(&pdev->dev, "Fails to read QM reg in the second time!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3302)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3303) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3304) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3306) static int qm_set_pf_mse(struct hisi_qm *qm, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3307) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3308) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3309) u16 cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3310) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3311)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3312) pci_read_config_word(pdev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3313) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3314) cmd |= PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3315) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3316) cmd &= ~PCI_COMMAND_MEMORY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3317)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3318) pci_write_config_word(pdev, PCI_COMMAND, cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3319) for (i = 0; i < MAX_WAIT_COUNTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3320) pci_read_config_word(pdev, PCI_COMMAND, &cmd);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3321) if (set == ((cmd & PCI_COMMAND_MEMORY) >> 1))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3322) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3323)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3324) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3325) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3326)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3327) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3328) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3330) static int qm_set_vf_mse(struct hisi_qm *qm, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3331) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3332) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3333) u16 sriov_ctrl;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3334) int pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3335) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3336)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3337) pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_SRIOV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3338) pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &sriov_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3339) if (set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3340) sriov_ctrl |= PCI_SRIOV_CTRL_MSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3341) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3342) sriov_ctrl &= ~PCI_SRIOV_CTRL_MSE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3343) pci_write_config_word(pdev, pos + PCI_SRIOV_CTRL, sriov_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3344)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3345) for (i = 0; i < MAX_WAIT_COUNTS; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3346) pci_read_config_word(pdev, pos + PCI_SRIOV_CTRL, &sriov_ctrl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3347) if (set == (sriov_ctrl & PCI_SRIOV_CTRL_MSE) >>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3348) ACC_PEH_SRIOV_CTRL_VF_MSE_SHIFT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3349) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3350)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3351) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3352) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3353)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3354) return -ETIMEDOUT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3357) static int qm_set_msi(struct hisi_qm *qm, bool set)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3358) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3359) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3361) if (set) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3362) pci_write_config_dword(pdev, pdev->msi_cap + PCI_MSI_MASK_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3363) 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3364) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3365) pci_write_config_dword(pdev, pdev->msi_cap + PCI_MSI_MASK_64,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3366) ACC_PEH_MSI_DISABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3367) if (qm->err_status.is_qm_ecc_mbit ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3368) qm->err_status.is_dev_ecc_mbit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3369) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3370)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3371) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3372) if (readl(qm->io_base + QM_PEH_DFX_INFO0))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3373) return -EFAULT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3374) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3375)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3376) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3377) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3378)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3379) static int qm_vf_reset_prepare(struct hisi_qm *qm,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3380) enum qm_stop_reason stop_reason)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3381) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3382) struct hisi_qm_list *qm_list = qm->qm_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3383) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3384) struct pci_dev *virtfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3385) struct hisi_qm *vf_qm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3386) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3388) mutex_lock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3389) list_for_each_entry(vf_qm, &qm_list->list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3390) virtfn = vf_qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3391) if (virtfn == pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3392) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3393)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3394) if (pci_physfn(virtfn) == pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3395) /* save VFs PCIE BAR configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3396) pci_save_state(virtfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3398) ret = hisi_qm_stop(vf_qm, stop_reason);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3399) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3400) goto stop_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3401) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3402) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3404) stop_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3405) mutex_unlock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3406) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3407) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3409) static int qm_reset_prepare_ready(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3410) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3411) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3412) struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3413) int delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3415) /* All reset requests need to be queued for processing */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3416) while (test_and_set_bit(QM_DEV_RESET_FLAG, &pf_qm->reset_flag)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3417) msleep(++delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3418) if (delay > QM_RESET_WAIT_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3419) return -EBUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3420) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3422) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3423) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3424)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3425) static int qm_controller_reset_prepare(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3426) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3427) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3428) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3429)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3430) ret = qm_reset_prepare_ready(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3431) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3432) pci_err(pdev, "Controller reset not ready!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3433) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3434) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3436) if (qm->vfs_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3437) ret = qm_vf_reset_prepare(qm, QM_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3438) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3439) pci_err(pdev, "Fails to stop VFs!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3440) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3441) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3442) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3443)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3444) ret = hisi_qm_stop(qm, QM_SOFT_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3445) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3446) pci_err(pdev, "Fails to stop QM!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3447) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3448) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3449)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3450) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3451) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3452)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3453) static void qm_dev_ecc_mbit_handle(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3454) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3455) u32 nfe_enb = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3457) if (!qm->err_status.is_dev_ecc_mbit &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3458) qm->err_status.is_qm_ecc_mbit &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3459) qm->err_ini->close_axi_master_ooo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3460)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3461) qm->err_ini->close_axi_master_ooo(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3463) } else if (qm->err_status.is_dev_ecc_mbit &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3464) !qm->err_status.is_qm_ecc_mbit &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3465) !qm->err_ini->close_axi_master_ooo) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3466)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3467) nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3468) writel(nfe_enb & QM_RAS_NFE_MBIT_DISABLE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3469) qm->io_base + QM_RAS_NFE_ENABLE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3470) writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3471) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3472) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3474) static int qm_soft_reset(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3475) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3476) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3477) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3478) u32 val;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3479)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3480) /* Ensure all doorbells and mailboxes received by QM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3481) ret = qm_check_req_recv(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3482) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3483) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3484)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3485) if (qm->vfs_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3486) ret = qm_set_vf_mse(qm, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3487) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3488) pci_err(pdev, "Fails to disable vf MSE bit.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3489) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3490) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3491) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3492)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3493) ret = qm_set_msi(qm, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3494) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3495) pci_err(pdev, "Fails to disable PEH MSI bit.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3496) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3497) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3498)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3499) qm_dev_ecc_mbit_handle(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3501) /* OOO register set and check */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3502) writel(ACC_MASTER_GLOBAL_CTRL_SHUTDOWN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3503) qm->io_base + ACC_MASTER_GLOBAL_CTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3505) /* If bus lock, reset chip */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3506) ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3507) val,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3508) (val == ACC_MASTER_TRANS_RETURN_RW),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3509) POLL_PERIOD, POLL_TIMEOUT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3510) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3511) pci_emerg(pdev, "Bus lock! Please reset system.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3512) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3513) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3514)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3515) ret = qm_set_pf_mse(qm, false);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3516) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3517) pci_err(pdev, "Fails to disable pf MSE bit.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3518) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3521) /* The reset related sub-control registers are not in PCI BAR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3522) if (ACPI_HANDLE(&pdev->dev)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3523) unsigned long long value = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3524) acpi_status s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3525)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3526) s = acpi_evaluate_integer(ACPI_HANDLE(&pdev->dev),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3527) qm->err_ini->err_info.acpi_rst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3528) NULL, &value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3529) if (ACPI_FAILURE(s)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3530) pci_err(pdev, "NO controller reset method!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3531) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3532) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3534) if (value) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3535) pci_err(pdev, "Reset step %llu failed!\n", value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3536) return -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3537) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3538) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3539) pci_err(pdev, "No reset method!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3540) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3541) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3543) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3544) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3545)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3546) static int qm_vf_reset_done(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3547) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3548) struct hisi_qm_list *qm_list = qm->qm_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3549) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3550) struct pci_dev *virtfn;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3551) struct hisi_qm *vf_qm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3552) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3554) mutex_lock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3555) list_for_each_entry(vf_qm, &qm_list->list, list) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3556) virtfn = vf_qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3557) if (virtfn == pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3558) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3560) if (pci_physfn(virtfn) == pdev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3561) /* enable VFs PCIE BAR configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3562) pci_restore_state(virtfn);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3563)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3564) ret = qm_restart(vf_qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3565) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3566) goto restart_fail;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3568) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3569)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3570) restart_fail:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3571) mutex_unlock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3572) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3573) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3575) static int qm_get_dev_err_status(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3576) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3577) return qm->err_ini->get_dev_hw_err_status(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3578) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3580) static int qm_dev_hw_init(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3581) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3582) return qm->err_ini->hw_init(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3583) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3585) static void qm_restart_prepare(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3586) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3587) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3588)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3589) if (!qm->err_status.is_qm_ecc_mbit &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3590) !qm->err_status.is_dev_ecc_mbit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3591) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3593) /* temporarily close the OOO port used for PEH to write out MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3594) value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3595) writel(value & ~qm->err_ini->err_info.msi_wr_port,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3596) qm->io_base + ACC_AM_CFG_PORT_WR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3598) /* clear dev ecc 2bit error source if having */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3599) value = qm_get_dev_err_status(qm) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3600) qm->err_ini->err_info.ecc_2bits_mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3601) if (value && qm->err_ini->clear_dev_hw_err_status)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3602) qm->err_ini->clear_dev_hw_err_status(qm, value);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3604) /* clear QM ecc mbit error source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3605) writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SOURCE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3607) /* clear AM Reorder Buffer ecc mbit source */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3608) writel(ACC_ROB_ECC_ERR_MULTPL, qm->io_base + ACC_AM_ROB_ECC_INT_STS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3609)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3610) if (qm->err_ini->open_axi_master_ooo)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3611) qm->err_ini->open_axi_master_ooo(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3612) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3614) static void qm_restart_done(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3615) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3616) u32 value;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3617)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3618) if (!qm->err_status.is_qm_ecc_mbit &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3619) !qm->err_status.is_dev_ecc_mbit)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3620) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3622) /* open the OOO port for PEH to write out MSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3623) value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3624) value |= qm->err_ini->err_info.msi_wr_port;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3625) writel(value, qm->io_base + ACC_AM_CFG_PORT_WR_EN);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3627) qm->err_status.is_qm_ecc_mbit = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3628) qm->err_status.is_dev_ecc_mbit = false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3629) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3630)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3631) static int qm_controller_reset_done(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3632) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3633) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3634) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3636) ret = qm_set_msi(qm, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3637) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3638) pci_err(pdev, "Fails to enable PEH MSI bit!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3639) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3640) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3642) ret = qm_set_pf_mse(qm, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3643) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3644) pci_err(pdev, "Fails to enable pf MSE bit!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3645) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3646) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3648) if (qm->vfs_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3649) ret = qm_set_vf_mse(qm, true);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3650) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3651) pci_err(pdev, "Fails to enable vf MSE bit!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3652) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3653) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3654) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3656) ret = qm_dev_hw_init(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3657) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3658) pci_err(pdev, "Failed to init device\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3659) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3662) qm_restart_prepare(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3663)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3664) ret = qm_restart(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3665) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3666) pci_err(pdev, "Failed to start QM!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3667) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3668) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3670) if (qm->vfs_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3671) ret = qm_vf_q_assign(qm, qm->vfs_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3672) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3673) pci_err(pdev, "Failed to assign queue!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3674) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3675) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3676) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3678) ret = qm_vf_reset_done(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3679) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3680) pci_err(pdev, "Failed to start VFs!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3681) return -EPERM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3682) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3683)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3684) hisi_qm_dev_err_init(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3685) qm_restart_done(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3686)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3687) clear_bit(QM_DEV_RESET_FLAG, &qm->reset_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3689) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3692) static int qm_controller_reset(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3693) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3694) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3695) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3696)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3697) pci_info(pdev, "Controller resetting...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3698)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3699) ret = qm_controller_reset_prepare(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3700) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3701) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3702)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3703) ret = qm_soft_reset(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3704) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3705) pci_err(pdev, "Controller reset failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3706) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3707) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3708)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3709) ret = qm_controller_reset_done(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3710) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3711) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3712)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3713) pci_info(pdev, "Controller reset complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3715) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3716) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3717)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3718) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3719) * hisi_qm_dev_slot_reset() - slot reset
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3720) * @pdev: the PCIe device
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3721) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3722) * This function offers QM relate PCIe device reset interface. Drivers which
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3723) * use QM can use this function as slot_reset in its struct pci_error_handlers.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3724) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3725) pci_ers_result_t hisi_qm_dev_slot_reset(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3726) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3727) struct hisi_qm *qm = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3728) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3730) if (pdev->is_virtfn)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3731) return PCI_ERS_RESULT_RECOVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3732)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3733) pci_aer_clear_nonfatal_status(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3734)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3735) /* reset pcie device controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3736) ret = qm_controller_reset(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3737) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3738) pci_err(pdev, "Controller reset failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3739) return PCI_ERS_RESULT_DISCONNECT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3740) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3741)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3742) return PCI_ERS_RESULT_RECOVERED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3743) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3744) EXPORT_SYMBOL_GPL(hisi_qm_dev_slot_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3745)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3746) /* check the interrupt is ecc-mbit error or not */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3747) static int qm_check_dev_error(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3748) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3749) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3750)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3751) if (qm->fun_type == QM_HW_VF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3752) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3753)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3754) ret = qm_get_hw_error_status(qm) & QM_ECC_MBIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3755) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3756) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3757)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3758) return (qm_get_dev_err_status(qm) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3759) qm->err_ini->err_info.ecc_2bits_mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3760) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3761)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3762) void hisi_qm_reset_prepare(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3763) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3764) struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3765) struct hisi_qm *qm = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3766) u32 delay = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3767) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3769) hisi_qm_dev_err_uninit(pf_qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3770)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3771) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3772) * Check whether there is an ECC mbit error, If it occurs, need to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3773) * wait for soft reset to fix it.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3774) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3775) while (qm_check_dev_error(pf_qm)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3776) msleep(++delay);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3777) if (delay > QM_RESET_WAIT_TIMEOUT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3778) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3779) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3780)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3781) ret = qm_reset_prepare_ready(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3782) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3783) pci_err(pdev, "FLR not ready!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3784) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3785) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3787) if (qm->vfs_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3788) ret = qm_vf_reset_prepare(qm, QM_FLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3789) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3790) pci_err(pdev, "Failed to prepare reset, ret = %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3791) ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3792) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3794) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3795)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3796) ret = hisi_qm_stop(qm, QM_FLR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3797) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3798) pci_err(pdev, "Failed to stop QM, ret = %d.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3799) return;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3801)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3802) pci_info(pdev, "FLR resetting...\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3803) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3804) EXPORT_SYMBOL_GPL(hisi_qm_reset_prepare);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3806) static bool qm_flr_reset_complete(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3807) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3808) struct pci_dev *pf_pdev = pci_physfn(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3809) struct hisi_qm *qm = pci_get_drvdata(pf_pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3810) u32 id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3811)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3812) pci_read_config_dword(qm->pdev, PCI_COMMAND, &id);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3813) if (id == QM_PCI_COMMAND_INVALID) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3814) pci_err(pdev, "Device can not be used!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3815) return false;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3816) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3817)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3818) clear_bit(QM_DEV_RESET_FLAG, &qm->reset_flag);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3820) return true;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3823) void hisi_qm_reset_done(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3824) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3825) struct hisi_qm *pf_qm = pci_get_drvdata(pci_physfn(pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3826) struct hisi_qm *qm = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3827) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3829) hisi_qm_dev_err_init(pf_qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3830)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3831) ret = qm_restart(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3832) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3833) pci_err(pdev, "Failed to start QM, ret = %d.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3834) goto flr_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3837) if (qm->fun_type == QM_HW_PF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3838) ret = qm_dev_hw_init(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3839) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3840) pci_err(pdev, "Failed to init PF, ret = %d.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3841) goto flr_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3842) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3843)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3844) if (!qm->vfs_num)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3845) goto flr_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3846)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3847) ret = qm_vf_q_assign(qm, qm->vfs_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3848) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3849) pci_err(pdev, "Failed to assign VFs, ret = %d.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3850) goto flr_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3851) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3852)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3853) ret = qm_vf_reset_done(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3854) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3855) pci_err(pdev, "Failed to start VFs, ret = %d.\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3856) goto flr_done;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3857) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3858) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3859)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3860) flr_done:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3861) if (qm_flr_reset_complete(pdev))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3862) pci_info(pdev, "FLR reset complete\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3863) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3864) EXPORT_SYMBOL_GPL(hisi_qm_reset_done);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3866) static irqreturn_t qm_abnormal_irq(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3867) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3868) struct hisi_qm *qm = data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3869) enum acc_err_result ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3871) atomic64_inc(&qm->debug.dfx.abnormal_irq_cnt);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3872) ret = qm_process_dev_error(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3873) if (ret == ACC_ERR_NEED_RESET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3874) schedule_work(&qm->rst_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3875)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3876) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3877) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3878)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3879) static int qm_irq_register(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3880) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3881) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3882) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3883)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3884) ret = request_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3885) qm_irq, IRQF_SHARED, qm->dev_name, qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3886) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3887) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3888)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3889) if (qm->ver != QM_HW_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3890) ret = request_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3891) qm_aeq_irq, IRQF_SHARED, qm->dev_name, qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3892) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3893) goto err_aeq_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3894)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3895) if (qm->fun_type == QM_HW_PF) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3896) ret = request_irq(pci_irq_vector(pdev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3897) QM_ABNORMAL_EVENT_IRQ_VECTOR),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3898) qm_abnormal_irq, IRQF_SHARED,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3899) qm->dev_name, qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3900) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3901) goto err_abonormal_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3902) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3903) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3904)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3905) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3907) err_abonormal_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3908) free_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3909) err_aeq_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3910) free_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3911) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3912) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3913)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3914) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3915) * hisi_qm_dev_shutdown() - Shutdown device.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3916) * @pdev: The device will be shutdown.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3917) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3918) * This function will stop qm when OS shutdown or rebooting.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3919) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3920) void hisi_qm_dev_shutdown(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3921) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3922) struct hisi_qm *qm = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3923) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3924)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3925) ret = hisi_qm_stop(qm, QM_NORMAL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3926) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3927) dev_err(&pdev->dev, "Fail to stop qm in shutdown!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3929) EXPORT_SYMBOL_GPL(hisi_qm_dev_shutdown);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3930)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3931) static void hisi_qm_controller_reset(struct work_struct *rst_work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3932) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3933) struct hisi_qm *qm = container_of(rst_work, struct hisi_qm, rst_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3934) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3935)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3936) /* reset pcie device controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3937) ret = qm_controller_reset(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3938) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3939) dev_err(&qm->pdev->dev, "controller reset failed (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3941) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3943) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3944) * hisi_qm_alg_register() - Register alg to crypto and add qm to qm_list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3945) * @qm: The qm needs add.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3946) * @qm_list: The qm list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3947) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3948) * This function adds qm to qm list, and will register algorithm to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3949) * crypto when the qm list is empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3950) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3951) int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3952) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3953) int flag = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3954) int ret = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3956) mutex_lock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3957) if (list_empty(&qm_list->list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3958) flag = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3959) list_add_tail(&qm->list, &qm_list->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3960) mutex_unlock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3961)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3962) if (flag) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3963) ret = qm_list->register_to_crypto();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3964) if (ret) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3965) mutex_lock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3966) list_del(&qm->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3967) mutex_unlock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3968) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3969) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3970)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3971) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3972) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3973) EXPORT_SYMBOL_GPL(hisi_qm_alg_register);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3974)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3975) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3976) * hisi_qm_alg_unregister() - Unregister alg from crypto and delete qm from
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3977) * qm list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3978) * @qm: The qm needs delete.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3979) * @qm_list: The qm list.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3980) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3981) * This function deletes qm from qm list, and will unregister algorithm
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3982) * from crypto when the qm list is empty.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3983) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3984) void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3985) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3986) mutex_lock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3987) list_del(&qm->list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3988) mutex_unlock(&qm_list->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3989)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3990) if (list_empty(&qm_list->list))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3991) qm_list->unregister_from_crypto();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3992) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3993) EXPORT_SYMBOL_GPL(hisi_qm_alg_unregister);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3994)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3995) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3996) * hisi_qm_init() - Initialize configures about qm.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3997) * @qm: The qm needing init.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3998) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3999) * This function init qm, then we can call hisi_qm_start to put qm into work.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4000) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4001) int hisi_qm_init(struct hisi_qm *qm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4003) struct pci_dev *pdev = qm->pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4004) struct device *dev = &pdev->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4005) unsigned int num_vec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4006) int ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4007)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4008) hisi_qm_pre_init(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4009)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4010) ret = qm_alloc_uacce(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4011) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4012) dev_warn(&pdev->dev, "fail to alloc uacce (%d)\n", ret);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4013)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4014) ret = pci_enable_device_mem(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4015) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4016) dev_err(&pdev->dev, "Failed to enable device mem!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4017) goto err_remove_uacce;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4018) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4019)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4020) ret = pci_request_mem_regions(pdev, qm->dev_name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4021) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4022) dev_err(&pdev->dev, "Failed to request mem regions!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4023) goto err_disable_pcidev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4024) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4025)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4026) qm->phys_base = pci_resource_start(pdev, PCI_BAR_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4027) qm->phys_size = pci_resource_len(qm->pdev, PCI_BAR_2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4028) qm->io_base = ioremap(qm->phys_base, qm->phys_size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4029) if (!qm->io_base) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4030) ret = -EIO;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4031) goto err_release_mem_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4032) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4033)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4034) ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(64));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4035) if (ret < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4036) goto err_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4037) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4038)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4039) if (!qm->ops->get_irq_num) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4040) ret = -EOPNOTSUPP;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4041) goto err_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4042) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4043) num_vec = qm->ops->get_irq_num(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4044) ret = pci_alloc_irq_vectors(pdev, num_vec, num_vec, PCI_IRQ_MSI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4045) if (ret < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4046) dev_err(dev, "Failed to enable MSI vectors!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4047) goto err_iounmap;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4048) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4049)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4050) ret = qm_irq_register(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4051) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4052) goto err_free_irq_vectors;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4053)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4054) if (qm->fun_type == QM_HW_VF && qm->ver != QM_HW_V1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4055) /* v2 starts to support get vft by mailbox */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4056) ret = hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4057) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4058) goto err_irq_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4059) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4061) ret = hisi_qm_memory_init(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4062) if (ret)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4063) goto err_irq_unregister;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4064)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4065) INIT_WORK(&qm->work, qm_work_process);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4066) if (qm->fun_type == QM_HW_PF)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4067) INIT_WORK(&qm->rst_work, hisi_qm_controller_reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4069) atomic_set(&qm->status.flags, QM_INIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4071) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4072)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4073) err_irq_unregister:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4074) qm_irq_unregister(qm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4075) err_free_irq_vectors:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4076) pci_free_irq_vectors(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4077) err_iounmap:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4078) iounmap(qm->io_base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4079) err_release_mem_regions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4080) pci_release_mem_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4081) err_disable_pcidev:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4082) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4083) err_remove_uacce:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4084) uacce_remove(qm->uacce);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4085) qm->uacce = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4086) return ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4087) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4088) EXPORT_SYMBOL_GPL(hisi_qm_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4090)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4091) MODULE_LICENSE("GPL v2");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4092) MODULE_AUTHOR("Zhou Wang <wangzhou1@hisilicon.com>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4093) MODULE_DESCRIPTION("HiSilicon Accelerator queue manager driver");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags