^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: GPL-2.0-or-later
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * 2007+ Copyright (c) Evgeniy Polyakov <johnpol@2ka.mipt.ru>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #include <linux/kernel.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #include <linux/module.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include <linux/moduleparam.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #include <linux/mod_devicetable.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #include <linux/interrupt.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #include <linux/pci.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #include <linux/slab.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #include <linux/delay.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #include <linux/mm.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <linux/dma-mapping.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #include <linux/scatterlist.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #include <linux/highmem.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #include <linux/crypto.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #include <linux/hw_random.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #include <linux/ktime.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #include <crypto/algapi.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #include <crypto/internal/des.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #include <crypto/internal/skcipher.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) static char hifn_pll_ref[sizeof("extNNN")] = "ext";
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) module_param_string(hifn_pll_ref, hifn_pll_ref, sizeof(hifn_pll_ref), 0444);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) MODULE_PARM_DESC(hifn_pll_ref,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) "PLL reference clock (pci[freq] or ext[freq], default ext)");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) static atomic_t hifn_dev_number;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ACRYPTO_OP_DECRYPT 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ACRYPTO_OP_ENCRYPT 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ACRYPTO_OP_HMAC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ACRYPTO_OP_RNG 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ACRYPTO_MODE_ECB 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ACRYPTO_MODE_CBC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ACRYPTO_MODE_CFB 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ACRYPTO_MODE_OFB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ACRYPTO_TYPE_AES_128 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ACRYPTO_TYPE_AES_192 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ACRYPTO_TYPE_AES_256 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ACRYPTO_TYPE_3DES 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ACRYPTO_TYPE_DES 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCI_VENDOR_ID_HIFN 0x13A3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCI_DEVICE_ID_HIFN_7955 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCI_DEVICE_ID_HIFN_7956 0x001d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) /* I/O region sizes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HIFN_BAR0_SIZE 0x1000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HIFN_BAR1_SIZE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HIFN_BAR2_SIZE 0x8000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) /* DMA registres */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HIFN_DMA_CRA 0x0C /* DMA Command Ring Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HIFN_DMA_SDRA 0x1C /* DMA Source Data Ring Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HIFN_DMA_RRA 0x2C /* DMA Result Ring Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HIFN_DMA_DDRA 0x3C /* DMA Destination Data Ring Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define HIFN_DMA_STCTL 0x40 /* DMA Status and Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define HIFN_DMA_INTREN 0x44 /* DMA Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define HIFN_DMA_CFG1 0x48 /* DMA Configuration #1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define HIFN_DMA_CFG2 0x6C /* DMA Configuration #2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define HIFN_CHIP_ID 0x98 /* Chip ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * Processing Unit Registers (offset from BASEREG0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define HIFN_0_PUDATA 0x00 /* Processing Unit Data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HIFN_0_PUCTRL 0x04 /* Processing Unit Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define HIFN_0_PUISR 0x08 /* Processing Unit Interrupt Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define HIFN_0_PUCNFG 0x0c /* Processing Unit Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define HIFN_0_PUIER 0x10 /* Processing Unit Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define HIFN_0_PUSTAT 0x14 /* Processing Unit Status/Chip ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define HIFN_0_FIFOSTAT 0x18 /* FIFO Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define HIFN_0_FIFOCNFG 0x1c /* FIFO Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define HIFN_0_SPACESIZE 0x20 /* Register space size */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) /* Processing Unit Control Register (HIFN_0_PUCTRL) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define HIFN_PUCTRL_CLRSRCFIFO 0x0010 /* clear source fifo */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define HIFN_PUCTRL_STOP 0x0008 /* stop pu */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define HIFN_PUCTRL_LOCKRAM 0x0004 /* lock ram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define HIFN_PUCTRL_DMAENA 0x0002 /* enable dma */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define HIFN_PUCTRL_RESET 0x0001 /* Reset processing unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) /* Processing Unit Interrupt Status Register (HIFN_0_PUISR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define HIFN_PUISR_CMDINVAL 0x8000 /* Invalid command interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define HIFN_PUISR_DATAERR 0x4000 /* Data error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define HIFN_PUISR_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define HIFN_PUISR_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define HIFN_PUISR_DSTOVER 0x0200 /* Destination overrun interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define HIFN_PUISR_SRCCMD 0x0080 /* Source command interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define HIFN_PUISR_SRCCTX 0x0040 /* Source context interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define HIFN_PUISR_SRCDATA 0x0020 /* Source data interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define HIFN_PUISR_DSTDATA 0x0010 /* Destination data interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define HIFN_PUISR_DSTRESULT 0x0004 /* Destination result interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* Processing Unit Configuration Register (HIFN_0_PUCNFG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define HIFN_PUCNFG_DRAMMASK 0xe000 /* DRAM size mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define HIFN_PUCNFG_DSZ_256K 0x0000 /* 256k dram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define HIFN_PUCNFG_DSZ_512K 0x2000 /* 512k dram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define HIFN_PUCNFG_DSZ_1M 0x4000 /* 1m dram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define HIFN_PUCNFG_DSZ_2M 0x6000 /* 2m dram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HIFN_PUCNFG_DSZ_4M 0x8000 /* 4m dram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define HIFN_PUCNFG_DSZ_8M 0xa000 /* 8m dram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define HIFN_PUNCFG_DSZ_16M 0xc000 /* 16m dram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define HIFN_PUCNFG_DSZ_32M 0xe000 /* 32m dram */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define HIFN_PUCNFG_DRAMREFRESH 0x1800 /* DRAM refresh rate mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define HIFN_PUCNFG_DRFR_512 0x0000 /* 512 divisor of ECLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define HIFN_PUCNFG_DRFR_256 0x0800 /* 256 divisor of ECLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define HIFN_PUCNFG_DRFR_128 0x1000 /* 128 divisor of ECLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define HIFN_PUCNFG_TCALLPHASES 0x0200 /* your guess is as good as mine... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define HIFN_PUCNFG_TCDRVTOTEM 0x0100 /* your guess is as good as mine... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define HIFN_PUCNFG_BIGENDIAN 0x0080 /* DMA big endian mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define HIFN_PUCNFG_BUS32 0x0040 /* Bus width 32bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define HIFN_PUCNFG_BUS16 0x0000 /* Bus width 16 bits */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define HIFN_PUCNFG_CHIPID 0x0020 /* Allow chipid from PUSTAT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define HIFN_PUCNFG_DRAM 0x0010 /* Context RAM is DRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define HIFN_PUCNFG_SRAM 0x0000 /* Context RAM is SRAM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define HIFN_PUCNFG_COMPSING 0x0004 /* Enable single compression context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define HIFN_PUCNFG_ENCCNFG 0x0002 /* Encryption configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) /* Processing Unit Interrupt Enable Register (HIFN_0_PUIER) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define HIFN_PUIER_CMDINVAL 0x8000 /* Invalid command interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HIFN_PUIER_DATAERR 0x4000 /* Data error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define HIFN_PUIER_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define HIFN_PUIER_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define HIFN_PUIER_DSTOVER 0x0200 /* Destination overrun interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define HIFN_PUIER_SRCCMD 0x0080 /* Source command interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define HIFN_PUIER_SRCCTX 0x0040 /* Source context interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define HIFN_PUIER_SRCDATA 0x0020 /* Source data interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define HIFN_PUIER_DSTDATA 0x0010 /* Destination data interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HIFN_PUIER_DSTRESULT 0x0004 /* Destination result interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) /* Processing Unit Status Register/Chip ID (HIFN_0_PUSTAT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HIFN_PUSTAT_CMDINVAL 0x8000 /* Invalid command interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HIFN_PUSTAT_DATAERR 0x4000 /* Data error interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HIFN_PUSTAT_SRCFIFO 0x2000 /* Source FIFO ready interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HIFN_PUSTAT_DSTFIFO 0x1000 /* Destination FIFO ready interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HIFN_PUSTAT_DSTOVER 0x0200 /* Destination overrun interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HIFN_PUSTAT_SRCCMD 0x0080 /* Source command interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HIFN_PUSTAT_SRCCTX 0x0040 /* Source context interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HIFN_PUSTAT_SRCDATA 0x0020 /* Source data interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HIFN_PUSTAT_DSTDATA 0x0010 /* Destination data interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HIFN_PUSTAT_DSTRESULT 0x0004 /* Destination result interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HIFN_PUSTAT_CHIPREV 0x00ff /* Chip revision mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HIFN_PUSTAT_CHIPENA 0xff00 /* Chip enabled mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HIFN_PUSTAT_ENA_2 0x1100 /* Level 2 enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HIFN_PUSTAT_ENA_1 0x1000 /* Level 1 enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HIFN_PUSTAT_ENA_0 0x3000 /* Level 0 enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HIFN_PUSTAT_REV_2 0x0020 /* 7751 PT6/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HIFN_PUSTAT_REV_3 0x0030 /* 7751 PT6/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) /* FIFO Status Register (HIFN_0_FIFOSTAT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HIFN_FIFOSTAT_SRC 0x7f00 /* Source FIFO available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HIFN_FIFOSTAT_DST 0x007f /* Destination FIFO available */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* FIFO Configuration Register (HIFN_0_FIFOCNFG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define HIFN_FIFOCNFG_THRESHOLD 0x0400 /* must be written as 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) * DMA Interface Registers (offset from BASEREG1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define HIFN_1_DMA_CRAR 0x0c /* DMA Command Ring Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define HIFN_1_DMA_SRAR 0x1c /* DMA Source Ring Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define HIFN_1_DMA_RRAR 0x2c /* DMA Result Ring Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define HIFN_1_DMA_DRAR 0x3c /* DMA Destination Ring Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define HIFN_1_DMA_CSR 0x40 /* DMA Status and Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define HIFN_1_DMA_IER 0x44 /* DMA Interrupt Enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define HIFN_1_DMA_CNFG 0x48 /* DMA Configuration */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define HIFN_1_PLL 0x4c /* 795x: PLL config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define HIFN_1_7811_RNGENA 0x60 /* 7811: rng enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define HIFN_1_7811_RNGCFG 0x64 /* 7811: rng config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define HIFN_1_7811_RNGDAT 0x68 /* 7811: rng data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define HIFN_1_7811_RNGSTS 0x6c /* 7811: rng status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define HIFN_1_7811_MIPSRST 0x94 /* 7811: MIPS reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define HIFN_1_REVID 0x98 /* Revision ID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define HIFN_1_UNLOCK_SECRET1 0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define HIFN_1_UNLOCK_SECRET2 0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define HIFN_1_PUB_RESET 0x204 /* Public/RNG Reset */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define HIFN_1_PUB_BASE 0x300 /* Public Base Address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define HIFN_1_PUB_OPLEN 0x304 /* Public Operand Length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define HIFN_1_PUB_OP 0x308 /* Public Operand */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define HIFN_1_PUB_STATUS 0x30c /* Public Status */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define HIFN_1_PUB_IEN 0x310 /* Public Interrupt enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define HIFN_1_RNG_CONFIG 0x314 /* RNG config */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define HIFN_1_RNG_DATA 0x318 /* RNG data */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define HIFN_1_PUB_MEM 0x400 /* start of Public key memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define HIFN_1_PUB_MEMEND 0xbff /* end of Public key memory */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* DMA Status and Control Register (HIFN_1_DMA_CSR) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define HIFN_DMACSR_D_CTRLMASK 0xc0000000 /* Destinition Ring Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define HIFN_DMACSR_D_CTRL_NOP 0x00000000 /* Dest. Control: no-op */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define HIFN_DMACSR_D_CTRL_DIS 0x40000000 /* Dest. Control: disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define HIFN_DMACSR_D_CTRL_ENA 0x80000000 /* Dest. Control: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define HIFN_DMACSR_D_ABORT 0x20000000 /* Destinition Ring PCIAbort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define HIFN_DMACSR_D_DONE 0x10000000 /* Destinition Ring Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define HIFN_DMACSR_D_LAST 0x08000000 /* Destinition Ring Last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define HIFN_DMACSR_D_WAIT 0x04000000 /* Destinition Ring Waiting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define HIFN_DMACSR_D_OVER 0x02000000 /* Destinition Ring Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define HIFN_DMACSR_R_CTRL 0x00c00000 /* Result Ring Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define HIFN_DMACSR_R_CTRL_NOP 0x00000000 /* Result Control: no-op */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define HIFN_DMACSR_R_CTRL_DIS 0x00400000 /* Result Control: disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define HIFN_DMACSR_R_CTRL_ENA 0x00800000 /* Result Control: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define HIFN_DMACSR_R_ABORT 0x00200000 /* Result Ring PCI Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define HIFN_DMACSR_R_DONE 0x00100000 /* Result Ring Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define HIFN_DMACSR_R_LAST 0x00080000 /* Result Ring Last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define HIFN_DMACSR_R_WAIT 0x00040000 /* Result Ring Waiting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define HIFN_DMACSR_R_OVER 0x00020000 /* Result Ring Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define HIFN_DMACSR_S_CTRL 0x0000c000 /* Source Ring Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define HIFN_DMACSR_S_CTRL_NOP 0x00000000 /* Source Control: no-op */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define HIFN_DMACSR_S_CTRL_DIS 0x00004000 /* Source Control: disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define HIFN_DMACSR_S_CTRL_ENA 0x00008000 /* Source Control: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define HIFN_DMACSR_S_ABORT 0x00002000 /* Source Ring PCI Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define HIFN_DMACSR_S_DONE 0x00001000 /* Source Ring Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define HIFN_DMACSR_S_LAST 0x00000800 /* Source Ring Last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define HIFN_DMACSR_S_WAIT 0x00000400 /* Source Ring Waiting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define HIFN_DMACSR_ILLW 0x00000200 /* Illegal write (7811 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define HIFN_DMACSR_ILLR 0x00000100 /* Illegal read (7811 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define HIFN_DMACSR_C_CTRL 0x000000c0 /* Command Ring Control */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define HIFN_DMACSR_C_CTRL_NOP 0x00000000 /* Command Control: no-op */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define HIFN_DMACSR_C_CTRL_DIS 0x00000040 /* Command Control: disable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define HIFN_DMACSR_C_CTRL_ENA 0x00000080 /* Command Control: enable */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define HIFN_DMACSR_C_ABORT 0x00000020 /* Command Ring PCI Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define HIFN_DMACSR_C_DONE 0x00000010 /* Command Ring Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define HIFN_DMACSR_C_LAST 0x00000008 /* Command Ring Last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define HIFN_DMACSR_C_WAIT 0x00000004 /* Command Ring Waiting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define HIFN_DMACSR_PUBDONE 0x00000002 /* Public op done (7951 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define HIFN_DMACSR_ENGINE 0x00000001 /* Command Ring Engine IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* DMA Interrupt Enable Register (HIFN_1_DMA_IER) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define HIFN_DMAIER_D_ABORT 0x20000000 /* Destination Ring PCIAbort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define HIFN_DMAIER_D_DONE 0x10000000 /* Destination Ring Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define HIFN_DMAIER_D_LAST 0x08000000 /* Destination Ring Last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define HIFN_DMAIER_D_WAIT 0x04000000 /* Destination Ring Waiting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define HIFN_DMAIER_D_OVER 0x02000000 /* Destination Ring Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define HIFN_DMAIER_R_ABORT 0x00200000 /* Result Ring PCI Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define HIFN_DMAIER_R_DONE 0x00100000 /* Result Ring Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define HIFN_DMAIER_R_LAST 0x00080000 /* Result Ring Last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define HIFN_DMAIER_R_WAIT 0x00040000 /* Result Ring Waiting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define HIFN_DMAIER_R_OVER 0x00020000 /* Result Ring Overflow */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define HIFN_DMAIER_S_ABORT 0x00002000 /* Source Ring PCI Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define HIFN_DMAIER_S_DONE 0x00001000 /* Source Ring Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define HIFN_DMAIER_S_LAST 0x00000800 /* Source Ring Last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define HIFN_DMAIER_S_WAIT 0x00000400 /* Source Ring Waiting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define HIFN_DMAIER_ILLW 0x00000200 /* Illegal write (7811 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define HIFN_DMAIER_ILLR 0x00000100 /* Illegal read (7811 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define HIFN_DMAIER_C_ABORT 0x00000020 /* Command Ring PCI Abort */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define HIFN_DMAIER_C_DONE 0x00000010 /* Command Ring Done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define HIFN_DMAIER_C_LAST 0x00000008 /* Command Ring Last */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define HIFN_DMAIER_C_WAIT 0x00000004 /* Command Ring Waiting */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define HIFN_DMAIER_PUBDONE 0x00000002 /* public op done (7951 only) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define HIFN_DMAIER_ENGINE 0x00000001 /* Engine IRQ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* DMA Configuration Register (HIFN_1_DMA_CNFG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define HIFN_DMACNFG_BIGENDIAN 0x10000000 /* big endian mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define HIFN_DMACNFG_POLLFREQ 0x00ff0000 /* Poll frequency mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define HIFN_DMACNFG_UNLOCK 0x00000800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define HIFN_DMACNFG_POLLINVAL 0x00000700 /* Invalid Poll Scalar */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define HIFN_DMACNFG_LAST 0x00000010 /* Host control LAST bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define HIFN_DMACNFG_MODE 0x00000004 /* DMA mode */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define HIFN_DMACNFG_DMARESET 0x00000002 /* DMA Reset # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define HIFN_DMACNFG_MSTRESET 0x00000001 /* Master Reset # */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) /* PLL configuration register */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define HIFN_PLL_REF_CLK_HBI 0x00000000 /* HBI reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define HIFN_PLL_REF_CLK_PLL 0x00000001 /* PLL reference clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define HIFN_PLL_BP 0x00000002 /* Reference clock bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define HIFN_PLL_PK_CLK_HBI 0x00000000 /* PK engine HBI clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define HIFN_PLL_PK_CLK_PLL 0x00000008 /* PK engine PLL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define HIFN_PLL_PE_CLK_HBI 0x00000000 /* PE engine HBI clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define HIFN_PLL_PE_CLK_PLL 0x00000010 /* PE engine PLL clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define HIFN_PLL_RESERVED_1 0x00000400 /* Reserved bit, must be 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define HIFN_PLL_ND_SHIFT 11 /* Clock multiplier shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define HIFN_PLL_ND_MULT_2 0x00000000 /* PLL clock multiplier 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define HIFN_PLL_ND_MULT_4 0x00000800 /* PLL clock multiplier 4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define HIFN_PLL_ND_MULT_6 0x00001000 /* PLL clock multiplier 6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define HIFN_PLL_ND_MULT_8 0x00001800 /* PLL clock multiplier 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define HIFN_PLL_ND_MULT_10 0x00002000 /* PLL clock multiplier 10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define HIFN_PLL_ND_MULT_12 0x00002800 /* PLL clock multiplier 12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define HIFN_PLL_IS_1_8 0x00000000 /* charge pump (mult. 1-8) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define HIFN_PLL_IS_9_12 0x00010000 /* charge pump (mult. 9-12) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define HIFN_PLL_FCK_MAX 266 /* Maximum PLL frequency */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* Public key reset register (HIFN_1_PUB_RESET) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define HIFN_PUBRST_RESET 0x00000001 /* reset public/rng unit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) /* Public base address register (HIFN_1_PUB_BASE) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define HIFN_PUBBASE_ADDR 0x00003fff /* base address */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) /* Public operand length register (HIFN_1_PUB_OPLEN) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define HIFN_PUBOPLEN_MOD_M 0x0000007f /* modulus length mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define HIFN_PUBOPLEN_MOD_S 0 /* modulus length shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define HIFN_PUBOPLEN_EXP_M 0x0003ff80 /* exponent length mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define HIFN_PUBOPLEN_EXP_S 7 /* exponent length shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define HIFN_PUBOPLEN_RED_M 0x003c0000 /* reducend length mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define HIFN_PUBOPLEN_RED_S 18 /* reducend length shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* Public operation register (HIFN_1_PUB_OP) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define HIFN_PUBOP_AOFFSET_M 0x0000007f /* A offset mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define HIFN_PUBOP_AOFFSET_S 0 /* A offset shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define HIFN_PUBOP_BOFFSET_M 0x00000f80 /* B offset mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define HIFN_PUBOP_BOFFSET_S 7 /* B offset shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define HIFN_PUBOP_MOFFSET_M 0x0003f000 /* M offset mask */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define HIFN_PUBOP_MOFFSET_S 12 /* M offset shift */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define HIFN_PUBOP_OP_MASK 0x003c0000 /* Opcode: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define HIFN_PUBOP_OP_NOP 0x00000000 /* NOP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define HIFN_PUBOP_OP_ADD 0x00040000 /* ADD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define HIFN_PUBOP_OP_ADDC 0x00080000 /* ADD w/carry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define HIFN_PUBOP_OP_SUB 0x000c0000 /* SUB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define HIFN_PUBOP_OP_SUBC 0x00100000 /* SUB w/carry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define HIFN_PUBOP_OP_MODADD 0x00140000 /* Modular ADD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define HIFN_PUBOP_OP_MODSUB 0x00180000 /* Modular SUB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define HIFN_PUBOP_OP_INCA 0x001c0000 /* INC A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define HIFN_PUBOP_OP_DECA 0x00200000 /* DEC A */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define HIFN_PUBOP_OP_MULT 0x00240000 /* MULT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define HIFN_PUBOP_OP_MODMULT 0x00280000 /* Modular MULT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define HIFN_PUBOP_OP_MODRED 0x002c0000 /* Modular RED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define HIFN_PUBOP_OP_MODEXP 0x00300000 /* Modular EXP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* Public status register (HIFN_1_PUB_STATUS) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define HIFN_PUBSTS_DONE 0x00000001 /* operation done */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define HIFN_PUBSTS_CARRY 0x00000002 /* carry */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) /* Public interrupt enable register (HIFN_1_PUB_IEN) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define HIFN_PUBIEN_DONE 0x00000001 /* operation done interrupt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) /* Random number generator config register (HIFN_1_RNG_CONFIG) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define HIFN_RNGCFG_ENA 0x00000001 /* enable rng */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define HIFN_NAMESIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define HIFN_MAX_RESULT_ORDER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define HIFN_D_CMD_RSIZE (24 * 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define HIFN_D_SRC_RSIZE (80 * 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define HIFN_D_DST_RSIZE (80 * 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define HIFN_D_RES_RSIZE (24 * 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define HIFN_D_DST_DALIGN 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define HIFN_QUEUE_LENGTH (HIFN_D_CMD_RSIZE - 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define AES_MIN_KEY_SIZE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define AES_MAX_KEY_SIZE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define HIFN_DES_KEY_LENGTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define HIFN_3DES_KEY_LENGTH 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define HIFN_MAX_CRYPT_KEY_LENGTH AES_MAX_KEY_SIZE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define HIFN_IV_LENGTH 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define HIFN_AES_IV_LENGTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define HIFN_MAX_IV_LENGTH HIFN_AES_IV_LENGTH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define HIFN_MAC_KEY_LENGTH 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define HIFN_MD5_LENGTH 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define HIFN_SHA1_LENGTH 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define HIFN_MAC_TRUNC_LENGTH 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define HIFN_MAX_COMMAND (8 + 8 + 8 + 64 + 260)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define HIFN_MAX_RESULT (8 + 4 + 4 + 20 + 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define HIFN_USED_RESULT 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) struct hifn_desc {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) volatile __le32 l;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) volatile __le32 p;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) struct hifn_dma {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) struct hifn_desc cmdr[HIFN_D_CMD_RSIZE + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) struct hifn_desc srcr[HIFN_D_SRC_RSIZE + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) struct hifn_desc dstr[HIFN_D_DST_RSIZE + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) struct hifn_desc resr[HIFN_D_RES_RSIZE + 1];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) u8 command_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_COMMAND];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) u8 result_bufs[HIFN_D_CMD_RSIZE][HIFN_MAX_RESULT];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) * Our current positions for insertion and removal from the descriptor
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) * rings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) volatile int cmdi, srci, dsti, resi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) volatile int cmdu, srcu, dstu, resu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) int cmdk, srck, dstk, resk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define HIFN_FLAG_CMD_BUSY (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define HIFN_FLAG_SRC_BUSY (1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define HIFN_FLAG_DST_BUSY (1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define HIFN_FLAG_RES_BUSY (1 << 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define HIFN_FLAG_OLD_KEY (1 << 4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define HIFN_DEFAULT_ACTIVE_NUM 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) struct hifn_device {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) char name[HIFN_NAMESIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) int irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) struct pci_dev *pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) void __iomem *bar[3];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) void *desc_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) dma_addr_t desc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) u32 dmareg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) void *sa[HIFN_D_RES_RSIZE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) spinlock_t lock;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) int active, started;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) struct delayed_work work;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) unsigned long reset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) unsigned long success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) unsigned long prev_success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) u8 snum;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) struct tasklet_struct tasklet;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) struct crypto_queue queue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) struct list_head alg_list;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) unsigned int pk_clk_freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) unsigned int rng_wait_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) ktime_t rngtime;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) struct hwrng rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define HIFN_D_LENGTH 0x0000ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define HIFN_D_NOINVALID 0x01000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define HIFN_D_MASKDONEIRQ 0x02000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define HIFN_D_DESTOVER 0x04000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define HIFN_D_OVER 0x08000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define HIFN_D_LAST 0x20000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define HIFN_D_JUMP 0x40000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define HIFN_D_VALID 0x80000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) struct hifn_base_command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) volatile __le16 masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) volatile __le16 session_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) volatile __le16 total_source_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) volatile __le16 total_dest_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define HIFN_BASE_CMD_COMP 0x0100 /* enable compression engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define HIFN_BASE_CMD_PAD 0x0200 /* enable padding engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define HIFN_BASE_CMD_MAC 0x0400 /* enable MAC engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define HIFN_BASE_CMD_CRYPT 0x0800 /* enable crypt engine */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define HIFN_BASE_CMD_DECODE 0x2000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define HIFN_BASE_CMD_SRCLEN_M 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define HIFN_BASE_CMD_SRCLEN_S 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define HIFN_BASE_CMD_DSTLEN_M 0x3000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define HIFN_BASE_CMD_DSTLEN_S 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define HIFN_BASE_CMD_LENMASK_HI 0x30000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define HIFN_BASE_CMD_LENMASK_LO 0x0ffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) * Structure to help build up the command data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) struct hifn_crypt_command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) volatile __le16 masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) volatile __le16 header_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) volatile __le16 source_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) volatile __le16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define HIFN_CRYPT_CMD_ALG_MASK 0x0003 /* algorithm: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define HIFN_CRYPT_CMD_ALG_DES 0x0000 /* DES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define HIFN_CRYPT_CMD_ALG_3DES 0x0001 /* 3DES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define HIFN_CRYPT_CMD_ALG_RC4 0x0002 /* RC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define HIFN_CRYPT_CMD_ALG_AES 0x0003 /* AES */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define HIFN_CRYPT_CMD_MODE_MASK 0x0018 /* Encrypt mode: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define HIFN_CRYPT_CMD_MODE_ECB 0x0000 /* ECB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define HIFN_CRYPT_CMD_MODE_CBC 0x0008 /* CBC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define HIFN_CRYPT_CMD_MODE_CFB 0x0010 /* CFB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define HIFN_CRYPT_CMD_MODE_OFB 0x0018 /* OFB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define HIFN_CRYPT_CMD_CLR_CTX 0x0040 /* clear context */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define HIFN_CRYPT_CMD_KSZ_MASK 0x0600 /* AES key size: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define HIFN_CRYPT_CMD_KSZ_128 0x0000 /* 128 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define HIFN_CRYPT_CMD_KSZ_192 0x0200 /* 192 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define HIFN_CRYPT_CMD_KSZ_256 0x0400 /* 256 bit */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define HIFN_CRYPT_CMD_NEW_KEY 0x0800 /* expect new key */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define HIFN_CRYPT_CMD_NEW_IV 0x1000 /* expect new iv */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define HIFN_CRYPT_CMD_SRCLEN_M 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define HIFN_CRYPT_CMD_SRCLEN_S 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) * Structure to help build up the command data structure.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) struct hifn_mac_command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) volatile __le16 masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) volatile __le16 header_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) volatile __le16 source_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) volatile __le16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define HIFN_MAC_CMD_ALG_MASK 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define HIFN_MAC_CMD_ALG_SHA1 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define HIFN_MAC_CMD_ALG_MD5 0x0001
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define HIFN_MAC_CMD_MODE_MASK 0x000c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define HIFN_MAC_CMD_MODE_HMAC 0x0000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define HIFN_MAC_CMD_MODE_SSL_MAC 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define HIFN_MAC_CMD_MODE_HASH 0x0008
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define HIFN_MAC_CMD_MODE_FULL 0x0004
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define HIFN_MAC_CMD_TRUNC 0x0010
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define HIFN_MAC_CMD_RESULT 0x0020
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define HIFN_MAC_CMD_APPEND 0x0040
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define HIFN_MAC_CMD_SRCLEN_M 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define HIFN_MAC_CMD_SRCLEN_S 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) * MAC POS IPsec initiates authentication after encryption on encodes
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) * and before decryption on decodes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define HIFN_MAC_CMD_POS_IPSEC 0x0200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define HIFN_MAC_CMD_NEW_KEY 0x0800
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) struct hifn_comp_command {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) volatile __le16 masks;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) volatile __le16 header_skip;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) volatile __le16 source_count;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) volatile __le16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define HIFN_COMP_CMD_SRCLEN_M 0xc000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define HIFN_COMP_CMD_SRCLEN_S 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define HIFN_COMP_CMD_ONE 0x0100 /* must be one */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define HIFN_COMP_CMD_CLEARHIST 0x0010 /* clear history */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define HIFN_COMP_CMD_UPDATEHIST 0x0008 /* update history */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define HIFN_COMP_CMD_LZS_STRIP0 0x0004 /* LZS: strip zero */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define HIFN_COMP_CMD_MPPC_RESTART 0x0004 /* MPPC: restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define HIFN_COMP_CMD_ALG_MASK 0x0001 /* compression mode: */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define HIFN_COMP_CMD_ALG_MPPC 0x0001 /* MPPC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define HIFN_COMP_CMD_ALG_LZS 0x0000 /* LZS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) struct hifn_base_result {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) volatile __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) volatile __le16 session;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) volatile __le16 src_cnt; /* 15:0 of source count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) volatile __le16 dst_cnt; /* 15:0 of dest count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define HIFN_BASE_RES_DSTOVERRUN 0x0200 /* destination overrun */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define HIFN_BASE_RES_SRCLEN_M 0xc000 /* 17:16 of source count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define HIFN_BASE_RES_SRCLEN_S 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define HIFN_BASE_RES_DSTLEN_M 0x3000 /* 17:16 of dest count */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define HIFN_BASE_RES_DSTLEN_S 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) struct hifn_comp_result {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) volatile __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) volatile __le16 crc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define HIFN_COMP_RES_LCB_M 0xff00 /* longitudinal check byte */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define HIFN_COMP_RES_LCB_S 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define HIFN_COMP_RES_RESTART 0x0004 /* MPPC: restart */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define HIFN_COMP_RES_ENDMARKER 0x0002 /* LZS: end marker seen */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define HIFN_COMP_RES_SRC_NOTZERO 0x0001 /* source expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) struct hifn_mac_result {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) volatile __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) volatile __le16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) /* followed by 0, 6, 8, or 10 u16's of the MAC, then crypt */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define HIFN_MAC_RES_MISCOMPARE 0x0002 /* compare failed */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define HIFN_MAC_RES_SRC_NOTZERO 0x0001 /* source expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) struct hifn_crypt_result {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) volatile __le16 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) volatile __le16 reserved;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define HIFN_CRYPT_RES_SRC_NOTZERO 0x0001 /* source expired */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #ifndef HIFN_POLL_FREQUENCY
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define HIFN_POLL_FREQUENCY 0x1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #ifndef HIFN_POLL_SCALAR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define HIFN_POLL_SCALAR 0x0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define HIFN_MAX_SEGLEN 0xffff /* maximum dma segment len */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define HIFN_MAX_DMALEN 0x3ffff /* maximum dma length */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) struct hifn_crypto_alg {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) struct list_head entry;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) struct skcipher_alg alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) struct hifn_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define ASYNC_SCATTERLIST_CACHE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define ASYNC_FLAGS_MISALIGNED (1 << 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) struct hifn_cipher_walk {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) struct scatterlist cache[ASYNC_SCATTERLIST_CACHE];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) u32 flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) int num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) struct hifn_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) u8 key[HIFN_MAX_CRYPT_KEY_LENGTH];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) struct hifn_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) unsigned int keysize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) struct hifn_request_context {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) u8 *iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) unsigned int ivsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) u8 op, type, mode, unused;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) struct hifn_cipher_walk walk;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define crypto_alg_to_hifn(a) container_of(a, struct hifn_crypto_alg, alg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) static inline u32 hifn_read_0(struct hifn_device *dev, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) return readl(dev->bar[0] + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) static inline u32 hifn_read_1(struct hifn_device *dev, u32 reg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) return readl(dev->bar[1] + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) static inline void hifn_write_0(struct hifn_device *dev, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) writel((__force u32)cpu_to_le32(val), dev->bar[0] + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) writel((__force u32)cpu_to_le32(val), dev->bar[1] + reg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) static void hifn_wait_puc(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) u32 ret;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) for (i = 10000; i > 0; --i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) ret = hifn_read_0(dev, HIFN_0_PUCTRL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) if (!(ret & HIFN_PUCTRL_RESET))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) udelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) if (!i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) dev_err(&dev->pdev->dev, "Failed to reset PUC unit.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) static void hifn_reset_puc(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) hifn_wait_puc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) static void hifn_stop_device(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) hifn_write_1(dev, HIFN_1_DMA_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) hifn_write_0(dev, HIFN_0_PUIER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) hifn_write_1(dev, HIFN_1_DMA_IER, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) static void hifn_reset_dma(struct hifn_device *dev, int full)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) hifn_stop_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) * Setting poll frequency and others to 0.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) * Reset DMA.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) if (full) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) HIFN_DMACNFG_MSTRESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) hifn_reset_puc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) hifn_reset_puc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) static u32 hifn_next_signature(u32 a, u_int cnt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) u32 v;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) for (i = 0; i < cnt; i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) /* get the parity */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) v = a & 0x80080125;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) v ^= v >> 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) v ^= v >> 8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) v ^= v >> 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) v ^= v >> 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) v ^= v >> 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) a = (v & 1) ^ (a << 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) return a;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) static struct pci2id {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) u_short pci_vendor;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) u_short pci_prod;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) char card_id[13];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) } pci2id[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) PCI_VENDOR_ID_HIFN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) PCI_DEVICE_ID_HIFN_7955,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) 0x00, 0x00, 0x00, 0x00, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) PCI_VENDOR_ID_HIFN,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) PCI_DEVICE_ID_HIFN_7956,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) 0x00, 0x00, 0x00, 0x00, 0x00 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) static int hifn_rng_data_present(struct hwrng *rng, int wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) struct hifn_device *dev = (struct hifn_device *)rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) s64 nsec;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) nsec = ktime_to_ns(ktime_sub(ktime_get(), dev->rngtime));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) nsec -= dev->rng_wait_time;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) if (nsec <= 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) if (!wait)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) ndelay(nsec);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) return 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) static int hifn_rng_data_read(struct hwrng *rng, u32 *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) struct hifn_device *dev = (struct hifn_device *)rng->priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) *data = hifn_read_1(dev, HIFN_1_RNG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) dev->rngtime = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) return 4;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) static int hifn_register_rng(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) * We must wait at least 256 Pk_clk cycles between two reads of the rng.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) dev->rng_wait_time = DIV_ROUND_UP_ULL(NSEC_PER_SEC,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) dev->pk_clk_freq) * 256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) dev->rng.name = dev->name;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) dev->rng.data_present = hifn_rng_data_present;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) dev->rng.data_read = hifn_rng_data_read;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) dev->rng.priv = (unsigned long)dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) return hwrng_register(&dev->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) static void hifn_unregister_rng(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) hwrng_unregister(&dev->rng);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) #define hifn_register_rng(dev) 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define hifn_unregister_rng(dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) static int hifn_init_pubrng(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) HIFN_PUBRST_RESET);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) for (i = 100; i > 0; --i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) if ((hifn_read_1(dev, HIFN_1_PUB_RESET) & HIFN_PUBRST_RESET) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) if (!i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) dev_err(&dev->pdev->dev, "Failed to initialise public key engine.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) dev->dmareg |= HIFN_DMAIER_PUBDONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) dev_dbg(&dev->pdev->dev, "Public key engine has been successfully initialised.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /* Enable RNG engine. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) hifn_write_1(dev, HIFN_1_RNG_CONFIG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) hifn_read_1(dev, HIFN_1_RNG_CONFIG) | HIFN_RNGCFG_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) dev_dbg(&dev->pdev->dev, "RNG engine has been successfully initialised.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) #ifdef CONFIG_CRYPTO_DEV_HIFN_795X_RNG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) /* First value must be discarded */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) hifn_read_1(dev, HIFN_1_RNG_DATA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) dev->rngtime = ktime_get();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) static int hifn_enable_crypto(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) u32 dmacfg, addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) char *offtbl = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) for (i = 0; i < ARRAY_SIZE(pci2id); i++) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) if (pci2id[i].pci_vendor == dev->pdev->vendor &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) pci2id[i].pci_prod == dev->pdev->device) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) offtbl = pci2id[i].card_id;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) if (!offtbl) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) dev_err(&dev->pdev->dev, "Unknown card!\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) dmacfg = hifn_read_1(dev, HIFN_1_DMA_CNFG);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) hifn_write_1(dev, HIFN_1_DMA_CNFG,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) HIFN_DMACNFG_UNLOCK | HIFN_DMACNFG_MSTRESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) addr = hifn_read_1(dev, HIFN_1_UNLOCK_SECRET1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) for (i = 0; i < 12; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) addr = hifn_next_signature(addr, offtbl[i] + 0x101);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) mdelay(1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) dev_dbg(&dev->pdev->dev, "%s %s.\n", dev->name, pci_name(dev->pdev));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) static void hifn_init_dma(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) u32 dptr = dev->desc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) for (i = 0; i < HIFN_D_CMD_RSIZE; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) dma->cmdr[i].p = __cpu_to_le32(dptr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) offsetof(struct hifn_dma, command_bufs[i][0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) for (i = 0; i < HIFN_D_RES_RSIZE; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) dma->resr[i].p = __cpu_to_le32(dptr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) offsetof(struct hifn_dma, result_bufs[i][0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) /* Setup LAST descriptors. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) dma->cmdr[HIFN_D_CMD_RSIZE].p = __cpu_to_le32(dptr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) offsetof(struct hifn_dma, cmdr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) dma->srcr[HIFN_D_SRC_RSIZE].p = __cpu_to_le32(dptr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) offsetof(struct hifn_dma, srcr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) dma->dstr[HIFN_D_DST_RSIZE].p = __cpu_to_le32(dptr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) offsetof(struct hifn_dma, dstr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) dma->resr[HIFN_D_RES_RSIZE].p = __cpu_to_le32(dptr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) offsetof(struct hifn_dma, resr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) dma->cmdu = dma->srcu = dma->dstu = dma->resu = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) dma->cmdi = dma->srci = dma->dsti = dma->resi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) dma->cmdk = dma->srck = dma->dstk = dma->resk = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) * Initialize the PLL. We need to know the frequency of the reference clock
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) * to calculate the optimal multiplier. For PCI we assume 66MHz, since that
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) * allows us to operate without the risk of overclocking the chip. If it
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) * actually uses 33MHz, the chip will operate at half the speed, this can be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) * overridden by specifying the frequency as module parameter (pci33).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) * Unfortunately the PCI clock is not very suitable since the HIFN needs a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) * stable clock and the PCI clock frequency may vary, so the default is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) * external clock. There is no way to find out its frequency, we default to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) * 66MHz since according to Mike Ham of HiFn, almost every board in existence
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) * has an external crystal populated at 66MHz.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) static void hifn_init_pll(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) unsigned int freq, m;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) u32 pllcfg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) pllcfg = HIFN_1_PLL | HIFN_PLL_RESERVED_1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) if (strncmp(hifn_pll_ref, "ext", 3) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) pllcfg |= HIFN_PLL_REF_CLK_PLL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) pllcfg |= HIFN_PLL_REF_CLK_HBI;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) if (hifn_pll_ref[3] != '\0')
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) freq = 66;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) dev_info(&dev->pdev->dev, "assuming %uMHz clock speed, override with hifn_pll_ref=%.3s<frequency>\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938) freq, hifn_pll_ref);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) m = HIFN_PLL_FCK_MAX / freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 942)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 943) pllcfg |= (m / 2 - 1) << HIFN_PLL_ND_SHIFT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 944) if (m <= 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 945) pllcfg |= HIFN_PLL_IS_1_8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 946) else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 947) pllcfg |= HIFN_PLL_IS_9_12;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 949) /* Select clock source and enable clock bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 950) hifn_write_1(dev, HIFN_1_PLL, pllcfg |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 951) HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI | HIFN_PLL_BP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 953) /* Let the chip lock to the input clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 954) mdelay(10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 955)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 956) /* Disable clock bypass */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 957) hifn_write_1(dev, HIFN_1_PLL, pllcfg |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 958) HIFN_PLL_PK_CLK_HBI | HIFN_PLL_PE_CLK_HBI);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 959)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 960) /* Switch the engines to the PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 961) hifn_write_1(dev, HIFN_1_PLL, pllcfg |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 962) HIFN_PLL_PK_CLK_PLL | HIFN_PLL_PE_CLK_PLL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 963)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 964) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 965) * The Fpk_clk runs at half the total speed. Its frequency is needed to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 966) * calculate the minimum time between two reads of the rng. Since 33MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 967) * is actually 33.333... we overestimate the frequency here, resulting
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 968) * in slightly larger intervals.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 969) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 970) dev->pk_clk_freq = 1000000 * (freq + 1) * m / 2;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 971) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 972)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 973) static void hifn_init_registers(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 974) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 975) u32 dptr = dev->desc_dma;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 977) /* Initialization magic... */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 978) hifn_write_0(dev, HIFN_0_PUCTRL, HIFN_PUCTRL_DMAENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 979) hifn_write_0(dev, HIFN_0_FIFOCNFG, HIFN_FIFOCNFG_THRESHOLD);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 980) hifn_write_0(dev, HIFN_0_PUIER, HIFN_PUIER_DSTOVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 981)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 982) /* write all 4 ring address registers */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 983) hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 984) offsetof(struct hifn_dma, cmdr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 985) hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 986) offsetof(struct hifn_dma, srcr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 987) hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 988) offsetof(struct hifn_dma, dstr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 989) hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr +
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 990) offsetof(struct hifn_dma, resr[0]));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 992) mdelay(2);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 993) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 994) hifn_write_1(dev, HIFN_1_DMA_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 995) HIFN_DMACSR_D_CTRL_DIS | HIFN_DMACSR_R_CTRL_DIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 996) HIFN_DMACSR_S_CTRL_DIS | HIFN_DMACSR_C_CTRL_DIS |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 997) HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 998) HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 999) HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1000) HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1001) HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1002) HIFN_DMACSR_S_WAIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1003) HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1004) HIFN_DMACSR_C_WAIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1005) HIFN_DMACSR_ENGINE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1006) HIFN_DMACSR_PUBDONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1007) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1008) hifn_write_1(dev, HIFN_1_DMA_CSR,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1009) HIFN_DMACSR_C_CTRL_ENA | HIFN_DMACSR_S_CTRL_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1010) HIFN_DMACSR_D_CTRL_ENA | HIFN_DMACSR_R_CTRL_ENA |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1011) HIFN_DMACSR_D_ABORT | HIFN_DMACSR_D_DONE | HIFN_DMACSR_D_LAST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1012) HIFN_DMACSR_D_WAIT | HIFN_DMACSR_D_OVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1013) HIFN_DMACSR_R_ABORT | HIFN_DMACSR_R_DONE | HIFN_DMACSR_R_LAST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1014) HIFN_DMACSR_R_WAIT | HIFN_DMACSR_R_OVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1015) HIFN_DMACSR_S_ABORT | HIFN_DMACSR_S_DONE | HIFN_DMACSR_S_LAST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1016) HIFN_DMACSR_S_WAIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1017) HIFN_DMACSR_C_ABORT | HIFN_DMACSR_C_DONE | HIFN_DMACSR_C_LAST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1018) HIFN_DMACSR_C_WAIT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1019) HIFN_DMACSR_ENGINE |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1020) HIFN_DMACSR_PUBDONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1021) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1022) hifn_read_1(dev, HIFN_1_DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1023)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1024) dev->dmareg |= HIFN_DMAIER_R_DONE | HIFN_DMAIER_C_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1025) HIFN_DMAIER_D_OVER | HIFN_DMAIER_R_OVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1026) HIFN_DMAIER_S_ABORT | HIFN_DMAIER_D_ABORT | HIFN_DMAIER_R_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1027) HIFN_DMAIER_ENGINE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1028) dev->dmareg &= ~HIFN_DMAIER_C_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1029)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1030) hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1031) hifn_read_1(dev, HIFN_1_DMA_IER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1032) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1033) hifn_write_0(dev, HIFN_0_PUCNFG, HIFN_PUCNFG_ENCCNFG |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1034) HIFN_PUCNFG_DRFR_128 | HIFN_PUCNFG_TCALLPHASES |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1035) HIFN_PUCNFG_TCDRVTOTEM | HIFN_PUCNFG_BUS32 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1036) HIFN_PUCNFG_DRAM);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1037) #else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1038) hifn_write_0(dev, HIFN_0_PUCNFG, 0x10342);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1039) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1040) hifn_init_pll(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1041)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1042) hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1043) hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1044) HIFN_DMACNFG_DMARESET | HIFN_DMACNFG_MODE | HIFN_DMACNFG_LAST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1045) ((HIFN_POLL_FREQUENCY << 16 ) & HIFN_DMACNFG_POLLFREQ) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1046) ((HIFN_POLL_SCALAR << 8) & HIFN_DMACNFG_POLLINVAL));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1047) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1048)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1049) static int hifn_setup_base_command(struct hifn_device *dev, u8 *buf,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1050) unsigned dlen, unsigned slen, u16 mask, u8 snum)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1051) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1052) struct hifn_base_command *base_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1053) u8 *buf_pos = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1054)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1055) base_cmd = (struct hifn_base_command *)buf_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1056) base_cmd->masks = __cpu_to_le16(mask);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1057) base_cmd->total_source_count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1058) __cpu_to_le16(slen & HIFN_BASE_CMD_LENMASK_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1059) base_cmd->total_dest_count =
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1060) __cpu_to_le16(dlen & HIFN_BASE_CMD_LENMASK_LO);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1061)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1062) dlen >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1063) slen >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1064) base_cmd->session_num = __cpu_to_le16(snum |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1065) ((slen << HIFN_BASE_CMD_SRCLEN_S) & HIFN_BASE_CMD_SRCLEN_M) |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1066) ((dlen << HIFN_BASE_CMD_DSTLEN_S) & HIFN_BASE_CMD_DSTLEN_M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1067)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1068) return sizeof(struct hifn_base_command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1069) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1070)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1071) static int hifn_setup_crypto_command(struct hifn_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1072) u8 *buf, unsigned dlen, unsigned slen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1073) u8 *key, int keylen, u8 *iv, int ivsize, u16 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1074) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1075) struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1076) struct hifn_crypt_command *cry_cmd;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1077) u8 *buf_pos = buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1078) u16 cmd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1080) cry_cmd = (struct hifn_crypt_command *)buf_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1081)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1082) cry_cmd->source_count = __cpu_to_le16(dlen & 0xffff);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1083) dlen >>= 16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1084) cry_cmd->masks = __cpu_to_le16(mode |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1085) ((dlen << HIFN_CRYPT_CMD_SRCLEN_S) &
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1086) HIFN_CRYPT_CMD_SRCLEN_M));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1087) cry_cmd->header_skip = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1088) cry_cmd->reserved = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1089)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1090) buf_pos += sizeof(struct hifn_crypt_command);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1091)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1092) dma->cmdu++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1093) if (dma->cmdu > 1) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1094) dev->dmareg |= HIFN_DMAIER_C_WAIT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1095) hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1096) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1097)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1098) if (keylen) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1099) memcpy(buf_pos, key, keylen);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1100) buf_pos += keylen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1101) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1102) if (ivsize) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1103) memcpy(buf_pos, iv, ivsize);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1104) buf_pos += ivsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1105) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1107) cmd_len = buf_pos - buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1108)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1109) return cmd_len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1110) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1111)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1112) static int hifn_setup_cmd_desc(struct hifn_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1113) struct hifn_context *ctx, struct hifn_request_context *rctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1114) void *priv, unsigned int nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1115) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1116) struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1117) int cmd_len, sa_idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1118) u8 *buf, *buf_pos;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1119) u16 mask;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1120)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1121) sa_idx = dma->cmdi;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1122) buf_pos = buf = dma->command_bufs[dma->cmdi];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1123)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1124) mask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1125) switch (rctx->op) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1126) case ACRYPTO_OP_DECRYPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1127) mask = HIFN_BASE_CMD_CRYPT | HIFN_BASE_CMD_DECODE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1128) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1129) case ACRYPTO_OP_ENCRYPT:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1130) mask = HIFN_BASE_CMD_CRYPT;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1131) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1132) case ACRYPTO_OP_HMAC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1133) mask = HIFN_BASE_CMD_MAC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1134) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1135) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1136) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1137) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1138)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1139) buf_pos += hifn_setup_base_command(dev, buf_pos, nbytes,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1140) nbytes, mask, dev->snum);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1141)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1142) if (rctx->op == ACRYPTO_OP_ENCRYPT || rctx->op == ACRYPTO_OP_DECRYPT) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1143) u16 md = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1144)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1145) if (ctx->keysize)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1146) md |= HIFN_CRYPT_CMD_NEW_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1147) if (rctx->iv && rctx->mode != ACRYPTO_MODE_ECB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1148) md |= HIFN_CRYPT_CMD_NEW_IV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1149)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1150) switch (rctx->mode) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1151) case ACRYPTO_MODE_ECB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1152) md |= HIFN_CRYPT_CMD_MODE_ECB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1153) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1154) case ACRYPTO_MODE_CBC:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1155) md |= HIFN_CRYPT_CMD_MODE_CBC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1156) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1157) case ACRYPTO_MODE_CFB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1158) md |= HIFN_CRYPT_CMD_MODE_CFB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1159) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1160) case ACRYPTO_MODE_OFB:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1161) md |= HIFN_CRYPT_CMD_MODE_OFB;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1162) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1163) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1164) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1166)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1167) switch (rctx->type) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1168) case ACRYPTO_TYPE_AES_128:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1169) if (ctx->keysize != 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1170) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1171) md |= HIFN_CRYPT_CMD_KSZ_128 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1172) HIFN_CRYPT_CMD_ALG_AES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1173) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1174) case ACRYPTO_TYPE_AES_192:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1175) if (ctx->keysize != 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1176) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1177) md |= HIFN_CRYPT_CMD_KSZ_192 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1178) HIFN_CRYPT_CMD_ALG_AES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1179) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1180) case ACRYPTO_TYPE_AES_256:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1181) if (ctx->keysize != 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1182) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1183) md |= HIFN_CRYPT_CMD_KSZ_256 |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1184) HIFN_CRYPT_CMD_ALG_AES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1185) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1186) case ACRYPTO_TYPE_3DES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1187) if (ctx->keysize != 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1188) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1189) md |= HIFN_CRYPT_CMD_ALG_3DES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1190) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1191) case ACRYPTO_TYPE_DES:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1192) if (ctx->keysize != 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1193) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1194) md |= HIFN_CRYPT_CMD_ALG_DES;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1195) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1196) default:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1197) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1198) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1199)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1200) buf_pos += hifn_setup_crypto_command(dev, buf_pos,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1201) nbytes, nbytes, ctx->key, ctx->keysize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1202) rctx->iv, rctx->ivsize, md);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1203) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1204)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1205) dev->sa[sa_idx] = priv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1206) dev->started++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1207)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1208) cmd_len = buf_pos - buf;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1209) dma->cmdr[dma->cmdi].l = __cpu_to_le32(cmd_len | HIFN_D_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1210) HIFN_D_LAST | HIFN_D_MASKDONEIRQ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1211)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1212) if (++dma->cmdi == HIFN_D_CMD_RSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1213) dma->cmdr[dma->cmdi].l = __cpu_to_le32(
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1214) HIFN_D_VALID | HIFN_D_LAST |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1215) HIFN_D_MASKDONEIRQ | HIFN_D_JUMP);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1216) dma->cmdi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1217) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1218) dma->cmdr[dma->cmdi - 1].l |= __cpu_to_le32(HIFN_D_VALID);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1219) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1220)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1221) if (!(dev->flags & HIFN_FLAG_CMD_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1222) hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1223) dev->flags |= HIFN_FLAG_CMD_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1224) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1225) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1226)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1227) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1228) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1229) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1230)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1231) static int hifn_setup_src_desc(struct hifn_device *dev, struct page *page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1232) unsigned int offset, unsigned int size, int last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1233) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1234) struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1235) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1236) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1237)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1238) addr = dma_map_page(&dev->pdev->dev, page, offset, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1239) DMA_TO_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1240)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1241) idx = dma->srci;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1242)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1243) dma->srcr[idx].p = __cpu_to_le32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1244) dma->srcr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1245) HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1246)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1247) if (++idx == HIFN_D_SRC_RSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1248) dma->srcr[idx].l = __cpu_to_le32(HIFN_D_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1249) HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1250) (last ? HIFN_D_LAST : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1251) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1252) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1253)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1254) dma->srci = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1255) dma->srcu++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1256)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1257) if (!(dev->flags & HIFN_FLAG_SRC_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1258) hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1259) dev->flags |= HIFN_FLAG_SRC_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1260) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1261)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1262) return size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1263) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1264)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1265) static void hifn_setup_res_desc(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1266) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1267) struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1268)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1269) dma->resr[dma->resi].l = __cpu_to_le32(HIFN_USED_RESULT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1270) HIFN_D_VALID | HIFN_D_LAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1271) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1272) * dma->resr[dma->resi].l = __cpu_to_le32(HIFN_MAX_RESULT | HIFN_D_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1273) * HIFN_D_LAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1274) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1275)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1276) if (++dma->resi == HIFN_D_RES_RSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1277) dma->resr[HIFN_D_RES_RSIZE].l = __cpu_to_le32(HIFN_D_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1278) HIFN_D_JUMP | HIFN_D_MASKDONEIRQ | HIFN_D_LAST);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1279) dma->resi = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1280) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1281)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1282) dma->resu++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1283)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1284) if (!(dev->flags & HIFN_FLAG_RES_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1285) hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1286) dev->flags |= HIFN_FLAG_RES_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1287) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1288) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1289)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1290) static void hifn_setup_dst_desc(struct hifn_device *dev, struct page *page,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1291) unsigned offset, unsigned size, int last)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1292) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1293) struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1294) int idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1295) dma_addr_t addr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1296)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1297) addr = dma_map_page(&dev->pdev->dev, page, offset, size,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1298) DMA_FROM_DEVICE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1299)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1300) idx = dma->dsti;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1301) dma->dstr[idx].p = __cpu_to_le32(addr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1302) dma->dstr[idx].l = __cpu_to_le32(size | HIFN_D_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1303) HIFN_D_MASKDONEIRQ | (last ? HIFN_D_LAST : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1304)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1305) if (++idx == HIFN_D_DST_RSIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1306) dma->dstr[idx].l = __cpu_to_le32(HIFN_D_VALID |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1307) HIFN_D_JUMP | HIFN_D_MASKDONEIRQ |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1308) (last ? HIFN_D_LAST : 0));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1309) idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1310) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1311) dma->dsti = idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1312) dma->dstu++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1313)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1314) if (!(dev->flags & HIFN_FLAG_DST_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1315) hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1316) dev->flags |= HIFN_FLAG_DST_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1317) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1318) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1319)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1320) static int hifn_setup_dma(struct hifn_device *dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1321) struct hifn_context *ctx, struct hifn_request_context *rctx,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1322) struct scatterlist *src, struct scatterlist *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1323) unsigned int nbytes, void *priv)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1324) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1325) struct scatterlist *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1326) struct page *spage, *dpage;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1327) unsigned int soff, doff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1328) unsigned int n, len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1329)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1330) n = nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1331) while (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1332) spage = sg_page(src);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1333) soff = src->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1334) len = min(src->length, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1335)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1336) hifn_setup_src_desc(dev, spage, soff, len, n - len == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1337)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1338) src++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1339) n -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1340) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1341)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1342) t = &rctx->walk.cache[0];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1343) n = nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1344) while (n) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1345) if (t->length && rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1346) BUG_ON(!sg_page(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1347) dpage = sg_page(t);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1348) doff = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1349) len = t->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1350) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1351) BUG_ON(!sg_page(dst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1352) dpage = sg_page(dst);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1353) doff = dst->offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1354) len = dst->length;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1355) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1356) len = min(len, n);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1357)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1358) hifn_setup_dst_desc(dev, dpage, doff, len, n - len == 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1359)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1360) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1361) t++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1362) n -= len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1363) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1364)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1365) hifn_setup_cmd_desc(dev, ctx, rctx, priv, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1366) hifn_setup_res_desc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1367) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1368) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1369)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1370) static int hifn_cipher_walk_init(struct hifn_cipher_walk *w,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1371) int num, gfp_t gfp_flags)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1372) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1373) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1374)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1375) num = min(ASYNC_SCATTERLIST_CACHE, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1376) sg_init_table(w->cache, num);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1378) w->num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1379) for (i = 0; i < num; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1380) struct page *page = alloc_page(gfp_flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1381) struct scatterlist *s;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1382)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1383) if (!page)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1384) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1385)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1386) s = &w->cache[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1388) sg_set_page(s, page, PAGE_SIZE, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1389) w->num++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1390) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1391)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1392) return i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1393) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1394)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1395) static void hifn_cipher_walk_exit(struct hifn_cipher_walk *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1396) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1397) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1398)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1399) for (i = 0; i < w->num; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1400) struct scatterlist *s = &w->cache[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1401)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1402) __free_page(sg_page(s));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1403)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1404) s->length = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1405) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1407) w->num = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1408) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1409)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1410) static int skcipher_add(unsigned int *drestp, struct scatterlist *dst,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1411) unsigned int size, unsigned int *nbytesp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1412) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1413) unsigned int copy, drest = *drestp, nbytes = *nbytesp;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1414) int idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1415)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1416) if (drest < size || size > nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1417) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1418)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1419) while (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1420) copy = min3(drest, size, dst->length);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1421)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1422) size -= copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1423) drest -= copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1424) nbytes -= copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1425)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1426) pr_debug("%s: copy: %u, size: %u, drest: %u, nbytes: %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1427) __func__, copy, size, drest, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1428)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1429) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1430) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1431) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1432)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1433) *nbytesp = nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1434) *drestp = drest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1435)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1436) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1437) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1438)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1439) static int hifn_cipher_walk(struct skcipher_request *req,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1440) struct hifn_cipher_walk *w)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1441) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1442) struct scatterlist *dst, *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1443) unsigned int nbytes = req->cryptlen, offset, copy, diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1444) int idx, tidx, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1445)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1446) tidx = idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1447) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1448) while (nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1449) if (idx >= w->num && (w->flags & ASYNC_FLAGS_MISALIGNED))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1450) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1452) dst = &req->dst[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1453)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1454) pr_debug("\n%s: dlen: %u, doff: %u, offset: %u, nbytes: %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1455) __func__, dst->length, dst->offset, offset, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1457) if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1458) !IS_ALIGNED(dst->length, HIFN_D_DST_DALIGN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1459) offset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1460) unsigned slen = min(dst->length - offset, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1461) unsigned dlen = PAGE_SIZE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1462)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1463) t = &w->cache[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1464)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1465) err = skcipher_add(&dlen, dst, slen, &nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1466) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1467) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1468)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1469) idx += err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1470)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1471) copy = slen & ~(HIFN_D_DST_DALIGN - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1472) diff = slen & (HIFN_D_DST_DALIGN - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1474) if (dlen < nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1475) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1476) * Destination page does not have enough space
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1477) * to put there additional blocksized chunk,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1478) * so we mark that page as containing only
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1479) * blocksize aligned chunks:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1480) * t->length = (slen & ~(HIFN_D_DST_DALIGN - 1));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1481) * and increase number of bytes to be processed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1482) * in next chunk:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1483) * nbytes += diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1484) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1485) nbytes += diff;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1486)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1487) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1488) * Temporary of course...
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1489) * Kick author if you will catch this one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1490) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1491) pr_err("%s: dlen: %u, nbytes: %u, slen: %u, offset: %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1492) __func__, dlen, nbytes, slen, offset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1493) pr_err("%s: please contact author to fix this "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1494) "issue, generally you should not catch "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1495) "this path under any condition but who "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1496) "knows how did you use crypto code.\n"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1497) "Thank you.\n", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1498) BUG();
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1499) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1500) copy += diff + nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1501)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1502) dst = &req->dst[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1503)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1504) err = skcipher_add(&dlen, dst, nbytes, &nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1505) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1506) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1507)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1508) idx += err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1509) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1510)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1511) t->length = copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1512) t->offset = offset;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1513) } else {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1514) nbytes -= min(dst->length, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1515) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1517)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1518) tidx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1519) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1520)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1521) return tidx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1522) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1523)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1524) static int hifn_setup_session(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1525) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1526) struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1527) struct hifn_request_context *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1528) struct hifn_device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1529) unsigned long dlen, flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1530) unsigned int nbytes = req->cryptlen, idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1531) int err = -EINVAL, sg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1532) struct scatterlist *dst;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1534) if (rctx->iv && !rctx->ivsize && rctx->mode != ACRYPTO_MODE_ECB)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1535) goto err_out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1536)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1537) rctx->walk.flags = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1538)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1539) while (nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1540) dst = &req->dst[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1541) dlen = min(dst->length, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1542)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1543) if (!IS_ALIGNED(dst->offset, HIFN_D_DST_DALIGN) ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1544) !IS_ALIGNED(dlen, HIFN_D_DST_DALIGN))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1545) rctx->walk.flags |= ASYNC_FLAGS_MISALIGNED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1546)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1547) nbytes -= dlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1548) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1549) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1550)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1551) if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1552) err = hifn_cipher_walk_init(&rctx->walk, idx, GFP_ATOMIC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1553) if (err < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1554) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1555) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1556)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1557) sg_num = hifn_cipher_walk(req, &rctx->walk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1558) if (sg_num < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1559) err = sg_num;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1560) goto err_out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1561) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1563) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1564) if (dev->started + sg_num > HIFN_QUEUE_LENGTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1565) err = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1566) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1567) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1569) err = hifn_setup_dma(dev, ctx, rctx, req->src, req->dst, req->cryptlen, req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1570) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1571) goto err_out;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1573) dev->snum++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1574)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1575) dev->active = HIFN_DEFAULT_ACTIVE_NUM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1576) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1577)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1578) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1579)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1580) err_out:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1581) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1582) err_out_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1583) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1584) dev_info(&dev->pdev->dev, "iv: %p [%d], key: %p [%d], mode: %u, op: %u, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1585) "type: %u, err: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1586) rctx->iv, rctx->ivsize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1587) ctx->key, ctx->keysize,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1588) rctx->mode, rctx->op, rctx->type, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1589) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1590)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1591) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1592) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1593)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1594) static int hifn_start_device(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1595) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1596) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1597)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1598) dev->started = dev->active = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1599) hifn_reset_dma(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1601) err = hifn_enable_crypto(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1602) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1603) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1604)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1605) hifn_reset_puc(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1606)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1607) hifn_init_dma(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1608)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1609) hifn_init_registers(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1611) hifn_init_pubrng(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1612)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1613) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1614) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1616) static int skcipher_get(void *saddr, unsigned int *srestp, unsigned int offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1617) struct scatterlist *dst, unsigned int size, unsigned int *nbytesp)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1618) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1619) unsigned int srest = *srestp, nbytes = *nbytesp, copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1620) void *daddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1621) int idx = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1622)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1623) if (srest < size || size > nbytes)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1624) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1625)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1626) while (size) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1627) copy = min3(srest, dst->length, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1629) daddr = kmap_atomic(sg_page(dst));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1630) memcpy(daddr + dst->offset + offset, saddr, copy);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1631) kunmap_atomic(daddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1633) nbytes -= copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1634) size -= copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1635) srest -= copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1636) saddr += copy;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1637) offset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1638)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1639) pr_debug("%s: copy: %u, size: %u, srest: %u, nbytes: %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1640) __func__, copy, size, srest, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1641)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1642) dst++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1643) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1644) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1645)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1646) *nbytesp = nbytes;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1647) *srestp = srest;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1648)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1649) return idx;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1650) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1651)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1652) static inline void hifn_complete_sa(struct hifn_device *dev, int i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1653) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1654) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1655)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1656) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1657) dev->sa[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1658) dev->started--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1659) if (dev->started < 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1660) dev_info(&dev->pdev->dev, "%s: started: %d.\n", __func__,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1661) dev->started);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1662) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1663) BUG_ON(dev->started < 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1664) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1665)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1666) static void hifn_process_ready(struct skcipher_request *req, int error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1667) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1668) struct hifn_request_context *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1669)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1670) if (rctx->walk.flags & ASYNC_FLAGS_MISALIGNED) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1671) unsigned int nbytes = req->cryptlen;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1672) int idx = 0, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1673) struct scatterlist *dst, *t;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1674) void *saddr;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1675)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1676) while (nbytes) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1677) t = &rctx->walk.cache[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1678) dst = &req->dst[idx];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1679)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1680) pr_debug("\n%s: sg_page(t): %p, t->length: %u, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1681) "sg_page(dst): %p, dst->length: %u, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1682) "nbytes: %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1683) __func__, sg_page(t), t->length,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1684) sg_page(dst), dst->length, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1685)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1686) if (!t->length) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1687) nbytes -= min(dst->length, nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1688) idx++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1689) continue;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1690) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1692) saddr = kmap_atomic(sg_page(t));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1693)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1694) err = skcipher_get(saddr, &t->length, t->offset,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1695) dst, nbytes, &nbytes);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1696) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1697) kunmap_atomic(saddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1698) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1699) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1700)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1701) idx += err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1702) kunmap_atomic(saddr);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1703) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1704)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1705) hifn_cipher_walk_exit(&rctx->walk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1706) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1707)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1708) req->base.complete(&req->base, error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1709) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1710)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1711) static void hifn_clear_rings(struct hifn_device *dev, int error)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1712) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1713) struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1714) int i, u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1715)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1716) dev_dbg(&dev->pdev->dev, "ring cleanup 1: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1717) "k: %d.%d.%d.%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1718) dma->cmdi, dma->srci, dma->dsti, dma->resi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1719) dma->cmdu, dma->srcu, dma->dstu, dma->resu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1720) dma->cmdk, dma->srck, dma->dstk, dma->resk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1721)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1722) i = dma->resk; u = dma->resu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1723) while (u != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1724) if (dma->resr[i].l & __cpu_to_le32(HIFN_D_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1725) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1726)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1727) if (dev->sa[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1728) dev->success++;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1729) dev->reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1730) hifn_process_ready(dev->sa[i], error);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1731) hifn_complete_sa(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1732) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1733)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1734) if (++i == HIFN_D_RES_RSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1735) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1736) u--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1737) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1738) dma->resk = i; dma->resu = u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1739)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1740) i = dma->srck; u = dma->srcu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1741) while (u != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1742) if (dma->srcr[i].l & __cpu_to_le32(HIFN_D_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1743) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1744) if (++i == HIFN_D_SRC_RSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1745) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1746) u--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1747) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1748) dma->srck = i; dma->srcu = u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1749)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1750) i = dma->cmdk; u = dma->cmdu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1751) while (u != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1752) if (dma->cmdr[i].l & __cpu_to_le32(HIFN_D_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1753) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1754) if (++i == HIFN_D_CMD_RSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1755) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1756) u--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1757) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1758) dma->cmdk = i; dma->cmdu = u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1759)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1760) i = dma->dstk; u = dma->dstu;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1761) while (u != 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1762) if (dma->dstr[i].l & __cpu_to_le32(HIFN_D_VALID))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1763) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1764) if (++i == HIFN_D_DST_RSIZE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1765) i = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1766) u--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1767) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1768) dma->dstk = i; dma->dstu = u;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1769)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1770) dev_dbg(&dev->pdev->dev, "ring cleanup 2: i: %d.%d.%d.%d, u: %d.%d.%d.%d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1771) "k: %d.%d.%d.%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1772) dma->cmdi, dma->srci, dma->dsti, dma->resi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1773) dma->cmdu, dma->srcu, dma->dstu, dma->resu,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1774) dma->cmdk, dma->srck, dma->dstk, dma->resk);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1775) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1776)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1777) static void hifn_work(struct work_struct *work)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1778) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1779) struct delayed_work *dw = to_delayed_work(work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1780) struct hifn_device *dev = container_of(dw, struct hifn_device, work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1781) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1782) int reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1783) u32 r = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1784)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1785) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1786) if (dev->active == 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1787) struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1788)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1789) if (dma->cmdu == 0 && (dev->flags & HIFN_FLAG_CMD_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1790) dev->flags &= ~HIFN_FLAG_CMD_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1791) r |= HIFN_DMACSR_C_CTRL_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1792) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1793) if (dma->srcu == 0 && (dev->flags & HIFN_FLAG_SRC_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1794) dev->flags &= ~HIFN_FLAG_SRC_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1795) r |= HIFN_DMACSR_S_CTRL_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1796) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1797) if (dma->dstu == 0 && (dev->flags & HIFN_FLAG_DST_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1798) dev->flags &= ~HIFN_FLAG_DST_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1799) r |= HIFN_DMACSR_D_CTRL_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1800) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1801) if (dma->resu == 0 && (dev->flags & HIFN_FLAG_RES_BUSY)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1802) dev->flags &= ~HIFN_FLAG_RES_BUSY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1803) r |= HIFN_DMACSR_R_CTRL_DIS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1804) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1805) if (r)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1806) hifn_write_1(dev, HIFN_1_DMA_CSR, r);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1807) } else
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1808) dev->active--;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1809)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1810) if ((dev->prev_success == dev->success) && dev->started)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1811) reset = 1;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1812) dev->prev_success = dev->success;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1813) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1814)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1815) if (reset) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1816) if (++dev->reset >= 5) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1817) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1818) struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1819)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1820) dev_info(&dev->pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1821) "r: %08x, active: %d, started: %d, "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1822) "success: %lu: qlen: %u/%u, reset: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1823) r, dev->active, dev->started,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1824) dev->success, dev->queue.qlen, dev->queue.max_qlen,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1825) reset);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1826)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1827) dev_info(&dev->pdev->dev, "%s: res: ", __func__);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1828) for (i = 0; i < HIFN_D_RES_RSIZE; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1829) pr_info("%x.%p ", dma->resr[i].l, dev->sa[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1830) if (dev->sa[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1831) hifn_process_ready(dev->sa[i], -ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1832) hifn_complete_sa(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1833) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1834) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1835) pr_info("\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1836)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1837) hifn_reset_dma(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1838) hifn_stop_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1839) hifn_start_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1840) dev->reset = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1841) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1842)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1843) tasklet_schedule(&dev->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1844) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1845)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1846) schedule_delayed_work(&dev->work, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1847) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1848)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1849) static irqreturn_t hifn_interrupt(int irq, void *data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1850) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1851) struct hifn_device *dev = (struct hifn_device *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1852) struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1853) u32 dmacsr, restart;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1854)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1855) dmacsr = hifn_read_1(dev, HIFN_1_DMA_CSR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1856)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1857) dev_dbg(&dev->pdev->dev, "1 dmacsr: %08x, dmareg: %08x, res: %08x [%d], "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1858) "i: %d.%d.%d.%d, u: %d.%d.%d.%d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1859) dmacsr, dev->dmareg, dmacsr & dev->dmareg, dma->cmdi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1860) dma->cmdi, dma->srci, dma->dsti, dma->resi,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1861) dma->cmdu, dma->srcu, dma->dstu, dma->resu);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1862)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1863) if ((dmacsr & dev->dmareg) == 0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1864) return IRQ_NONE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1865)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1866) hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1867)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1868) if (dmacsr & HIFN_DMACSR_ENGINE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1869) hifn_write_0(dev, HIFN_0_PUISR, hifn_read_0(dev, HIFN_0_PUISR));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1870) if (dmacsr & HIFN_DMACSR_PUBDONE)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1871) hifn_write_1(dev, HIFN_1_PUB_STATUS,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1872) hifn_read_1(dev, HIFN_1_PUB_STATUS) | HIFN_PUBSTS_DONE);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1873)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1874) restart = dmacsr & (HIFN_DMACSR_R_OVER | HIFN_DMACSR_D_OVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1875) if (restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1876) u32 puisr = hifn_read_0(dev, HIFN_0_PUISR);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1877)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1878) dev_warn(&dev->pdev->dev, "overflow: r: %d, d: %d, puisr: %08x, d: %u.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1879) !!(dmacsr & HIFN_DMACSR_R_OVER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1880) !!(dmacsr & HIFN_DMACSR_D_OVER),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1881) puisr, !!(puisr & HIFN_PUISR_DSTOVER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1882) if (!!(puisr & HIFN_PUISR_DSTOVER))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1883) hifn_write_0(dev, HIFN_0_PUISR, HIFN_PUISR_DSTOVER);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1884) hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1885) HIFN_DMACSR_D_OVER));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1886) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1887)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1888) restart = dmacsr & (HIFN_DMACSR_C_ABORT | HIFN_DMACSR_S_ABORT |
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1889) HIFN_DMACSR_D_ABORT | HIFN_DMACSR_R_ABORT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1890) if (restart) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1891) dev_warn(&dev->pdev->dev, "abort: c: %d, s: %d, d: %d, r: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1892) !!(dmacsr & HIFN_DMACSR_C_ABORT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1893) !!(dmacsr & HIFN_DMACSR_S_ABORT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1894) !!(dmacsr & HIFN_DMACSR_D_ABORT),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1895) !!(dmacsr & HIFN_DMACSR_R_ABORT));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1896) hifn_reset_dma(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1897) hifn_init_dma(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1898) hifn_init_registers(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1899) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1900)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1901) if ((dmacsr & HIFN_DMACSR_C_WAIT) && (dma->cmdu == 0)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1902) dev_dbg(&dev->pdev->dev, "wait on command.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1903) dev->dmareg &= ~(HIFN_DMAIER_C_WAIT);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1904) hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1905) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1906)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1907) tasklet_schedule(&dev->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1908)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1909) return IRQ_HANDLED;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1910) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1911)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1912) static void hifn_flush(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1913) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1914) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1915) struct crypto_async_request *async_req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1916) struct skcipher_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1917) struct hifn_dma *dma = (struct hifn_dma *)dev->desc_virt;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1918) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1919)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1920) for (i = 0; i < HIFN_D_RES_RSIZE; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1921) struct hifn_desc *d = &dma->resr[i];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1922)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1923) if (dev->sa[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1924) hifn_process_ready(dev->sa[i],
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1925) (d->l & __cpu_to_le32(HIFN_D_VALID)) ? -ENODEV : 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1926) hifn_complete_sa(dev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1927) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1928) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1929)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1930) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1931) while ((async_req = crypto_dequeue_request(&dev->queue))) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1932) req = skcipher_request_cast(async_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1933) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1934)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1935) hifn_process_ready(req, -ENODEV);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1936)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1937) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1938) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1939) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1940) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1941)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1942) static int hifn_setkey(struct crypto_skcipher *cipher, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1943) unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1944) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1945) struct hifn_context *ctx = crypto_skcipher_ctx(cipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1946) struct hifn_device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1947) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1948)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1949) err = verify_skcipher_des_key(cipher, key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1950) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1951) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1952)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1953) dev->flags &= ~HIFN_FLAG_OLD_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1954)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1955) memcpy(ctx->key, key, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1956) ctx->keysize = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1957)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1958) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1959) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1960)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1961) static int hifn_des3_setkey(struct crypto_skcipher *cipher, const u8 *key,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1962) unsigned int len)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1963) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1964) struct hifn_context *ctx = crypto_skcipher_ctx(cipher);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1965) struct hifn_device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1966) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1967)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1968) err = verify_skcipher_des3_key(cipher, key);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1969) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1970) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1971)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1972) dev->flags &= ~HIFN_FLAG_OLD_KEY;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1973)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1974) memcpy(ctx->key, key, len);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1975) ctx->keysize = len;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1976)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1977) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1978) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1979)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1980) static int hifn_handle_req(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1981) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1982) struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1983) struct hifn_device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1984) int err = -EAGAIN;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1985)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1986) if (dev->started + DIV_ROUND_UP(req->cryptlen, PAGE_SIZE) <= HIFN_QUEUE_LENGTH)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1987) err = hifn_setup_session(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1988)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1989) if (err == -EAGAIN) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1990) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1991)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1992) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1993) err = crypto_enqueue_request(&dev->queue, &req->base);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1994) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1995) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1996)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1997) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1998) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1999)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2000) static int hifn_setup_crypto_req(struct skcipher_request *req, u8 op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2001) u8 type, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2002) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2003) struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2004) struct hifn_request_context *rctx = skcipher_request_ctx(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2005) unsigned ivsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2006)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2007) ivsize = crypto_skcipher_ivsize(crypto_skcipher_reqtfm(req));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2008)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2009) if (req->iv && mode != ACRYPTO_MODE_ECB) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2010) if (type == ACRYPTO_TYPE_AES_128)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2011) ivsize = HIFN_AES_IV_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2012) else if (type == ACRYPTO_TYPE_DES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2013) ivsize = HIFN_DES_KEY_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2014) else if (type == ACRYPTO_TYPE_3DES)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2015) ivsize = HIFN_3DES_KEY_LENGTH;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2016) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2017)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2018) if (ctx->keysize != 16 && type == ACRYPTO_TYPE_AES_128) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2019) if (ctx->keysize == 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2020) type = ACRYPTO_TYPE_AES_192;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2021) else if (ctx->keysize == 32)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2022) type = ACRYPTO_TYPE_AES_256;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2023) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2024)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2025) rctx->op = op;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2026) rctx->mode = mode;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2027) rctx->type = type;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2028) rctx->iv = req->iv;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2029) rctx->ivsize = ivsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2030)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2031) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2032) * HEAVY TODO: needs to kick Herbert XU to write documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2033) * HEAVY TODO: needs to kick Herbert XU to write documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2034) * HEAVY TODO: needs to kick Herbert XU to write documentation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2035) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2036)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2037) return hifn_handle_req(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2038) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2039)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2040) static int hifn_process_queue(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2041) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2042) struct crypto_async_request *async_req, *backlog;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2043) struct skcipher_request *req;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2044) unsigned long flags;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2045) int err = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2046)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2047) while (dev->started < HIFN_QUEUE_LENGTH) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2048) spin_lock_irqsave(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2049) backlog = crypto_get_backlog(&dev->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2050) async_req = crypto_dequeue_request(&dev->queue);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2051) spin_unlock_irqrestore(&dev->lock, flags);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2052)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2053) if (!async_req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2054) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2055)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2056) if (backlog)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2057) backlog->complete(backlog, -EINPROGRESS);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2058)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2059) req = skcipher_request_cast(async_req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2060)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2061) err = hifn_handle_req(req);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2062) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2063) break;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2064) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2065)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2066) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2067) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2068)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2069) static int hifn_setup_crypto(struct skcipher_request *req, u8 op,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2070) u8 type, u8 mode)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2071) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2072) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2073) struct hifn_context *ctx = crypto_tfm_ctx(req->base.tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2074) struct hifn_device *dev = ctx->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2075)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2076) err = hifn_setup_crypto_req(req, op, type, mode);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2077) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2078) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2079)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2080) if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2081) hifn_process_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2082)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2083) return -EINPROGRESS;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2084) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2085)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2086) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2087) * AES ecryption functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2088) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2089) static inline int hifn_encrypt_aes_ecb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2090) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2091) return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2092) ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2093) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2094) static inline int hifn_encrypt_aes_cbc(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2095) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2096) return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2097) ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2098) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2099) static inline int hifn_encrypt_aes_cfb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2101) return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2102) ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2103) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2104) static inline int hifn_encrypt_aes_ofb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2105) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2106) return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2107) ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2108) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2109)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2110) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2111) * AES decryption functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2112) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2113) static inline int hifn_decrypt_aes_ecb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2114) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2115) return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2116) ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2117) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2118) static inline int hifn_decrypt_aes_cbc(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2119) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2120) return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2121) ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2122) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2123) static inline int hifn_decrypt_aes_cfb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2124) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2125) return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2126) ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_CFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2127) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2128) static inline int hifn_decrypt_aes_ofb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2129) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2130) return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2131) ACRYPTO_TYPE_AES_128, ACRYPTO_MODE_OFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2132) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2133)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2134) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2135) * DES ecryption functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2136) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2137) static inline int hifn_encrypt_des_ecb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2138) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2139) return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2140) ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2141) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2142) static inline int hifn_encrypt_des_cbc(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2143) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2144) return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2145) ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2146) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2147) static inline int hifn_encrypt_des_cfb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2148) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2149) return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2150) ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2151) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2152) static inline int hifn_encrypt_des_ofb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2153) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2154) return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2155) ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2156) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2157)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2158) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2159) * DES decryption functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2160) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2161) static inline int hifn_decrypt_des_ecb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2162) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2163) return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2164) ACRYPTO_TYPE_DES, ACRYPTO_MODE_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2165) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2166) static inline int hifn_decrypt_des_cbc(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2167) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2168) return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2169) ACRYPTO_TYPE_DES, ACRYPTO_MODE_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2170) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2171) static inline int hifn_decrypt_des_cfb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2172) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2173) return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2174) ACRYPTO_TYPE_DES, ACRYPTO_MODE_CFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2175) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2176) static inline int hifn_decrypt_des_ofb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2177) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2178) return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2179) ACRYPTO_TYPE_DES, ACRYPTO_MODE_OFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2180) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2181)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2182) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2183) * 3DES ecryption functions.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2184) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2185) static inline int hifn_encrypt_3des_ecb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2186) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2187) return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2188) ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2189) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2190) static inline int hifn_encrypt_3des_cbc(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2191) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2192) return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2193) ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2194) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2195) static inline int hifn_encrypt_3des_cfb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2196) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2197) return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2198) ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2199) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2200) static inline int hifn_encrypt_3des_ofb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2201) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2202) return hifn_setup_crypto(req, ACRYPTO_OP_ENCRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2203) ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2204) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2205)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2206) /* 3DES decryption functions. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2207) static inline int hifn_decrypt_3des_ecb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2208) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2209) return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2210) ACRYPTO_TYPE_3DES, ACRYPTO_MODE_ECB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2211) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2212) static inline int hifn_decrypt_3des_cbc(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2213) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2214) return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2215) ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CBC);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2216) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2217) static inline int hifn_decrypt_3des_cfb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2218) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2219) return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2220) ACRYPTO_TYPE_3DES, ACRYPTO_MODE_CFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2221) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2222) static inline int hifn_decrypt_3des_ofb(struct skcipher_request *req)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2223) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2224) return hifn_setup_crypto(req, ACRYPTO_OP_DECRYPT,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2225) ACRYPTO_TYPE_3DES, ACRYPTO_MODE_OFB);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2226) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2227)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2228) struct hifn_alg_template {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2229) char name[CRYPTO_MAX_ALG_NAME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2230) char drv_name[CRYPTO_MAX_ALG_NAME];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2231) unsigned int bsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2232) struct skcipher_alg skcipher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2233) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2234)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2235) static const struct hifn_alg_template hifn_alg_templates[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2236) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2237) * 3DES ECB, CBC, CFB and OFB modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2238) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2239) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2240) .name = "cfb(des3_ede)", .drv_name = "cfb-3des", .bsize = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2241) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2242) .min_keysize = HIFN_3DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2243) .max_keysize = HIFN_3DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2244) .setkey = hifn_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2245) .encrypt = hifn_encrypt_3des_cfb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2246) .decrypt = hifn_decrypt_3des_cfb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2247) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2248) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2249) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2250) .name = "ofb(des3_ede)", .drv_name = "ofb-3des", .bsize = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2251) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2252) .min_keysize = HIFN_3DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2253) .max_keysize = HIFN_3DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2254) .setkey = hifn_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2255) .encrypt = hifn_encrypt_3des_ofb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2256) .decrypt = hifn_decrypt_3des_ofb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2257) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2258) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2259) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2260) .name = "cbc(des3_ede)", .drv_name = "cbc-3des", .bsize = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2261) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2262) .ivsize = HIFN_IV_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2263) .min_keysize = HIFN_3DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2264) .max_keysize = HIFN_3DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2265) .setkey = hifn_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2266) .encrypt = hifn_encrypt_3des_cbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2267) .decrypt = hifn_decrypt_3des_cbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2268) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2269) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2270) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2271) .name = "ecb(des3_ede)", .drv_name = "ecb-3des", .bsize = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2272) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2273) .min_keysize = HIFN_3DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2274) .max_keysize = HIFN_3DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2275) .setkey = hifn_des3_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2276) .encrypt = hifn_encrypt_3des_ecb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2277) .decrypt = hifn_decrypt_3des_ecb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2278) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2279) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2280)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2281) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2282) * DES ECB, CBC, CFB and OFB modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2283) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2284) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2285) .name = "cfb(des)", .drv_name = "cfb-des", .bsize = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2286) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2287) .min_keysize = HIFN_DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2288) .max_keysize = HIFN_DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2289) .setkey = hifn_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2290) .encrypt = hifn_encrypt_des_cfb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2291) .decrypt = hifn_decrypt_des_cfb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2292) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2293) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2294) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2295) .name = "ofb(des)", .drv_name = "ofb-des", .bsize = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2296) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2297) .min_keysize = HIFN_DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2298) .max_keysize = HIFN_DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2299) .setkey = hifn_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2300) .encrypt = hifn_encrypt_des_ofb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2301) .decrypt = hifn_decrypt_des_ofb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2302) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2303) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2304) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2305) .name = "cbc(des)", .drv_name = "cbc-des", .bsize = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2306) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2307) .ivsize = HIFN_IV_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2308) .min_keysize = HIFN_DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2309) .max_keysize = HIFN_DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2310) .setkey = hifn_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2311) .encrypt = hifn_encrypt_des_cbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2312) .decrypt = hifn_decrypt_des_cbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2313) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2314) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2315) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2316) .name = "ecb(des)", .drv_name = "ecb-des", .bsize = 8,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2317) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2318) .min_keysize = HIFN_DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2319) .max_keysize = HIFN_DES_KEY_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2320) .setkey = hifn_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2321) .encrypt = hifn_encrypt_des_ecb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2322) .decrypt = hifn_decrypt_des_ecb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2323) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2324) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2325)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2326) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2327) * AES ECB, CBC, CFB and OFB modes.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2328) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2329) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2330) .name = "ecb(aes)", .drv_name = "ecb-aes", .bsize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2331) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2332) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2333) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2334) .setkey = hifn_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2335) .encrypt = hifn_encrypt_aes_ecb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2336) .decrypt = hifn_decrypt_aes_ecb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2337) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2338) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2339) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2340) .name = "cbc(aes)", .drv_name = "cbc-aes", .bsize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2341) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2342) .ivsize = HIFN_AES_IV_LENGTH,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2343) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2344) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2345) .setkey = hifn_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2346) .encrypt = hifn_encrypt_aes_cbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2347) .decrypt = hifn_decrypt_aes_cbc,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2348) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2349) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2350) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2351) .name = "cfb(aes)", .drv_name = "cfb-aes", .bsize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2352) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2353) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2354) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2355) .setkey = hifn_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2356) .encrypt = hifn_encrypt_aes_cfb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2357) .decrypt = hifn_decrypt_aes_cfb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2358) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2359) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2360) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2361) .name = "ofb(aes)", .drv_name = "ofb-aes", .bsize = 16,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2362) .skcipher = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2363) .min_keysize = AES_MIN_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2364) .max_keysize = AES_MAX_KEY_SIZE,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2365) .setkey = hifn_setkey,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2366) .encrypt = hifn_encrypt_aes_ofb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2367) .decrypt = hifn_decrypt_aes_ofb,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2368) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2369) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2370) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2371)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2372) static int hifn_init_tfm(struct crypto_skcipher *tfm)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2373) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2374) struct skcipher_alg *alg = crypto_skcipher_alg(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2375) struct hifn_crypto_alg *ha = crypto_alg_to_hifn(alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2376) struct hifn_context *ctx = crypto_skcipher_ctx(tfm);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2377)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2378) ctx->dev = ha->dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2379) crypto_skcipher_set_reqsize(tfm, sizeof(struct hifn_request_context));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2380)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2381) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2382) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2383)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2384) static int hifn_alg_alloc(struct hifn_device *dev, const struct hifn_alg_template *t)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2385) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2386) struct hifn_crypto_alg *alg;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2387) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2388)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2389) alg = kzalloc(sizeof(*alg), GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2390) if (!alg)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2391) return -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2392)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2393) alg->alg = t->skcipher;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2394) alg->alg.init = hifn_init_tfm;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2395)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2396) snprintf(alg->alg.base.cra_name, CRYPTO_MAX_ALG_NAME, "%s", t->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2397) snprintf(alg->alg.base.cra_driver_name, CRYPTO_MAX_ALG_NAME, "%s-%s",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2398) t->drv_name, dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2399)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2400) alg->alg.base.cra_priority = 300;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2401) alg->alg.base.cra_flags = CRYPTO_ALG_KERN_DRIVER_ONLY | CRYPTO_ALG_ASYNC;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2402) alg->alg.base.cra_blocksize = t->bsize;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2403) alg->alg.base.cra_ctxsize = sizeof(struct hifn_context);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2404) alg->alg.base.cra_alignmask = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2405) alg->alg.base.cra_module = THIS_MODULE;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2406)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2407) alg->dev = dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2408)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2409) list_add_tail(&alg->entry, &dev->alg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2410)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2411) err = crypto_register_skcipher(&alg->alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2412) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2413) list_del(&alg->entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2414) kfree(alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2415) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2416)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2417) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2418) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2419)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2420) static void hifn_unregister_alg(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2421) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2422) struct hifn_crypto_alg *a, *n;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2424) list_for_each_entry_safe(a, n, &dev->alg_list, entry) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2425) list_del(&a->entry);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2426) crypto_unregister_skcipher(&a->alg);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2427) kfree(a);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2428) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2429) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2430)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2431) static int hifn_register_alg(struct hifn_device *dev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2432) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2433) int i, err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2434)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2435) for (i = 0; i < ARRAY_SIZE(hifn_alg_templates); ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2436) err = hifn_alg_alloc(dev, &hifn_alg_templates[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2437) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2438) goto err_out_exit;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2439) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2440)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2441) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2442)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2443) err_out_exit:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2444) hifn_unregister_alg(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2445) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2446) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2447)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2448) static void hifn_tasklet_callback(unsigned long data)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2449) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2450) struct hifn_device *dev = (struct hifn_device *)data;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2451)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2452) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2453) * This is ok to call this without lock being held,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2454) * althogh it modifies some parameters used in parallel,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2455) * (like dev->success), but they are used in process
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2456) * context or update is atomic (like setting dev->sa[i] to NULL).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2457) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2458) hifn_clear_rings(dev, 0);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2459)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2460) if (dev->started < HIFN_QUEUE_LENGTH && dev->queue.qlen)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2461) hifn_process_queue(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2462) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2463)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2464) static int hifn_probe(struct pci_dev *pdev, const struct pci_device_id *id)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2465) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2466) int err, i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2467) struct hifn_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2468) char name[8];
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2469)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2470) err = pci_enable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2471) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2472) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2473) pci_set_master(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2474)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2475) err = dma_set_mask(&pdev->dev, DMA_BIT_MASK(32));
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2476) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2477) goto err_out_disable_pci_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2478)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2479) snprintf(name, sizeof(name), "hifn%d",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2480) atomic_inc_return(&hifn_dev_number) - 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2481)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2482) err = pci_request_regions(pdev, name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2483) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2484) goto err_out_disable_pci_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2485)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2486) if (pci_resource_len(pdev, 0) < HIFN_BAR0_SIZE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2487) pci_resource_len(pdev, 1) < HIFN_BAR1_SIZE ||
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2488) pci_resource_len(pdev, 2) < HIFN_BAR2_SIZE) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2489) dev_err(&pdev->dev, "Broken hardware - I/O regions are too small.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2490) err = -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2491) goto err_out_free_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2492) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2493)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2494) dev = kzalloc(sizeof(struct hifn_device) + sizeof(struct crypto_alg),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2495) GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2496) if (!dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2497) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2498) goto err_out_free_regions;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2499) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2500)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2501) INIT_LIST_HEAD(&dev->alg_list);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2502)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2503) snprintf(dev->name, sizeof(dev->name), "%s", name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2504) spin_lock_init(&dev->lock);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2505)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2506) for (i = 0; i < 3; ++i) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2507) unsigned long addr, size;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2508)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2509) addr = pci_resource_start(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2510) size = pci_resource_len(pdev, i);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2511)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2512) dev->bar[i] = ioremap(addr, size);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2513) if (!dev->bar[i]) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2514) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2515) goto err_out_unmap_bars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2516) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2517) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2518)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2519) dev->desc_virt = dma_alloc_coherent(&pdev->dev,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2520) sizeof(struct hifn_dma),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2521) &dev->desc_dma, GFP_KERNEL);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2522) if (!dev->desc_virt) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2523) dev_err(&pdev->dev, "Failed to allocate descriptor rings.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2524) err = -ENOMEM;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2525) goto err_out_unmap_bars;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2526) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2527)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2528) dev->pdev = pdev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2529) dev->irq = pdev->irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2530)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2531) for (i = 0; i < HIFN_D_RES_RSIZE; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2532) dev->sa[i] = NULL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2533)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2534) pci_set_drvdata(pdev, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2535)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2536) tasklet_init(&dev->tasklet, hifn_tasklet_callback, (unsigned long)dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2537)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2538) crypto_init_queue(&dev->queue, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2540) err = request_irq(dev->irq, hifn_interrupt, IRQF_SHARED, dev->name, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2541) if (err) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2542) dev_err(&pdev->dev, "Failed to request IRQ%d: err: %d.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2543) dev->irq, err);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2544) dev->irq = 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2545) goto err_out_free_desc;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2546) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2547)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2548) err = hifn_start_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2549) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2550) goto err_out_free_irq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2551)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2552) err = hifn_register_rng(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2553) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2554) goto err_out_stop_device;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2555)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2556) err = hifn_register_alg(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2557) if (err)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2558) goto err_out_unregister_rng;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2559)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2560) INIT_DELAYED_WORK(&dev->work, hifn_work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2561) schedule_delayed_work(&dev->work, HZ);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2562)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2563) dev_dbg(&pdev->dev, "HIFN crypto accelerator card at %s has been "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2564) "successfully registered as %s.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2565) pci_name(pdev), dev->name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2567) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2568)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2569) err_out_unregister_rng:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2570) hifn_unregister_rng(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2571) err_out_stop_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2572) hifn_reset_dma(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2573) hifn_stop_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2574) err_out_free_irq:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2575) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2576) tasklet_kill(&dev->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2577) err_out_free_desc:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2578) dma_free_coherent(&pdev->dev, sizeof(struct hifn_dma), dev->desc_virt,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2579) dev->desc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2580)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2581) err_out_unmap_bars:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2582) for (i = 0; i < 3; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2583) if (dev->bar[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2584) iounmap(dev->bar[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2585) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2586)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2587) err_out_free_regions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2588) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2589)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2590) err_out_disable_pci_device:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2591) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2592)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2593) return err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2594) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2595)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2596) static void hifn_remove(struct pci_dev *pdev)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2597) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2598) int i;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2599) struct hifn_device *dev;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2600)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2601) dev = pci_get_drvdata(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2602)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2603) if (dev) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2604) cancel_delayed_work_sync(&dev->work);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2605)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2606) hifn_unregister_rng(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2607) hifn_unregister_alg(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2608) hifn_reset_dma(dev, 1);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2609) hifn_stop_device(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2610)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2611) free_irq(dev->irq, dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2612) tasklet_kill(&dev->tasklet);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2613)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2614) hifn_flush(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2615)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2616) dma_free_coherent(&pdev->dev, sizeof(struct hifn_dma),
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2617) dev->desc_virt, dev->desc_dma);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2618) for (i = 0; i < 3; ++i)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2619) if (dev->bar[i])
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2620) iounmap(dev->bar[i]);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2621)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2622) kfree(dev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2623) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2624)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2625) pci_release_regions(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2626) pci_disable_device(pdev);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2627) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2628)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2629) static struct pci_device_id hifn_pci_tbl[] = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2630) { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7955) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2631) { PCI_DEVICE(PCI_VENDOR_ID_HIFN, PCI_DEVICE_ID_HIFN_7956) },
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2632) { 0 }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2633) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2634) MODULE_DEVICE_TABLE(pci, hifn_pci_tbl);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2635)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2636) static struct pci_driver hifn_pci_driver = {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2637) .name = "hifn795x",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2638) .id_table = hifn_pci_tbl,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2639) .probe = hifn_probe,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2640) .remove = hifn_remove,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2641) };
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2642)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2643) static int __init hifn_init(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2644) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2645) unsigned int freq;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2646) int err;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2647)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2648) if (strncmp(hifn_pll_ref, "ext", 3) &&
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2649) strncmp(hifn_pll_ref, "pci", 3)) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2650) pr_err("hifn795x: invalid hifn_pll_ref clock, must be pci or ext");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2651) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2652) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2653)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2654) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2655) * For the 7955/7956 the reference clock frequency must be in the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2656) * range of 20MHz-100MHz. For the 7954 the upper bound is 66.67MHz,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2657) * but this chip is currently not supported.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2658) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2659) if (hifn_pll_ref[3] != '\0') {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2660) freq = simple_strtoul(hifn_pll_ref + 3, NULL, 10);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2661) if (freq < 20 || freq > 100) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2662) pr_err("hifn795x: invalid hifn_pll_ref frequency, must"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2663) "be in the range of 20-100");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2664) return -EINVAL;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2665) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2666) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2667)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2668) err = pci_register_driver(&hifn_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2669) if (err < 0) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2670) pr_err("Failed to register PCI driver for %s device.\n",
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2671) hifn_pci_driver.name);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2672) return -ENODEV;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2673) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2674)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2675) pr_info("Driver for HIFN 795x crypto accelerator chip "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2676) "has been successfully registered.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2677)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2678) return 0;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2679) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2680)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2681) static void __exit hifn_fini(void)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2682) {
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2683) pci_unregister_driver(&hifn_pci_driver);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2684)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2685) pr_info("Driver for HIFN 795x crypto accelerator chip "
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2686) "has been successfully unregistered.\n");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2687) }
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2688)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2689) module_init(hifn_init);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2690) module_exit(hifn_fini);
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2691)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2692) MODULE_LICENSE("GPL");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2693) MODULE_AUTHOR("Evgeniy Polyakov <johnpol@2ka.mipt.ru>");
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2694) MODULE_DESCRIPTION("Driver for HIFN 795x crypto accelerator chip.");
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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